STM32 F7: Add RCC clock configuration logic from STM32 F429
This commit is contained in:
Gregory Nutt
parent
cbaf241078
commit
9c78772fce
@ -167,6 +167,10 @@ config STM32F7_I2C1
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default n
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select STM32F7_I2C
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config STM32F7_CEC
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bool "HDMI-CEC"
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default n
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config STM32F7_I2C2
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bool "I2C2"
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default n
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@ -177,6 +181,10 @@ config STM32F7_I2C3
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default n
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select STM32F7_I2C
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config STM32F7_LPTIM1
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bool "Low-power timer 1"
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default n
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config STM32F7_LTDC
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bool "LTDC"
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default n
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@ -204,10 +212,11 @@ config STM32F7_OTGHS
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default n
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select USBHOST_HAVE_ASYNCH if USBHOST
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config STM32F7_PWR
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bool "PWR"
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config STM32F7_QUADSPI
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bool "QuadSPI"
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default n
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config STM32F7_SAI1
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config STM32F7_RNG
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bool "RNG"
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default n
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@ -107,4 +107,4 @@ endif
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# Required STM32F7 files
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_irq.c stm32_start.c stm32_timerisr.c
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CHIP_CSRCS = stm32_irq.c stm32_rcc.c stm32_start.c stm32_timerisr.c
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@ -50,4 +50,3 @@
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#endif
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_GPIO_H */
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@ -50,4 +50,3 @@
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#endif
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_MEMORYMAP_H */
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175
arch/arm/src/stm32f7/stm32_rcc.c
Normal file
175
arch/arm/src/stm32f7/stm32_rcc.c
Normal file
@ -0,0 +1,175 @@
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/****************************************************************************
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* arch/arm/src/stm32f7/stm32_rcc.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_rcc.h"
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#include "stm32_flash.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/* Include chip-specific clocking initialization logic */
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# include "stm32f74xx75xx_rcc.c"
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#else
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# error "Unsupported STM32 F7 chip"
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_clockconfig
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*
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* Description:
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* Called to establish the clock settings based on the values in board.h.
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* This function (by default) will reset most everything, enable the PLL,
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* and enable peripheral clocking for all peripherals enabled in the NuttX
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* configurationfile.
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*
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* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking
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* will be enabled by an externally provided, board-specific function called
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* stm32_board_clockconfig().
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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void stm32_clockconfig(void)
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{
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/* Make sure that we are starting in the reset state */
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rcc_reset();
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#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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/* Invoke Board Custom Clock Configuration */
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stm32_board_clockconfig();
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#else
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/* Invoke standard, fixed clock configuration based on definitions in board.h */
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stm32_stdclockconfig();
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#endif
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/* Enable peripheral clocking */
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rcc_enableperipherals();
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}
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/************************************************************************************
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* Name: stm32_clockenable
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*
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* Description:
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* Re-enable the clock and restore the clock settings based on settings in board.h.
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* This function is only available to support low-power modes of operation: When
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* re-awakening from deep-sleep modes, it is necessary to re-enable/re-start the
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* PLL
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*
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* This functional performs a subset of the operations performed by
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* stm32_clockconfig(): It does not reset any devices, and it does not reset the
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* currenlty enabled peripheral clocks.
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*
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* If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking will
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* be enabled by an externally provided, board-specific function called
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* stm32_board_clockconfig().
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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#ifdef CONFIG_PM
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void stm32_clockenable(void)
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{
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#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG)
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/* Invoke Board Custom Clock Configuration */
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stm32_board_clockconfig();
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#else
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/* Invoke standard, fixed clock configuration based on definitions in board.h */
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stm32_stdclockconfig();
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#endif
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}
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#endif
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870
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
Normal file
870
arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c
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@ -0,0 +1,870 @@
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/****************************************************************************
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* arch/arm/src/stm32f7/stm32f74xxx75xx_rcc.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "stm32_pwr.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway. Normally this is very fast, but I have seen at least one
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* board that required this long, long timeout for the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/* Same for HSI */
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#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
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/* HSE divisor to yield ~1MHz RTC clock */
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#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rcc_reset
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*
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* Description:
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* Reset the RCC clock configuration to the default reset state
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*
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****************************************************************************/
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static inline void rcc_reset(void)
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{
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uint32_t regval;
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/* Enable the Internal High Speed clock (HSI) */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_HSION;
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putreg32(regval, STM32_RCC_CR);
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/* Reset CFGR register */
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putreg32(0x00000000, STM32_RCC_CFGR);
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/* Reset HSION, HSEON, CSSON and PLLON bits */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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/* Reset PLLCFGR register to reset default */
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putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
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/* Reset HSEBYP bit */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP;
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putreg32(regval, STM32_RCC_CR);
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/* Disable all interrupts */
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putreg32(0x00000000, STM32_RCC_CIR);
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}
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/****************************************************************************
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* Name: rcc_enableahb1
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*
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* Description:
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* Enable selected AHB1 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb1(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the AHB1ENR register to enabled the
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* selected AHB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_AHB1ENR);
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/* Enable GPIOA, GPIOB, .... GPIOI*/
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#if STM32F7_NGPIO > 0
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regval |= (RCC_AHB1ENR_GPIOAEN
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#if STM32F7_NGPIO > 1
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| RCC_AHB1ENR_GPIOBEN
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#endif
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#if STM32F7_NGPIO > 2
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| RCC_AHB1ENR_GPIOCEN
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#endif
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#if STM32F7_NGPIO > 3
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| RCC_AHB1ENR_GPIODEN
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#endif
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#if STM32F7_NGPIO > 4
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| RCC_AHB1ENR_GPIOEEN
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#endif
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#if STM32F7_NGPIO > 5
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| RCC_AHB1ENR_GPIOFEN
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#endif
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#if STM32F7_NGPIO > 6
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| RCC_AHB1ENR_GPIOGEN
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#endif
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#if STM32F7_NGPIO > 7
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| RCC_AHB1ENR_GPIOHEN
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#endif
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#if STM32F7_NGPIO > 8
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| RCC_AHB1ENR_GPIOIEN
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#endif
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#if STM32F7_NGPIO > 9
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| RCC_AHB1ENR_GPIOJEN
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#endif
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#if STM32F7_NGPIO > 10
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| RCC_AHB1ENR_GPIOKEN
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#endif
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);
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#endif
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#ifdef CONFIG_STM32F7_CRC
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/* CRC clock enable */
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regval |= RCC_AHB1ENR_CRCEN;
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#endif
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#ifdef CONFIG_STM32F7_BKPSRAM
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/* Backup SRAM clock enable */
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regval |= RCC_AHB1ENR_BKPSRAMEN;
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#endif
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#ifdef CONFIG_ARMV7M_DTCM
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/* DTCM data RAM clock enable */
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regval |= RCC_AHB1ENR_DTCMRAMEN;
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#endif
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#ifdef CONFIG_STM32F7_DMA1
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/* DMA 1 clock enable */
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regval |= RCC_AHB1ENR_DMA1EN;
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#endif
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#ifdef CONFIG_STM32F7_DMA2
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/* DMA 2 clock enable */
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regval |= RCC_AHB1ENR_DMA2EN;
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#endif
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#ifdef CONFIG_STM32F7_DMA2D
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/* DMA2D clock */
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regval |= RCC_AHB1ENR_DMA2DEN;
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#endif
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#ifdef CONFIG_STM32F7_ETHMAC
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/* Ethernet MAC clocking */
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regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \
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RCC_AHB1ENR_ETHMACRXEN);
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#ifdef CONFIG_STM32F7_ETH_PTP
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/* Precision Time Protocol (PTP) */
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regval |= RCC_AHB1ENR_ETHMACPTPEN;
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#endif
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#endif
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#ifdef CONFIG_STM32F7_OTGHS
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/* USB OTG HS */
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regval |= RCC_AHB1ENR_OTGHSEN;
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#endif /* CONFIG_STM32F7_OTGHS */
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putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableahb2
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*
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* Description:
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* Enable selected AHB2 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb2(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the AHB2ENR register to enabled the
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* selected AHB2 peripherals.
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*/
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regval = getreg32(STM32_RCC_AHB2ENR);
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#ifdef CONFIG_STM32F7_DCMI
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/* Camera interface enable */
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regval |= RCC_AHB2ENR_DCMIEN;
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#endif
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#ifdef CONFIG_STM32F7_CRYP
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/* Cryptographic modules clock enable */
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regval |= RCC_AHB2ENR_CRYPEN;
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#endif
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#ifdef CONFIG_STM32F7_HASH
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/* Hash modules clock enable */
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regval |= RCC_AHB2ENR_HASHEN;
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#endif
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#ifdef CONFIG_STM32F7_RNG
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/* Random number generator clock enable */
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regval |= RCC_AHB2ENR_RNGEN;
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#endif
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#ifdef CONFIG_STM32F7_OTGFS
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/* USB OTG FS clock enable */
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regval |= RCC_AHB2ENR_OTGFSEN;
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#endif
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putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableahb3
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*
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* Description:
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* Enable selected AHB3 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb3(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the AHB3ENR register to enabled the
|
||||
* selected AHB3 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB3ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F7_FSMC
|
||||
/* Flexible static memory controller module clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_FSMCEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_QUADSPI
|
||||
/* FQuad SPI memory controller clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_QSPIEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb1
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB1 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb1(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB1ENR register to enabled the
|
||||
* selected APB1 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM2
|
||||
/* TIM2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM3
|
||||
/* TIM3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM4
|
||||
/* TIM4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM5
|
||||
/* TIM5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM6
|
||||
/* TIM6 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM7
|
||||
/* TIM7 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM7EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM12
|
||||
/* TIM12 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM12EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM13
|
||||
/* TIM13 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM13EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM14
|
||||
/* TIM14 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_TIM14EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_LPTIM1
|
||||
/* Low-power timer 1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_LPTIM1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_WWDG
|
||||
/* Window watchdog clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_WWDGEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI2
|
||||
/* SPI2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI3
|
||||
/* SPI3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPI3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPDIFRX
|
||||
/* SPDIFRX clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_SPDIFRXEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_USART2
|
||||
/* USART 2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USART2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_USART3
|
||||
/* USART3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_USART3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_UART4
|
||||
/* UART4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_UART5
|
||||
/* UART5 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C1
|
||||
/* I2C1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C2
|
||||
/* I2C2 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C3
|
||||
/* I2C3 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_I2C4
|
||||
/* I2C4 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_I2C4EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_CAN1
|
||||
/* CAN 1 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_CAN1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_CAN2
|
||||
/* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */
|
||||
|
||||
regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_CEC
|
||||
/* CEC clock enable. */
|
||||
|
||||
regval |= RCC_APB1ENR_CECEN;
|
||||
#endif
|
||||
|
||||
/* Power interface clock enable. The PWR block is always enabled so that
|
||||
* we can set the internal voltage regulator for maximum performance.
|
||||
*/
|
||||
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
|
||||
#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2)
|
||||
/* DAC interface clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_DACEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_UART7
|
||||
/* UART7 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART7EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_UART8
|
||||
/* UART8 clock enable */
|
||||
|
||||
regval |= RCC_APB1ENR_UART8EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableapb2
|
||||
*
|
||||
* Description:
|
||||
* Enable selected APB2 peripherals
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableapb2(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the appropriate bits in the APB2ENR register to enabled the
|
||||
* selected APB2 peripherals.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB2ENR);
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM1
|
||||
/* TIM1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM8
|
||||
/* TIM8 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM8EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_USART1
|
||||
/* USART1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_USART6
|
||||
/* USART6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_USART6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_ADC1
|
||||
/* ADC1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_ADC2
|
||||
/* ADC2 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_ADC3
|
||||
/* ADC3 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_ADC3EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SDMMC1
|
||||
/* SDIO clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI1
|
||||
/* SPI1 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI4
|
||||
/* SPI4 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI4EN;
|
||||
#endif
|
||||
|
||||
/* System configuration controller clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SYSCFGEN;
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM9
|
||||
/* TIM9 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM9EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM10
|
||||
/* TIM10 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM10EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_TIM11
|
||||
/* TIM11 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_TIM11EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI5
|
||||
/* SPI5 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI5EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SPI6
|
||||
/* SPI6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SPI6EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SAI1
|
||||
/* SPI6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SAI1EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_SAI2
|
||||
/* SPI6 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SAI2EN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32F7_LTDC
|
||||
/* LTDC clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_LTDCEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
* NOTE: This logic would need to be extended if you need to select low-
|
||||
* power clocking modes!
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
|
||||
static void stm32_stdclockconfig(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
/* Enable Internal High-Speed Clock (HSI) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSION; /* Enable HSI */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSI is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSIRDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
/* Enable External High-Speed Clock (HSE) */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSEON; /* Enable HSE */
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the HSE is ready (or until a timeout elapsed) */
|
||||
|
||||
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the HSERDY flag is the set in the CR */
|
||||
|
||||
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Check for a timeout. If this timeout occurs, then we are hosed. We
|
||||
* have no real back-up plan, although the following logic makes it look
|
||||
* as though we do.
|
||||
*/
|
||||
|
||||
if (timeout > 0)
|
||||
{
|
||||
/* Select regulator voltage output Scale 1 mode to support system
|
||||
* frequencies up to 168 MHz.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1ENR);
|
||||
regval |= RCC_APB1ENR_PWREN;
|
||||
putreg32(regval, STM32_RCC_APB1ENR);
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval &= ~PWR_CR_VOS_MASK;
|
||||
regval |= PWR_CR_VOS_SCALE_1;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
|
||||
/* Set the HCLK source/divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_HPRE_MASK;
|
||||
regval |= STM32_RCC_CFGR_HPRE;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK2 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE2_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE2;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Set the PCLK1 divider */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_PPRE1_MASK;
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
||||
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
#endif
|
||||
|
||||
/* Set the PLL dividers and multipliers to configure the main PLL */
|
||||
|
||||
#ifdef STM32_BOARD_USEHSI
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
|
||||
#else /* if STM32_BOARD_USEHSE */
|
||||
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
|
||||
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
|
||||
#endif
|
||||
putreg32(regval, STM32_RCC_PLLCFG);
|
||||
|
||||
/* Enable the main PLL */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLL is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
regval = getreg32(STM32_PWR_CR);
|
||||
regval |= PWR_CR_ODSWEN;
|
||||
putreg32(regval, STM32_PWR_CR);
|
||||
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
||||
|
||||
#ifdef CONFIG_STM32F7_FLASH_PREFETCH
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
||||
#else
|
||||
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
||||
#endif
|
||||
putreg32(regval, STM32_FLASH_ACR);
|
||||
|
||||
/* Select the main PLL as system clock source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~RCC_CFGR_SW_MASK;
|
||||
regval |= RCC_CFGR_SW_PLL;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
|
||||
{
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32F7_LTDC
|
||||
/* Configure PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_PLLSAICFGR);
|
||||
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
|
||||
putreg32(regval, STM32_RCC_PLLSAICFGR);
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR);
|
||||
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
|
||||
putreg32(regval, STM32_RCC_DCKCFGR);
|
||||
|
||||
/* Enable PLLSAI */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLSAION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLSAI is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
* be enabled: if the MCO1 pin selects LSE as source.
|
||||
*/
|
||||
|
||||
stm32_rcc_enablelse();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: rcc_enableperiphals
|
||||
****************************************************************************/
|
||||
|
||||
static inline void rcc_enableperipherals(void)
|
||||
{
|
||||
rcc_enableahb1();
|
||||
rcc_enableahb2();
|
||||
rcc_enableahb3();
|
||||
rcc_enableapb1();
|
||||
rcc_enableapb2();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
Loading…
Reference in New Issue
Block a user