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Name change: Change Cortex-M3 naming to ARMv7-M naming so support Cortex-M4

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3846 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-08-05 21:57:49 +00:00
parent 13c98be35b
commit 9c89c16a7c
71 changed files with 2558 additions and 2569 deletions
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4
ChangeLog
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@ -1986,4 +1986,8 @@
Add a directory structure to support the port to the Kinesis KwikStik-K40.
There is no real substance in the initial check-in; only the directory
structure and skeleton files.
* arch/arm/include/armv7-m, arch/arm/src/armv7-m, etc.: Rename all cortexm3
directories and files to armv7-m; Change name of of all CORTEXM3 constants
to ARMV7M. This is a major namespace change needed to cleanly support the
ARM Cortex-M4 which is also in the ARMv7 M Series (specifically, ARMv7E-M).

2
TODO
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@ -630,7 +630,7 @@ o ARM (arch/arm/)
Description: ARM interrupt handling performance could be improved in some
ways. One easy way is to use a pointer to the context save
area in current_regs instead of using up_copystate so much.
see handling of 'current_regs" in arch/arm/src/cortexm3/* for
see handling of 'current_regs" in arch/arm/src/armv7-m/* for
examples of how this might be done.
Status: Open
Priority: Low

4
arch/README.txt
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@ -144,8 +144,8 @@ arch/arm - ARM-based micro-controllers
arch/arm/src/arm and arch/arm/include/arm
Common ARM-specific logic
arch/arm/src/cortexm3 and arch/arm/include/cortexm3
Common Cortex-M3 logic
arch/arm/src/armv7-m and arch/arm/include/armv7-m
Common ARMv7-M logic (Cortex-M3 and Cortex-M4)
arch/arm/include/c5471 and arch/arm/src/c5471
TI TMS320C5471 (also called TMS320DM180 or just C5471).

8
arch/arm/include/cortexm3/irq.h → arch/arm/include/armv7-m/irq.h
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/cortexm3/irq.h
* arch/arm/include/armv7-m/irq.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@ -37,8 +37,8 @@
* through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
#define __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H
/****************************************************************************
* Included Files
@ -312,5 +312,5 @@ extern "C" {
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_IRQ_H */

8
arch/arm/include/cortexm3/syscall.h → arch/arm/include/armv7-m/syscall.h
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/cortexm3/syscall.h
* arch/arm/include/armv7-m/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@ -37,8 +37,8 @@
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H
#define __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
#define __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H
/****************************************************************************
* Included Files
@ -239,5 +239,5 @@ extern "C" {
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_INCLUDE_CORTEXM3_SYSCALL_H */
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SYSCALL_H */

6
arch/arm/include/irq.h
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@ -53,11 +53,11 @@
#include <arch/chip/irq.h>
/* Include ARM architecture-specific IRQ definitions (including register
* save structure and irqsave()/irqrestore() macros
* save structure and irqsave()/irqrestore() macros)
*/
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/irq.h>
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# include <arch/armv7-m/irq.h>
#else
# include <arch/arm/irq.h>
#endif

4
arch/arm/include/syscall.h
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@ -46,8 +46,8 @@
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/syscall.h>
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# include <arch/armv7-m/syscall.h>
#else
# include <arch/arm/syscall.h>
#endif

8
arch/arm/src/Makefile
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@ -37,11 +37,15 @@
-include chip/Make.defs
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(CONFIG_ARCH_CORTEXM3),y)
ARCH_SUBDIR = cortexm3
ifeq ($(CONFIG_ARCH_CORTEXM3),y) /* Cortex-M3 is ARMv7-M */
ARCH_SUBDIR = armv7-m
else
ifeq ($(CONFIG_ARCH_CORTEXM4),y) /* Cortex-M4 is ARMv7E-M */
ARCH_SUBDIR = armv7-m
else
ARCH_SUBDIR = arm
endif
endif
ifeq ($(WINTOOL),y)
NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx}"

2
arch/arm/src/cortexm3/exc_return.h → arch/arm/src/armv7-m/exc_return.h
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@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/exc_return.h
* arch/arm/src/armv7-m/exc_return.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/mpu.h → arch/arm/src/armv7-m/mpu.h
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@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/mpu.h
* arch/arm/src/armv7-m/mpu.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

440
arch/arm/src/cortexm3/nvic.h → arch/arm/src/armv7-m/nvic.h
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@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/nvic.h
* arch/arm/src/armv7-m/nvic.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
#define __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H
#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H
#define __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H
/************************************************************************************
* Included Files
@ -48,7 +48,7 @@
/* NVIC base address ****************************************************************/
#define CORTEXM3_NVIC_BASE 0xe000e000
#define ARMV7M_NVIC_BASE 0xe000e000
/* NVIC register offsets ************************************************************/
@ -216,166 +216,166 @@
/* NVIC register addresses **********************************************************/
#define NVIC_INTCTRL_TYPE (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_TYPE_OFFSET)
#define NVIC_SYSTICK_CTRL (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
#define NVIC_SYSTICK_RELOAD (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
#define NVIC_SYSTICK_CURRENT (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
#define NVIC_SYSTICK_CALIB (CORTEXM3_NVIC_BASE + NVIC_SYSTICK_CALIB_OFFSET)
#define NVIC_INTCTRL_TYPE (ARMV7M_NVIC_BASE + NVIC_INTCTRL_TYPE_OFFSET)
#define NVIC_SYSTICK_CTRL (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
#define NVIC_SYSTICK_RELOAD (ARMV7M_NVIC_BASE + NVIC_SYSTICK_RELOAD_OFFSET)
#define NVIC_SYSTICK_CURRENT (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CURRENT_OFFSET)
#define NVIC_SYSTICK_CALIB (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CALIB_OFFSET)
#define NVIC_IRQ_ENABLE(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_ENABLE_OFFSET(n))
#define NVIC_IRQ0_31_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ENABLE_OFFSET)
#define NVIC_IRQ32_63_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ENABLE_OFFSET)
#define NVIC_IRQ64_95_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ENABLE_OFFSET)
#define NVIC_IRQ96_127_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ENABLE_OFFSET)
#define NVIC_IRQ128_159_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ENABLE_OFFSET)
#define NVIC_IRQ160_191_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ENABLE_OFFSET)
#define NVIC_IRQ192_223_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ENABLE_OFFSET)
#define NVIC_IRQ224_239_ENABLE (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ENABLE_OFFSET)
#define NVIC_IRQ_ENABLE(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_ENABLE_OFFSET(n))
#define NVIC_IRQ0_31_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_ENABLE_OFFSET)
#define NVIC_IRQ32_63_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_ENABLE_OFFSET)
#define NVIC_IRQ64_95_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_ENABLE_OFFSET)
#define NVIC_IRQ96_127_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_ENABLE_OFFSET)
#define NVIC_IRQ128_159_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_ENABLE_OFFSET)
#define NVIC_IRQ160_191_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_ENABLE_OFFSET)
#define NVIC_IRQ192_223_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_ENABLE_OFFSET)
#define NVIC_IRQ224_239_ENABLE (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_ENABLE_OFFSET)
#define NVIC_IRQ_CLEAR(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLEAR_OFFSET(n))
#define NVIC_IRQ0_31_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLEAR_OFFSET)
#define NVIC_IRQ32_63_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLEAR_OFFSET)
#define NVIC_IRQ64_95_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLEAR_OFFSET)
#define NVIC_IRQ96_127_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLEAR_OFFSET)
#define NVIC_IRQ128_159_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLEAR_OFFSET)
#define NVIC_IRQ160_191_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLEAR_OFFSET)
#define NVIC_IRQ192_223_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLEAR_OFFSET)
#define NVIC_IRQ224_239_CLEAR (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLEAR_OFFSET)
#define NVIC_IRQ_CLEAR(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_CLEAR_OFFSET(n))
#define NVIC_IRQ0_31_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_CLEAR_OFFSET)
#define NVIC_IRQ32_63_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_CLEAR_OFFSET)
#define NVIC_IRQ64_95_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_CLEAR_OFFSET)
#define NVIC_IRQ96_127_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_CLEAR_OFFSET)
#define NVIC_IRQ128_159_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_CLEAR_OFFSET)
#define NVIC_IRQ160_191_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_CLEAR_OFFSET)
#define NVIC_IRQ192_223_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_CLEAR_OFFSET)
#define NVIC_IRQ224_239_CLEAR (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_CLEAR_OFFSET)
#define NVIC_IRQ_PEND(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_PEND_OFFSET(n))
#define NVIC_IRQ0_31_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_PEND_OFFSET)
#define NVIC_IRQ32_63_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_PEND_OFFSET)
#define NVIC_IRQ64_95_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_PEND_OFFSET)
#define NVIC_IRQ96_127_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_PEND_OFFSET)
#define NVIC_IRQ128_159_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_PEND_OFFSET)
#define NVIC_IRQ160_191_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_PEND_OFFSET)
#define NVIC_IRQ192_223_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_PEND_OFFSET)
#define NVIC_IRQ224_239_PEND (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_PEND_OFFSET)
#define NVIC_IRQ_PEND(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_PEND_OFFSET(n))
#define NVIC_IRQ0_31_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_PEND_OFFSET)
#define NVIC_IRQ32_63_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_PEND_OFFSET)
#define NVIC_IRQ64_95_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_PEND_OFFSET)
#define NVIC_IRQ96_127_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_PEND_OFFSET)
#define NVIC_IRQ128_159_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_PEND_OFFSET)
#define NVIC_IRQ160_191_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_PEND_OFFSET)
#define NVIC_IRQ192_223_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_PEND_OFFSET)
#define NVIC_IRQ224_239_PEND (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_PEND_OFFSET)
#define NVIC_IRQ_CLRPEND(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_CLRPEND_OFFSET(n))
#define NVIC_IRQ0_31_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_CLRPEND_OFFSET)
#define NVIC_IRQ32_63_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_CLRPEND_OFFSET)
#define NVIC_IRQ64_95_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_CLRPEND_OFFSET)
#define NVIC_IRQ96_127_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_CLRPEND_OFFSET)
#define NVIC_IRQ128_159_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_CLRPEND_OFFSET)
#define NVIC_IRQ160_191_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_CLRPEND_OFFSET)
#define NVIC_IRQ192_223_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_CLRPEND_OFFSET)
#define NVIC_IRQ224_239_CLRPEND (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_CLRPEND_OFFSET)
#define NVIC_IRQ_CLRPEND(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_CLRPEND_OFFSET(n))
#define NVIC_IRQ0_31_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_CLRPEND_OFFSET)
#define NVIC_IRQ32_63_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_CLRPEND_OFFSET)
#define NVIC_IRQ64_95_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_CLRPEND_OFFSET)
#define NVIC_IRQ96_127_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_CLRPEND_OFFSET)
#define NVIC_IRQ128_159_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_CLRPEND_OFFSET)
#define NVIC_IRQ160_191_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_CLRPEND_OFFSET)
#define NVIC_IRQ192_223_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_CLRPEND_OFFSET)
#define NVIC_IRQ224_239_CLRPEND (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_CLRPEND_OFFSET)
#define NVIC_IRQ_ACTIVE(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_ACTIVE_OFFSET(n))
#define NVIC_IRQ0_31_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ0_31_ACTIVE_OFFSET)
#define NVIC_IRQ32_63_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ32_63_ACTIVE_OFFSET)
#define NVIC_IRQ64_95_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ64_95_ACTIVE_OFFSET)
#define NVIC_IRQ96_127_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ96_127_ACTIVE_OFFSET)
#define NVIC_IRQ128_159_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ128_159_ACTIVE_OFFSET)
#define NVIC_IRQ160_191_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ160_191_ACTIVE_OFFSET)
#define NVIC_IRQ192_223_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ192_223_ACTIVE_OFFSET)
#define NVIC_IRQ224_239_ACTIVE (CORTEXM3_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
#define NVIC_IRQ_ACTIVE(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_ACTIVE_OFFSET(n))
#define NVIC_IRQ0_31_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ0_31_ACTIVE_OFFSET)
#define NVIC_IRQ32_63_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ32_63_ACTIVE_OFFSET)
#define NVIC_IRQ64_95_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ64_95_ACTIVE_OFFSET)
#define NVIC_IRQ96_127_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ96_127_ACTIVE_OFFSET)
#define NVIC_IRQ128_159_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ128_159_ACTIVE_OFFSET)
#define NVIC_IRQ160_191_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ160_191_ACTIVE_OFFSET)
#define NVIC_IRQ192_223_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ192_223_ACTIVE_OFFSET)
#define NVIC_IRQ224_239_ACTIVE (ARMV7M_NVIC_BASE + NVIC_IRQ224_239_ACTIVE_OFFSET)
#define NVIC_IRQ_PRIORITY(n) (CORTEXM3_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
#define NVIC_IRQ0_3_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ0_3_PRIORITY_OFFSET)
#define NVIC_IRQ4_7_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ4_7_PRIORITY_OFFSET)
#define NVIC_IRQ8_11_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ8_11_PRIORITY_OFFSET)
#define NVIC_IRQ12_15_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ12_15_PRIORITY_OFFSET)
#define NVIC_IRQ16_19_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ16_19_PRIORITY_OFFSET)
#define NVIC_IRQ20_23_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ20_23_PRIORITY_OFFSET)
#define NVIC_IRQ24_27_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ24_27_PRIORITY_OFFSET)
#define NVIC_IRQ28_31_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ28_31_PRIORITY_OFFSET)
#define NVIC_IRQ32_35_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ32_35_PRIORITY_OFFSET)
#define NVIC_IRQ36_39_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ36_39_PRIORITY_OFFSET)
#define NVIC_IRQ40_43_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ40_43_PRIORITY_OFFSET)
#define NVIC_IRQ44_47_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ44_47_PRIORITY_OFFSET)
#define NVIC_IRQ48_51_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ48_51_PRIORITY_OFFSET)
#define NVIC_IRQ52_55_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ52_55_PRIORITY_OFFSET)
#define NVIC_IRQ56_59_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ56_59_PRIORITY_OFFSET)
#define NVIC_IRQ60_63_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ60_63_PRIORITY_OFFSET)
#define NVIC_IRQ64_67_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ64_67_PRIORITY_OFFSET)
#define NVIC_IRQ68_71_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ68_71_PRIORITY_OFFSET)
#define NVIC_IRQ72_75_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ72_75_PRIORITY_OFFSET)
#define NVIC_IRQ76_79_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ76_79_PRIORITY_OFFSET)
#define NVIC_IRQ80_83_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ80_83_PRIORITY_OFFSET)
#define NVIC_IRQ84_87_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ84_87_PRIORITY_OFFSET)
#define NVIC_IRQ88_91_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ88_91_PRIORITY_OFFSET)
#define NVIC_IRQ92_95_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ92_95_PRIORITY_OFFSET)
#define NVIC_IRQ96_99_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ96_99_PRIORITY_OFFSET)
#define NVIC_IRQ100_103_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ100_103_PRIORITY_OFFSET)
#define NVIC_IRQ104_107_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ104_107_PRIORITY_OFFSET)
#define NVIC_IRQ108_111_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ108_111_PRIORITY_OFFSET)
#define NVIC_IRQ112_115_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ112_115_PRIORITY_OFFSET)
#define NVIC_IRQ116_119_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ116_119_PRIORITY_OFFSET)
#define NVIC_IRQ120_123_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ120_123_PRIORITY_OFFSET)
#define NVIC_IRQ124_127_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ124_127_PRIORITY_OFFSET)
#define NVIC_IRQ128_131_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ128_131_PRIORITY_OFFSET)
#define NVIC_IRQ132_135_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ132_135_PRIORITY_OFFSET)
#define NVIC_IRQ136_139_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ136_139_PRIORITY_OFFSET)
#define NVIC_IRQ140_143_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ140_143_PRIORITY_OFFSET)
#define NVIC_IRQ144_147_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ144_147_PRIORITY_OFFSET)
#define NVIC_IRQ148_151_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ148_151_PRIORITY_OFFSET)
#define NVIC_IRQ152_155_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ152_155_PRIORITY_OFFSET)
#define NVIC_IRQ156_159_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ156_159_PRIORITY_OFFSET)
#define NVIC_IRQ160_163_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ160_163_PRIORITY_OFFSET)
#define NVIC_IRQ164_167_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ164_167_PRIORITY_OFFSET)
#define NVIC_IRQ168_171_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ168_171_PRIORITY_OFFSET)
#define NVIC_IRQ172_175_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ172_175_PRIORITY_OFFSET)
#define NVIC_IRQ176_179_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ176_179_PRIORITY_OFFSET)
#define NVIC_IRQ180_183_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ180_183_PRIORITY_OFFSET)
#define NVIC_IRQ184_187_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ184_187_PRIORITY_OFFSET)
#define NVIC_IRQ188_191_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ188_191_PRIORITY_OFFSET)
#define NVIC_IRQ192_195_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ192_195_PRIORITY_OFFSET)
#define NVIC_IRQ196_199_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ196_199_PRIORITY_OFFSET)
#define NVIC_IRQ200_203_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ200_203_PRIORITY_OFFSET)
#define NVIC_IRQ204_207_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ204_207_PRIORITY_OFFSET)
#define NVIC_IRQ208_211_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ208_211_PRIORITY_OFFSET)
#define NVIC_IRQ212_215_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ212_215_PRIORITY_OFFSET)
#define NVIC_IRQ216_219_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ216_219_PRIORITY_OFFSET)
#define NVIC_IRQ220_223_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ220_223_PRIORITY_OFFSET)
#define NVIC_IRQ224_227_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ224_227_PRIORITY_OFFSET)
#define NVIC_IRQ228_231_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
#define NVIC_IRQ232_235_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
#define NVIC_IRQ_PRIORITY(n) (ARMV7M_NVIC_BASE + NVIC_IRQ_PRIORITY_OFFSET(n))
#define NVIC_IRQ0_3_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ0_3_PRIORITY_OFFSET)
#define NVIC_IRQ4_7_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ4_7_PRIORITY_OFFSET)
#define NVIC_IRQ8_11_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ8_11_PRIORITY_OFFSET)
#define NVIC_IRQ12_15_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ12_15_PRIORITY_OFFSET)
#define NVIC_IRQ16_19_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ16_19_PRIORITY_OFFSET)
#define NVIC_IRQ20_23_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ20_23_PRIORITY_OFFSET)
#define NVIC_IRQ24_27_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ24_27_PRIORITY_OFFSET)
#define NVIC_IRQ28_31_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ28_31_PRIORITY_OFFSET)
#define NVIC_IRQ32_35_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ32_35_PRIORITY_OFFSET)
#define NVIC_IRQ36_39_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ36_39_PRIORITY_OFFSET)
#define NVIC_IRQ40_43_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ40_43_PRIORITY_OFFSET)
#define NVIC_IRQ44_47_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ44_47_PRIORITY_OFFSET)
#define NVIC_IRQ48_51_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ48_51_PRIORITY_OFFSET)
#define NVIC_IRQ52_55_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ52_55_PRIORITY_OFFSET)
#define NVIC_IRQ56_59_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ56_59_PRIORITY_OFFSET)
#define NVIC_IRQ60_63_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ60_63_PRIORITY_OFFSET)
#define NVIC_IRQ64_67_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ64_67_PRIORITY_OFFSET)
#define NVIC_IRQ68_71_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ68_71_PRIORITY_OFFSET)
#define NVIC_IRQ72_75_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ72_75_PRIORITY_OFFSET)
#define NVIC_IRQ76_79_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ76_79_PRIORITY_OFFSET)
#define NVIC_IRQ80_83_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ80_83_PRIORITY_OFFSET)
#define NVIC_IRQ84_87_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ84_87_PRIORITY_OFFSET)
#define NVIC_IRQ88_91_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ88_91_PRIORITY_OFFSET)
#define NVIC_IRQ92_95_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ92_95_PRIORITY_OFFSET)
#define NVIC_IRQ96_99_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ96_99_PRIORITY_OFFSET)
#define NVIC_IRQ100_103_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ100_103_PRIORITY_OFFSET)
#define NVIC_IRQ104_107_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ104_107_PRIORITY_OFFSET)
#define NVIC_IRQ108_111_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ108_111_PRIORITY_OFFSET)
#define NVIC_IRQ112_115_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ112_115_PRIORITY_OFFSET)
#define NVIC_IRQ116_119_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ116_119_PRIORITY_OFFSET)
#define NVIC_IRQ120_123_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ120_123_PRIORITY_OFFSET)
#define NVIC_IRQ124_127_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ124_127_PRIORITY_OFFSET)
#define NVIC_IRQ128_131_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ128_131_PRIORITY_OFFSET)
#define NVIC_IRQ132_135_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ132_135_PRIORITY_OFFSET)
#define NVIC_IRQ136_139_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ136_139_PRIORITY_OFFSET)
#define NVIC_IRQ140_143_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ140_143_PRIORITY_OFFSET)
#define NVIC_IRQ144_147_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ144_147_PRIORITY_OFFSET)
#define NVIC_IRQ148_151_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ148_151_PRIORITY_OFFSET)
#define NVIC_IRQ152_155_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ152_155_PRIORITY_OFFSET)
#define NVIC_IRQ156_159_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ156_159_PRIORITY_OFFSET)
#define NVIC_IRQ160_163_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ160_163_PRIORITY_OFFSET)
#define NVIC_IRQ164_167_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ164_167_PRIORITY_OFFSET)
#define NVIC_IRQ168_171_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ168_171_PRIORITY_OFFSET)
#define NVIC_IRQ172_175_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ172_175_PRIORITY_OFFSET)
#define NVIC_IRQ176_179_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ176_179_PRIORITY_OFFSET)
#define NVIC_IRQ180_183_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ180_183_PRIORITY_OFFSET)
#define NVIC_IRQ184_187_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ184_187_PRIORITY_OFFSET)
#define NVIC_IRQ188_191_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ188_191_PRIORITY_OFFSET)
#define NVIC_IRQ192_195_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ192_195_PRIORITY_OFFSET)
#define NVIC_IRQ196_199_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ196_199_PRIORITY_OFFSET)
#define NVIC_IRQ200_203_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ200_203_PRIORITY_OFFSET)
#define NVIC_IRQ204_207_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ204_207_PRIORITY_OFFSET)
#define NVIC_IRQ208_211_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ208_211_PRIORITY_OFFSET)
#define NVIC_IRQ212_215_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ212_215_PRIORITY_OFFSET)
#define NVIC_IRQ216_219_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ216_219_PRIORITY_OFFSET)
#define NVIC_IRQ220_223_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ220_223_PRIORITY_OFFSET)
#define NVIC_IRQ224_227_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ224_227_PRIORITY_OFFSET)
#define NVIC_IRQ228_231_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ228_231_PRIORITY_OFFSET)
#define NVIC_IRQ232_235_PRIORITY (ARMV7M_NVIC_BASE + NVIC_IRQ232_235_PRIORITY_OFFSET)
#define NVIC_CPUID_BASE (CORTEXM3_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
#define NVIC_INTCTRL (CORTEXM3_NVIC_BASE + NVIC_INTCTRL_OFFSET)
#define NVIC_VECTAB (CORTEXM3_NVIC_BASE + NVIC_VECTAB_OFFSET)
#define NVIC_AIRC (CORTEXM3_NVIC_BASE + NVIC_AIRC_OFFSET)
#define NVIC_SYSCON (CORTEXM3_NVIC_BASE + NVIC_SYSCON_OFFSET)
#define NVIC_CFGCON (CORTEXM3_NVIC_BASE + NVIC_CFGCON_OFFSET)
#define NVIC_SYSH_PRIORITY(n) (CORTEXM3_NVIC_BASE + NVIC_SYSH_PRIORITY_OFFSET(n))
#define NVIC_SYSH4_7_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
#define NVIC_SYSH8_11_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
#define NVIC_SYSH12_15_PRIORITY (CORTEXM3_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
#define NVIC_SYSHCON (CORTEXM3_NVIC_BASE + NVIC_SYSHCON_OFFSET)
#define NVIC_CFAULTS (CORTEXM3_NVIC_BASE + NVIC_CFAULTS_OFFSET)
#define NVIC_HFAULTS (CORTEXM3_NVIC_BASE + NVIC_HFAULTS_OFFSET)
#define NVIC_DFAULTS (CORTEXM3_NVIC_BASE + NVIC_DFAULTS_OFFSET)
#define NVIC_MEMMANAGE_ADDR (CORTEXM3_NVIC_BASE + NVIC_MEMMANAGE_ADDR_OFFSET)
#define NVIC_BFAULT_ADDR (CORTEXM3_NVIC_BASE + NVIC_BFAULT_ADDR_OFFSET)
#define NVIC_AFAULTS (CORTEXM3_NVIC_BASE + NVIC_AFAULTS_OFFSET)
#define NVIC_PFR0 (CORTEXM3_NVIC_BASE + NVIC_PFR0_OFFSET)
#define NVIC_PFR1 (CORTEXM3_NVIC_BASE + NVIC_PFR1_OFFSET)
#define NVIC_DFR0 (CORTEXM3_NVIC_BASE + NVIC_DFR0_OFFSET)
#define NVIC_AFR0 (CORTEXM3_NVIC_BASE + NVIC_AFR0_OFFSET)
#define NVIC_MMFR0 (CORTEXM3_NVIC_BASE + NVIC_MMFR0_OFFSET)
#define NVIC_MMFR1 (CORTEXM3_NVIC_BASE + NVIC_MMFR1_OFFSET)
#define NVIC_MMFR2 (CORTEXM3_NVIC_BASE + NVIC_MMFR2_OFFSET)
#define NVIC_MMFR3 (CORTEXM3_NVIC_BASE + NVIC_MMFR3_OFFSET)
#define NVIC_ISAR0 (CORTEXM3_NVIC_BASE + NVIC_ISAR0_OFFSET)
#define NVIC_ISAR1 (CORTEXM3_NVIC_BASE + NVIC_ISAR1_OFFSET)
#define NVIC_ISAR2 (CORTEXM3_NVIC_BASE + NVIC_ISAR2_OFFSET)
#define NVIC_ISAR3 (CORTEXM3_NVIC_BASE + NVIC_ISAR3_OFFSET)
#define NVIC_ISAR4 (CORTEXM3_NVIC_BASE + NVIC_ISAR4_OFFSET)
#define NVIC_STIR (CORTEXM3_NVIC_BASE + NVIC_STIR_OFFSET)
#define NVIC_PID4 (CORTEXM3_NVIC_BASE + NVIC_PID4_OFFSET)
#define NVIC_PID5 (CORTEXM3_NVIC_BASE + NVIC_PID5_OFFSET)
#define NVIC_PID6 (CORTEXM3_NVIC_BASE + NVIC_PID6_OFFSET)
#define NVIC_PID7 (CORTEXM3_NVIC_BASE + NVIC_PID7_OFFSET)
#define NVIC_PID0 (CORTEXM3_NVIC_BASE + NVIC_PID0_OFFSET)
#define NVIC_PID1 (CORTEXM3_NVIC_BASE + NVIC_PID1_OFFSET)
#define NVIC_PID2 (CORTEXM3_NVIC_BASE + NVIC_PID2_OFFSET)
#define NVIC_PID3 (CORTEXM3_NVIC_BASE + NVIC_PID3_OFFSET)
#define NVIC_CID0 (CORTEXM3_NVIC_BASE + NVIC_CID0_OFFSET)
#define NVIC_CID1 (CORTEXM3_NVIC_BASE + NVIC_CID1_OFFSET)
#define NVIC_CID2 (CORTEXM3_NVIC_BASE + NVIC_CID2_OFFSET)
#define NVIC_CID3 (CORTEXM3_NVIC_BASE + NVIC_CID3_OFFSET)
#define NVIC_CPUID_BASE (ARMV7M_NVIC_BASE + NVIC_CPUID_BASE_OFFSET)
#define NVIC_INTCTRL (ARMV7M_NVIC_BASE + NVIC_INTCTRL_OFFSET)
#define NVIC_VECTAB (ARMV7M_NVIC_BASE + NVIC_VECTAB_OFFSET)
#define NVIC_AIRC (ARMV7M_NVIC_BASE + NVIC_AIRC_OFFSET)
#define NVIC_SYSCON (ARMV7M_NVIC_BASE + NVIC_SYSCON_OFFSET)
#define NVIC_CFGCON (ARMV7M_NVIC_BASE + NVIC_CFGCON_OFFSET)
#define NVIC_SYSH_PRIORITY(n) (ARMV7M_NVIC_BASE + NVIC_SYSH_PRIORITY_OFFSET(n))
#define NVIC_SYSH4_7_PRIORITY (ARMV7M_NVIC_BASE + NVIC_SYSH4_7_PRIORITY_OFFSET)
#define NVIC_SYSH8_11_PRIORITY (ARMV7M_NVIC_BASE + NVIC_SYSH8_11_PRIORITY_OFFSET)
#define NVIC_SYSH12_15_PRIORITY (ARMV7M_NVIC_BASE + NVIC_SYSH12_15_PRIORITY_OFFSET)
#define NVIC_SYSHCON (ARMV7M_NVIC_BASE + NVIC_SYSHCON_OFFSET)
#define NVIC_CFAULTS (ARMV7M_NVIC_BASE + NVIC_CFAULTS_OFFSET)
#define NVIC_HFAULTS (ARMV7M_NVIC_BASE + NVIC_HFAULTS_OFFSET)
#define NVIC_DFAULTS (ARMV7M_NVIC_BASE + NVIC_DFAULTS_OFFSET)
#define NVIC_MEMMANAGE_ADDR (ARMV7M_NVIC_BASE + NVIC_MEMMANAGE_ADDR_OFFSET)
#define NVIC_BFAULT_ADDR (ARMV7M_NVIC_BASE + NVIC_BFAULT_ADDR_OFFSET)
#define NVIC_AFAULTS (ARMV7M_NVIC_BASE + NVIC_AFAULTS_OFFSET)
#define NVIC_PFR0 (ARMV7M_NVIC_BASE + NVIC_PFR0_OFFSET)
#define NVIC_PFR1 (ARMV7M_NVIC_BASE + NVIC_PFR1_OFFSET)
#define NVIC_DFR0 (ARMV7M_NVIC_BASE + NVIC_DFR0_OFFSET)
#define NVIC_AFR0 (ARMV7M_NVIC_BASE + NVIC_AFR0_OFFSET)
#define NVIC_MMFR0 (ARMV7M_NVIC_BASE + NVIC_MMFR0_OFFSET)
#define NVIC_MMFR1 (ARMV7M_NVIC_BASE + NVIC_MMFR1_OFFSET)
#define NVIC_MMFR2 (ARMV7M_NVIC_BASE + NVIC_MMFR2_OFFSET)
#define NVIC_MMFR3 (ARMV7M_NVIC_BASE + NVIC_MMFR3_OFFSET)
#define NVIC_ISAR0 (ARMV7M_NVIC_BASE + NVIC_ISAR0_OFFSET)
#define NVIC_ISAR1 (ARMV7M_NVIC_BASE + NVIC_ISAR1_OFFSET)
#define NVIC_ISAR2 (ARMV7M_NVIC_BASE + NVIC_ISAR2_OFFSET)
#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
#define NVIC_PID5 (ARMV7M_NVIC_BASE + NVIC_PID5_OFFSET)
#define NVIC_PID6 (ARMV7M_NVIC_BASE + NVIC_PID6_OFFSET)
#define NVIC_PID7 (ARMV7M_NVIC_BASE + NVIC_PID7_OFFSET)
#define NVIC_PID0 (ARMV7M_NVIC_BASE + NVIC_PID0_OFFSET)
#define NVIC_PID1 (ARMV7M_NVIC_BASE + NVIC_PID1_OFFSET)
#define NVIC_PID2 (ARMV7M_NVIC_BASE + NVIC_PID2_OFFSET)
#define NVIC_PID3 (ARMV7M_NVIC_BASE + NVIC_PID3_OFFSET)
#define NVIC_CID0 (ARMV7M_NVIC_BASE + NVIC_CID0_OFFSET)
#define NVIC_CID1 (ARMV7M_NVIC_BASE + NVIC_CID1_OFFSET)
#define NVIC_CID2 (ARMV7M_NVIC_BASE + NVIC_CID2_OFFSET)
#define NVIC_CID3 (ARMV7M_NVIC_BASE + NVIC_CID3_OFFSET)
/* NVIC register bit definitions ****************************************************/
@ -386,92 +386,92 @@
/* SysTick control and status register (SYSTICK_CTRL) */
#define NVIC_SYSTICK_CTRL_ENABLE (1 << 0) /* Bit 0: Enable */
#define NVIC_SYSTICK_CTRL_TICKINT (1 << 1) /* Bit 1: Tick interrupt */
#define NVIC_SYSTICK_CTRL_CLKSOURCE (1 << 2) /* Bit 2: Clock source */
#define NVIC_SYSTICK_CTRL_COUNTFLAG (1 << 16) /* Bit 16: Count Flag */
#define NVIC_SYSTICK_CTRL_ENABLE (1 << 0) /* Bit 0: Enable */
#define NVIC_SYSTICK_CTRL_TICKINT (1 << 1) /* Bit 1: Tick interrupt */
#define NVIC_SYSTICK_CTRL_CLKSOURCE (1 << 2) /* Bit 2: Clock source */
#define NVIC_SYSTICK_CTRL_COUNTFLAG (1 << 16) /* Bit 16: Count Flag */
/* SysTick reload value register (SYSTICK_RELOAD) */
#define NVIC_SYSTICK_RELOAD_SHIFT 0 /* Bits 23-0: Timer reload value */
#define NVIC_SYSTICK_RELOAD_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
#define NVIC_SYSTICK_RELOAD_SHIFT 0 /* Bits 23-0: Timer reload value */
#define NVIC_SYSTICK_RELOAD_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
/* SysTick current value registe (SYSTICK_CURRENT) */
#define NVIC_SYSTICK_CURRENT_SHIFT 0 /* Bits 23-0: Timer current value */
#define NVIC_SYSTICK_CURRENT_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
#define NVIC_SYSTICK_CURRENT_SHIFT 0 /* Bits 23-0: Timer current value */
#define NVIC_SYSTICK_CURRENT_MASK (0x00ffffff << NVIC_SYSTICK_RELOAD_SHIFT)
/* SysTick calibration value register (SYSTICK_CALIB) */
#define NVIC_SYSTICK_CALIB_TENMS_SHIFT 0 /* Bits 23-0: Calibration value */
#define NVIC_SYSTICK_CALIB_TENMS_MASK (0x00ffffff << NVIC_SYSTICK_CALIB_TENMS_SHIFT)
#define NVIC_SYSTICK_CALIB_SKEW (1 << 30) /* Bit 30: Calibration value inexact */
#define NVIC_SYSTICK_CALIB_NOREF (1 << 31) /* Bit 31: No external reference clock */
#define NVIC_SYSTICK_CALIB_TENMS_SHIFT 0 /* Bits 23-0: Calibration value */
#define NVIC_SYSTICK_CALIB_TENMS_MASK (0x00ffffff << NVIC_SYSTICK_CALIB_TENMS_SHIFT)
#define NVIC_SYSTICK_CALIB_SKEW (1 << 30) /* Bit 30: Calibration value inexact */
#define NVIC_SYSTICK_CALIB_NOREF (1 << 31) /* Bit 31: No external reference clock */
/* Interrupt control state register (INTCTRL) */
#define NVIC_INTCTRL_NMIPENDSET (1 << 31) /* Bit 31: Set pending NMI bit */
#define NVIC_INTCTRL_PENDSVSET (1 << 28) /* Bit 28: Set pending PendSV bit */
#define NVIC_INTCTRL_PENDSVCLR (1 << 27) /* Bit 27: Clear pending PendSV bit */
#define NVIC_INTCTRL_PENDSTSET (1 << 26) /* Bit 26: Set pending SysTick bit */
#define NVIC_INTCTRL_PENDSTCLR (1 << 25) /* Bit 25: Clear pending SysTick bit */
#define NVIC_INTCTRL_ISPREEMPOT (1 << 23) /* Bit 23: Pending active next cycle */
#define NVIC_INTCTRL_ISRPENDING (1 << 22) /* Bit 22: Interrupt pending flag */
#define NVIC_INTCTRL_VECTPENDING_SHIFT 12 /* Bits 21-12: Pending ISR number field */
#define NVIC_INTCTRL_VECTPENDING_MASK (0x3ff << NVIC_INTCTRL_VECTPENDING_SHIFT)
#define NVIC_INTCTRL_RETTOBASE (1 << 11) /* Bit 11: no other exceptions pending */
#define NVIC_INTCTRL_VECTACTIVE_SHIFT 0 /* Bits 8-0: Active ISR number */
#define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
#define NVIC_INTCTRL_NMIPENDSET (1 << 31) /* Bit 31: Set pending NMI bit */
#define NVIC_INTCTRL_PENDSVSET (1 << 28) /* Bit 28: Set pending PendSV bit */
#define NVIC_INTCTRL_PENDSVCLR (1 << 27) /* Bit 27: Clear pending PendSV bit */
#define NVIC_INTCTRL_PENDSTSET (1 << 26) /* Bit 26: Set pending SysTick bit */
#define NVIC_INTCTRL_PENDSTCLR (1 << 25) /* Bit 25: Clear pending SysTick bit */
#define NVIC_INTCTRL_ISPREEMPOT (1 << 23) /* Bit 23: Pending active next cycle */
#define NVIC_INTCTRL_ISRPENDING (1 << 22) /* Bit 22: Interrupt pending flag */
#define NVIC_INTCTRL_VECTPENDING_SHIFT 12 /* Bits 21-12: Pending ISR number field */
#define NVIC_INTCTRL_VECTPENDING_MASK (0x3ff << NVIC_INTCTRL_VECTPENDING_SHIFT)
#define NVIC_INTCTRL_RETTOBASE (1 << 11) /* Bit 11: no other exceptions pending */
#define NVIC_INTCTRL_VECTACTIVE_SHIFT 0 /* Bits 8-0: Active ISR number */
#define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
/* System handler 4-7 priority register */
#define NVIC_SYSH_PRIORITY_PR4_SHIFT 0
#define NVIC_SYSH_PRIORITY_PR4_MASK (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
#define NVIC_SYSH_PRIORITY_PR5_SHIFT 8
#define NVIC_SYSH_PRIORITY_PR5_MASK (0xff << NVIC_SYSH_PRIORITY_PR5_SHIFT)
#define NVIC_SYSH_PRIORITY_PR6_SHIFT 16
#define NVIC_SYSH_PRIORITY_PR6_MASK (0xff << NVIC_SYSH_PRIORITY_PR6_SHIFT)
#define NVIC_SYSH_PRIORITY_PR7_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR7_MASK (0xff << NVIC_SYSH_PRIORITY_PR7_SHIFT)
#define NVIC_SYSH_PRIORITY_PR4_SHIFT 0
#define NVIC_SYSH_PRIORITY_PR4_MASK (0xff << NVIC_SYSH_PRIORITY_PR4_SHIFT)
#define NVIC_SYSH_PRIORITY_PR5_SHIFT 8
#define NVIC_SYSH_PRIORITY_PR5_MASK (0xff << NVIC_SYSH_PRIORITY_PR5_SHIFT)
#define NVIC_SYSH_PRIORITY_PR6_SHIFT 16
#define NVIC_SYSH_PRIORITY_PR6_MASK (0xff << NVIC_SYSH_PRIORITY_PR6_SHIFT)
#define NVIC_SYSH_PRIORITY_PR7_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR7_MASK (0xff << NVIC_SYSH_PRIORITY_PR7_SHIFT)
/* System handler 8-11 priority register */
#define NVIC_SYSH_PRIORITY_PR8_SHIFT 0
#define NVIC_SYSH_PRIORITY_PR8_MASK (0xff << NVIC_SYSH_PRIORITY_PR8_SHIFT)
#define NVIC_SYSH_PRIORITY_PR9_SHIFT 8
#define NVIC_SYSH_PRIORITY_PR9_MASK (0xff << NVIC_SYSH_PRIORITY_PR9_SHIFT)
#define NVIC_SYSH_PRIORITY_PR10_SHIFT 16
#define NVIC_SYSH_PRIORITY_PR10_MASK (0xff << NVIC_SYSH_PRIORITY_PR10_SHIFT)
#define NVIC_SYSH_PRIORITY_PR11_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR11_MASK (0xff << NVIC_SYSH_PRIORITY_PR11_SHIFT)
#define NVIC_SYSH_PRIORITY_PR8_SHIFT 0
#define NVIC_SYSH_PRIORITY_PR8_MASK (0xff << NVIC_SYSH_PRIORITY_PR8_SHIFT)
#define NVIC_SYSH_PRIORITY_PR9_SHIFT 8
#define NVIC_SYSH_PRIORITY_PR9_MASK (0xff << NVIC_SYSH_PRIORITY_PR9_SHIFT)
#define NVIC_SYSH_PRIORITY_PR10_SHIFT 16
#define NVIC_SYSH_PRIORITY_PR10_MASK (0xff << NVIC_SYSH_PRIORITY_PR10_SHIFT)
#define NVIC_SYSH_PRIORITY_PR11_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR11_MASK (0xff << NVIC_SYSH_PRIORITY_PR11_SHIFT)
/* System handler 12-15 priority register */
#define NVIC_SYSH_PRIORITY_PR12_SHIFT 0
#define NVIC_SYSH_PRIORITY_PR12_MASK (0xff << NVIC_SYSH_PRIORITY_PR12_SHIFT)
#define NVIC_SYSH_PRIORITY_PR13_SHIFT 8
#define NVIC_SYSH_PRIORITY_PR13_MASK (0xff << NVIC_SYSH_PRIORITY_PR13_SHIFT)
#define NVIC_SYSH_PRIORITY_PR14_SHIFT 16
#define NVIC_SYSH_PRIORITY_PR14_MASK (0xff << NVIC_SYSH_PRIORITY_PR14_SHIFT)
#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
#define NVIC_SYSH_PRIORITY_PR12_SHIFT 0
#define NVIC_SYSH_PRIORITY_PR12_MASK (0xff << NVIC_SYSH_PRIORITY_PR12_SHIFT)
#define NVIC_SYSH_PRIORITY_PR13_SHIFT 8
#define NVIC_SYSH_PRIORITY_PR13_MASK (0xff << NVIC_SYSH_PRIORITY_PR13_SHIFT)
#define NVIC_SYSH_PRIORITY_PR14_SHIFT 16
#define NVIC_SYSH_PRIORITY_PR14_MASK (0xff << NVIC_SYSH_PRIORITY_PR14_SHIFT)
#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
/* System handler control and state register (SYSHCON) */
#define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */
#define NVIC_SYSHCON_BUSFAULTACT (1 << 1) /* Bit 1: BusFault is active */
#define NVIC_SYSHCON_USGFAULTACT (1 << 3) /* Bit 3: UsageFault is active */
#define NVIC_SYSHCON_SVCALLACT (1 << 7) /* Bit 7: SVCall is active */
#define NVIC_SYSHCON_MONITORACT (1 << 8) /* Bit 8: Monitor is active */
#define NVIC_SYSHCON_PENDSVACT (1 << 10) /* Bit 10: PendSV is active */
#define NVIC_SYSHCON_SYSTICKACT (1 << 11) /* Bit 11: SysTick is active */
#define NVIC_SYSHCON_USGFAULTPENDED (1 << 12) /* Bit 12: Usage fault is pended */
#define NVIC_SYSHCON_MEMFAULTPENDED (1 << 13) /* Bit 13: MemManage is pended */
#define NVIC_SYSHCON_BUSFAULTPENDED (1 << 14) /* Bit 14: BusFault is pended */
#define NVIC_SYSHCON_SVCALLPENDED (1 << 15) /* Bit 15: SVCall is pended */
#define NVIC_SYSHCON_MEMFAULTENA (1 << 16) /* Bit 16: MemFault enabled */
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
#define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */
#define NVIC_SYSHCON_BUSFAULTACT (1 << 1) /* Bit 1: BusFault is active */
#define NVIC_SYSHCON_USGFAULTACT (1 << 3) /* Bit 3: UsageFault is active */
#define NVIC_SYSHCON_SVCALLACT (1 << 7) /* Bit 7: SVCall is active */
#define NVIC_SYSHCON_MONITORACT (1 << 8) /* Bit 8: Monitor is active */
#define NVIC_SYSHCON_PENDSVACT (1 << 10) /* Bit 10: PendSV is active */
#define NVIC_SYSHCON_SYSTICKACT (1 << 11) /* Bit 11: SysTick is active */
#define NVIC_SYSHCON_USGFAULTPENDED (1 << 12) /* Bit 12: Usage fault is pended */
#define NVIC_SYSHCON_MEMFAULTPENDED (1 << 13) /* Bit 13: MemManage is pended */
#define NVIC_SYSHCON_BUSFAULTPENDED (1 << 14) /* Bit 14: BusFault is pended */
#define NVIC_SYSHCON_SVCALLPENDED (1 << 15) /* Bit 15: SVCall is pended */
#define NVIC_SYSHCON_MEMFAULTENA (1 << 16) /* Bit 16: MemFault enabled */
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
/************************************************************************************
* Public Types
@ -485,4 +485,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM3_NVIC_H */
#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H */

58
arch/arm/src/cortexm3/psr.h → arch/arm/src/armv7-m/psr.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/cortexm3/psr.h
* arch/arm/src/armv7-m/psr.h
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
#define __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H
#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H
#define __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H
/************************************************************************************
* Included Files
@ -46,42 +46,42 @@
/* Application Program Status Register (APSR) */
#define CORTEXM3_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
#define CORTEXM3_APSR_V (1 << 28) /* Bit 28: Overflow flag */
#define CORTEXM3_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
#define CORTEXM3_APSR_Z (1 << 30) /* Bit 30: Zero flag */
#define CORTEXM3_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
#define ARMV7M_APSR_Q (1 << 27) /* Bit 27: Sticky saturation flag */
#define ARMV7M_APSR_V (1 << 28) /* Bit 28: Overflow flag */
#define ARMV7M_APSR_C (1 << 29) /* Bit 29: Carry/borrow flag */
#define ARMV7M_APSR_Z (1 << 30) /* Bit 30: Zero flag */
#define ARMV7M_APSR_N (1 << 31) /* Bit 31: Negative, less than flag */
/* Interrupt Program Status Register (IPSR) */
#define CORTEXM3_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
#define CORTEXM3_IPSR_ISR_MASK (0x1ff << CORTEXM3_IPSR_ISR_SHIFT)
#define ARMV7M_IPSR_ISR_SHIFT 0 /* Bits 8-0: ISR number */
#define ARMV7M_IPSR_ISR_MASK (0x1ff << ARMV7M_IPSR_ISR_SHIFT)
/* Execution PSR Register (EPSR) */
#define CORTEXM3_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
#define CORTEXM3_EPSR_ICIIT1_MASK (3 << CORTEXM3_EPSR_ICIIT1_SHIFT)
#define CORTEXM3_EPSR_T (1 << 24) /* Bit 24: T-bit */
#define CORTEXM3_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
#define CORTEXM3_EPSR_ICIIT2_MASK (3 << CORTEXM3_EPSR_ICIIT2_SHIFT)
#define ARMV7M_EPSR_ICIIT1_SHIFT 10 /* Bits 15-10: Interrupt-Continuable-Instruction/If-Then bits */
#define ARMV7M_EPSR_ICIIT1_MASK (3 << ARMV7M_EPSR_ICIIT1_SHIFT)
#define ARMV7M_EPSR_T (1 << 24) /* Bit 24: T-bit */
#define ARMV7M_EPSR_ICIIT2_SHIFT 25 /* Bits 26-25: Interrupt-Continuable-Instruction/If-Then bits */
#define ARMV7M_EPSR_ICIIT2_MASK (3 << ARMV7M_EPSR_ICIIT2_SHIFT)
/* Save xPSR bits */
#define CORTEXM3_XPSR_ISR_SHIFT CORTEXM3_IPSR_ISR_SHIFT
#define CORTEXM3_XPSR_ISR_MASK CORTEXM3_IPSR_ISR_MASK
#define CORTEXM3_XPSR_ICIIT1_SHIFT CORTEXM3_EPSR_ICIIT1_SHIFT/
#define CORTEXM3_XPSR_ICIIT1_MASK CORTEXM3_EPSR_ICIIT1_MASK
#define CORTEXM3_XPSR_T CORTEXM3_EPSR_T
#define CORTEXM3_XPSR_ICIIT2_SHIFT CORTEXM3_EPSR_ICIIT2_SHIFT
#define CORTEXM3_XPSR_ICIIT2_MASK CORTEXM3_EPSR_ICIIT2_MASK
#define CORTEXM3_XPSR_Q CORTEXM3_APSR_Q
#define CORTEXM3_XPSR_V CORTEXM3_APSR_V
#define CORTEXM3_XPSR_C CORTEXM3_APSR_C
#define CORTEXM3_XPSR_Z CORTEXM3_APSR_Z
#define CORTEXM3_XPSR_N CORTEXM3_APSR_N
#define ARMV7M_XPSR_ISR_SHIFT ARMV7M_IPSR_ISR_SHIFT
#define ARMV7M_XPSR_ISR_MASK ARMV7M_IPSR_ISR_MASK
#define ARMV7M_XPSR_ICIIT1_SHIFT ARMV7M_EPSR_ICIIT1_SHIFT/
#define ARMV7M_XPSR_ICIIT1_MASK ARMV7M_EPSR_ICIIT1_MASK
#define ARMV7M_XPSR_T ARMV7M_EPSR_T
#define ARMV7M_XPSR_ICIIT2_SHIFT ARMV7M_EPSR_ICIIT2_SHIFT
#define ARMV7M_XPSR_ICIIT2_MASK ARMV7M_EPSR_ICIIT2_MASK
#define ARMV7M_XPSR_Q ARMV7M_APSR_Q
#define ARMV7M_XPSR_V ARMV7M_APSR_V
#define ARMV7M_XPSR_C ARMV7M_APSR_C
#define ARMV7M_XPSR_Z ARMV7M_APSR_Z
#define ARMV7M_XPSR_N ARMV7M_APSR_N
/************************************************************************************
* Inline Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_COMMON_CORTEXM_PSR_H */
#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_PSR_H */

2
arch/arm/src/cortexm3/svcall.h → arch/arm/src/armv7-m/svcall.h
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/svcall.h
* arch/arm/src/armv7-m/svcall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_assert.c → arch/arm/src/armv7-m/up_assert.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_assert.c
* arch/arm/src/armv7-m/up_assert.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_blocktask.c → arch/arm/src/armv7-m/up_blocktask.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_blocktask.c
* arch/arm/src/armv7-m/up_blocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_copystate.c → arch/arm/src/armv7-m/up_copystate.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_copystate.c
* arch/arm/src/armv7-m/up_copystate.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_doirq.c → arch/arm/src/armv7-m/up_doirq.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_doirq.c
* arch/arm/src/armv7-m/up_doirq.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_fullcontextrestore.S → arch/arm/src/armv7-m/up_fullcontextrestore.S
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/up_fullcontextrestore.S
* arch/arm/src/armv7-m/up_fullcontextrestore.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_hardfault.c → arch/arm/src/armv7-m/up_hardfault.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_hardfault.c
* arch/arm/src/armv7-m/up_hardfault.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

6
arch/arm/src/cortexm3/up_initialstate.c → arch/arm/src/armv7-m/up_initialstate.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_initialstate.c
* arch/arm/src/armv7-m/up_initialstate.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -99,7 +99,7 @@ void up_initial_state(_TCB *tcb)
/* Specify thumb mode */
xcp->regs[REG_XPSR] = CORTEXM3_XPSR_T;
xcp->regs[REG_XPSR] = ARMV7M_XPSR_T;
/* If this task is running PIC, then set the PIC base register to the
* address of the allocated D-Space region.

2
arch/arm/src/cortexm3/up_memfault.c → arch/arm/src/armv7-m/up_memfault.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_memfault.c
* arch/arm/src/armv7-m/up_memfault.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_mpu.c → arch/arm/src/armv7-m/up_mpu.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_mpu.c
* arch/arm/src/armv7-m/up_mpu.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_releasepending.c → arch/arm/src/armv7-m/up_releasepending.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_releasepending.c
* arch/arm/src/armv7-m/up_releasepending.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_reprioritizertr.c → arch/arm/src/armv7-m/up_reprioritizertr.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_reprioritizertr.c
* arch/arm/src/armv7-m/up_reprioritizertr.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_saveusercontext.S → arch/arm/src/armv7-m/up_saveusercontext.S
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/up_saveusercontext.S
* arch/arm/src/armv7-m/up_saveusercontext.S
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

8
arch/arm/src/cortexm3/up_schedulesigaction.c → arch/arm/src/armv7-m/up_schedulesigaction.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_schedulesigaction.c
* arch/arm/src/armv7-m/up_schedulesigaction.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -164,7 +164,7 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
current_regs[REG_PC] = (uint32_t)up_sigdeliver;
current_regs[REG_PRIMASK] = 1;
current_regs[REG_XPSR] = CORTEXM3_XPSR_T;
current_regs[REG_XPSR] = ARMV7M_XPSR_T;
/* And make sure that the saved context in the TCB
* is the same as the interrupt return context.
@ -198,7 +198,7 @@ void up_schedule_sigaction(_TCB *tcb, sig_deliver_t sigdeliver)
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
tcb->xcp.regs[REG_PRIMASK] = 1;
tcb->xcp.regs[REG_XPSR] = CORTEXM3_XPSR_T;
tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
}
irqrestore(flags);

2
arch/arm/src/cortexm3/up_sigdeliver.c → arch/arm/src/armv7-m/up_sigdeliver.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_sigdeliver.c
* arch/arm/src/armv7-m/up_sigdeliver.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_svcall.c → arch/arm/src/armv7-m/up_svcall.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_svcall.c
* arch/arm/src/armv7-m/up_svcall.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_switchcontext.S → arch/arm/src/armv7-m/up_switchcontext.S
View File

@ -1,5 +1,5 @@
/************************************************************************************
* arch/arm/src/cortexm3/up_switchcontext.S
* arch/arm/src/armv7-m/up_switchcontext.S
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

2
arch/arm/src/cortexm3/up_unblocktask.c → arch/arm/src/armv7-m/up_unblocktask.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_unblocktask.c
* arch/arm/src/armv7-m/up_unblocktask.c
*
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>

10
arch/arm/src/common/up_internal.h
View File

@ -82,7 +82,7 @@
* a referenced is passed to get the state from the TCB.
*/
#ifdef CONFIG_ARCH_CORTEXM3
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
# define up_savestate(regs) up_copystate(regs, (uint32_t*)current_regs)
# define up_restorestate(regs) (current_regs = regs)
#else
@ -121,7 +121,7 @@ extern uint32_t g_heapbase;
/* Address of the saved user stack pointer */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
# ifdef CONFIG_ARCH_CORTEXM3
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern void g_intstackbase;
# else
extern uint32_t g_userstack;
@ -180,14 +180,14 @@ extern void up_sigdeliver(void);
extern void up_irqinitialize(void);
extern void up_maskack_irq(int irq);
#ifdef CONFIG_ARCH_CORTEXM3
#if defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4)
extern uint32_t *up_doirq(int irq, uint32_t *regs);
extern int up_svcall(int irq, FAR void *context);
extern int up_hardfault(int irq, FAR void *context);
extern int up_memfault(int irq, FAR void *context);
#else /* CONFIG_ARCH_CORTEXM3 */
#else /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_doirq(int irq, uint32_t *regs);
#ifdef CONFIG_PAGING
@ -202,7 +202,7 @@ extern void up_prefetchabort(uint32_t *regs);
extern void up_syscall(uint32_t *regs);
extern void up_undefinedinsn(uint32_t *regs);
#endif /* CONFIG_ARCH_CORTEXM3 */
#endif /* CONFIG_ARCH_CORTEXM3 || CONFIG_ARCH_CORTEXM4 */
extern void up_vectorundefinsn(void);
extern void up_vectorswi(void);

4
arch/arm/src/kinetis/kinetis_memorymap.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/kinetis/kinetis_memorymap.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -61,7 +61,7 @@
# define KINETIS_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define KINETIS_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define KINETIS_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
#define KINETIS_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
#define KINETIS_CORTEXM4_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define KINETIS_SCS_BASE 0xe000e000
#define KINETIS_DEBUGMCU_BASE 0xe0042000

4
arch/arm/src/lm3s/lm3s_irq.c
View File

@ -320,7 +320,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM3S_IRQ_MEMFAULT);
#endif
@ -329,7 +329,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);

4
arch/arm/src/lpc17xx/lpc17_irq.c
View File

@ -308,7 +308,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LPC17_IRQ_MEMFAULT);
#endif
@ -317,7 +317,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(LPC17_IRQ_NMI, lpc17_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault);

2
arch/arm/src/lpc17xx/lpc17_memorymap.h
View File

@ -61,7 +61,7 @@
# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
#define LPC17_SCS_BASE 0xe000e000
#define LPC17_DEBUGMCU_BASE 0xe0042000

4
arch/arm/src/sam3u/sam3u_irq.c
View File

@ -301,7 +301,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM3U_IRQ_MEMFAULT);
#endif
@ -310,7 +310,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);

2
arch/arm/src/stm32/chip/stm32_memorymap.h
View File

@ -125,7 +125,7 @@
#define STM32_FSMC_BASE 0xa0000000
/* Other registers -- see cortexm3/nvic.h for standard Cortex-M3 registers in this
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
* address range
*/

4
arch/arm/src/stm32/stm32_irq.c
View File

@ -335,7 +335,7 @@ void up_irqinitialize(void)
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
#ifdef CONFIG_ARMV7M_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
up_enable_irq(STM32_IRQ_MEMFAULT);
#endif
@ -344,7 +344,7 @@ void up_irqinitialize(void)
#ifdef CONFIG_DEBUG
irq_attach(STM32_IRQ_NMI, stm32_nmi);
#ifndef CONFIG_CORTEXM3_MPU
#ifndef CONFIG_ARMV7M_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);

16
arch/hc/include/syscall.h
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/include/syscall.h
* arch/hc/include/syscall.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@ -37,21 +37,13 @@
* through include/syscall.h or include/sys/sycall.h
*/
#ifndef _ARCH_ARM_INCLUDE_SYSCALL_H
#define _ARCH_ARM_INCLUDE_SYSCALL_H
#ifndef _ARCH_HC_INCLUDE_SYSCALL_H
#define _ARCH_HC_INCLUDE_SYSCALL_H
/****************************************************************************
* Included Files
****************************************************************************/
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/irq.h>
#else
# include <arch/arm/irq.h>
#endif
/****************************************************************************
* Definitions
****************************************************************************/
@ -86,5 +78,5 @@ extern "C" {
#endif
#endif
#endif /* _ARCH_ARM_INCLUDE_SYSCALL_H */
#endif /* _ARCH_HC_INCLUDE_SYSCALL_H */

8
arch/z80/include/syscall.h
View File

@ -44,14 +44,6 @@
* Included Files
****************************************************************************/
/* Include ARM architecture-specific syscall macros */
#ifdef CONFIG_ARCH_CORTEXM3
# include <arch/cortexm3/syscall.h>
#else
# include <arch/arm/syscall.h>
#endif
/****************************************************************************
* Definitions
****************************************************************************/

5
configs/demo9s12ne64/src/Makefile
View File

@ -52,10 +52,9 @@ OBJS = $(AOBJS) $(COBJS)
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common
endif
all: libboard$(LIBEXT)

808
configs/detron/README.txt
View File

@ -1,404 +1,404 @@
README
^^^^^^
README for NuttX port to the Detron LPC1768 board from Decio Renno
(http://www.detroneletronica.com.br/)
Contents
^^^^^^^^
Internet Radio Detron Board
Development Environment
GNU Toolchain Options
IDEs
NuttX buildroot Toolchain
Detron Configuration Options
USB Host Configuration
Configurations
Internet Radio Detron Board
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Graphic display
Pin Port Function
58 P0(20) DI
59 P0(19) RW
49 P0(11) ENABLE
78 P0(7) D0
79 P0(6) D1
78 P0(5) D2
81 P0(4) D3
94 P1(1) D4
95 P1(0) D5
47 P0(1) D6
46 P0(0) D7
VS1003
Pin Port Function
65 P2(8) xreset
85 P4(29) dreq
82 P4(28) xdcs
63 P0(16) xcs
62 P0(15) sclk
60 P0(18) si
61 P0(17) so
USB
Pin Port Function
29 D+
30 D-
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment.
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The devkitARM GNU toolchain,
3. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the NuttX buildroot toolchain. However,
the make system is setup to default to use the devkitARM toolchain. To use
the CodeSourcery or devkitARM toolchain, you simply need add one of the
following configuration options to your .config (or defconfig) file:
CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
the PATH in the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
Linux native toolchains. There are several limitations to using a Windows based
toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had not effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
Support has been added for making dependencies with the windows-native toolchains.
That support can be enabled by modifying your Make.defs file as follows:
- MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
If you have problems with the dependency build (for example, if you are not
building on C:), then you may need to modify tools/mkdeps.sh
NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
^^^^
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project (There is a simple RIDE project
in the RIDE subdirectory).
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/lpc17x/lpc17_vectors.S.
NuttX buildroot Toolchain
^^^^^^^^^^^^^^^^^^^^^^^^^
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh detron/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-4.3.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
detailed PLUS some special instructions that you will need to follow if you
are building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: This is an OABI toolchain.
Detron Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
be set to:
CONFIG_ARCH=arm
CONFIG_ARCH_family - For use in C code:
CONFIG_ARCH_ARM=y
CONFIG_ARCH_architecture - For use in C code:
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
CONFIG_ARCH_CHIP=lpc17xx
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
CONFIG_ARCH_CHIP_LPC1768=y
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
CONFIG_ARCH_BOARD=detron (for the Detron board)
CONFIG_ARCH_BOARD_name - For use in C code
CONFIG_ARCH_BOARD_DETRON=y
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
of delay loops
CONFIG_ENDIAN_BIG - define if big endian (default is little
endian)
CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
CONFIG_DRAM_SIZE=(32*1024) (32Kb)
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
CONFIG_DRAM_START - The start address of installed DRAM
CONFIG_DRAM_START=0x10000000
CONFIG_DRAM_END - Last address+1 of installed RAM
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
cause a 100 second delay during boot-up. This 100 second delay
serves no purpose other than it allows you to calibratre
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LPC17_FLASH=n
LPC17xx specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
This specific the size of the receive buffer
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
being sent. This specific the size of the transmit buffer
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
CONFIG_UARTn_2STOP - Two stop bits
LPC17xx specific PHY/Ethernet device driver settings. These setting
also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
CONFIG_PHY_AUTONEG - Enable auto-negotion
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
the higest priority.
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
CONFIG_DEBUG.
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
Also needs CONFIG_DEBUG.
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
Automatically set if CONFIG_NET_IGMP is selected.
LPC17xx USB Device Configuration
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
Handle USB Start-Of-Frame events.
Enable reading SOF from interrupt handler vs. simply reading on demand.
Probably a bad idea... Unless there is some issue with sampling the SOF
from hardware asynchronously.
CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
Enable high priority interrupts. I have no idea why you might want to
do that
CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
Number of DMA descriptors to allocate in SRAM.
CONFIG_LPC17_USBDEV_DMA
Enable lpc17xx-specific DMA support
CONFIG_LPC17_USBDEV_NOVBUS
Define if the hardware implementation does not support the VBUS signal
CONFIG_LPC17_USBDEV_NOLED
Define if the hardware implementation does not support the LED output
LPC17xx USB Host Configuration
CONFIG_USBHOST_OHCIRAM_SIZE
Total size of OHCI RAM (in AHB SRAM Bank 1)
CONFIG_USBHOST_NEDS
Number of endpoint descriptors
CONFIG_USBHOST_NTDS
Number of transfer descriptors
CONFIG_USBHOST_TDBUFFERS
Number of transfer descriptor buffers
CONFIG_USBHOST_TDBUFSIZE
Size of one transfer descriptor buffer
CONFIG_USBHOST_IOBUFSIZE
Size of one end-user I/O buffer. This can be zero if the
application can guarantee that all end-user I/O buffers
reside in AHB SRAM.
Configurations
^^^^^^^^^^^^^^
Each Detron configuration is maintained in a sudirectory and can be
selected as follow:
cd tools
./configure.sh detron/<subdir>
cd -
. ./setenv.sh
Where <subdir> is one of the following:
hidkbd:
This configuration directory, performs a simple test of the USB host
HID keyboard class driver using the test logic in examples/hidkbd.
nsh:
Configures the NuttShell (nsh) located at examples/nsh. The
Configuration enables only the serial NSH interfaces.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.
README
^^^^^^
README for NuttX port to the Detron LPC1768 board from Decio Renno
(http://www.detroneletronica.com.br/)
Contents
^^^^^^^^
Internet Radio Detron Board
Development Environment
GNU Toolchain Options
IDEs
NuttX buildroot Toolchain
Detron Configuration Options
USB Host Configuration
Configurations
Internet Radio Detron Board
^^^^^^^^^^^^^^^^^^^^^^^^^^^
Graphic display
Pin Port Function
58 P0(20) DI
59 P0(19) RW
49 P0(11) ENABLE
78 P0(7) D0
79 P0(6) D1
78 P0(5) D2
81 P0(4) D3
94 P1(1) D4
95 P1(0) D5
47 P0(1) D6
46 P0(0) D7
VS1003
Pin Port Function
65 P2(8) xreset
85 P4(29) dreq
82 P4(28) xdcs
63 P0(16) xcs
62 P0(15) sclk
60 P0(18) si
61 P0(17) so
USB
Pin Port Function
29 D+
30 D-
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment.
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The devkitARM GNU toolchain,
3. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the NuttX buildroot toolchain. However,
the make system is setup to default to use the devkitARM toolchain. To use
the CodeSourcery or devkitARM toolchain, you simply need add one of the
following configuration options to your .config (or defconfig) file:
CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
the PATH in the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
Linux native toolchains. There are several limitations to using a Windows based
toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had not effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
Support has been added for making dependencies with the windows-native toolchains.
That support can be enabled by modifying your Make.defs file as follows:
- MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
If you have problems with the dependency build (for example, if you are not
building on C:), then you may need to modify tools/mkdeps.sh
NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
^^^^
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project (There is a simple RIDE project
in the RIDE subdirectory).
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/lpc17x/lpc17_vectors.S.
NuttX buildroot Toolchain
^^^^^^^^^^^^^^^^^^^^^^^^^
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh detron/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-4.3.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
detailed PLUS some special instructions that you will need to follow if you
are building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: This is an OABI toolchain.
Detron Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
be set to:
CONFIG_ARCH=arm
CONFIG_ARCH_family - For use in C code:
CONFIG_ARCH_ARM=y
CONFIG_ARCH_architecture - For use in C code:
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
CONFIG_ARCH_CHIP=lpc17xx
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
CONFIG_ARCH_CHIP_LPC1768=y
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
CONFIG_ARCH_BOARD=detron (for the Detron board)
CONFIG_ARCH_BOARD_name - For use in C code
CONFIG_ARCH_BOARD_DETRON=y
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
of delay loops
CONFIG_ENDIAN_BIG - define if big endian (default is little
endian)
CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
CONFIG_DRAM_SIZE=(32*1024) (32Kb)
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
CONFIG_DRAM_START - The start address of installed DRAM
CONFIG_DRAM_START=0x10000000
CONFIG_DRAM_END - Last address+1 of installed RAM
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
cause a 100 second delay during boot-up. This 100 second delay
serves no purpose other than it allows you to calibratre
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LPC17_FLASH=n
LPC17xx specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
This specific the size of the receive buffer
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
being sent. This specific the size of the transmit buffer
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
CONFIG_UARTn_2STOP - Two stop bits
LPC17xx specific PHY/Ethernet device driver settings. These setting
also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
CONFIG_PHY_AUTONEG - Enable auto-negotion
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
the higest priority.
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
CONFIG_DEBUG.
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
Also needs CONFIG_DEBUG.
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
Automatically set if CONFIG_NET_IGMP is selected.
LPC17xx USB Device Configuration
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
Handle USB Start-Of-Frame events.
Enable reading SOF from interrupt handler vs. simply reading on demand.
Probably a bad idea... Unless there is some issue with sampling the SOF
from hardware asynchronously.
CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
Enable high priority interrupts. I have no idea why you might want to
do that
CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
Number of DMA descriptors to allocate in SRAM.
CONFIG_LPC17_USBDEV_DMA
Enable lpc17xx-specific DMA support
CONFIG_LPC17_USBDEV_NOVBUS
Define if the hardware implementation does not support the VBUS signal
CONFIG_LPC17_USBDEV_NOLED
Define if the hardware implementation does not support the LED output
LPC17xx USB Host Configuration
CONFIG_USBHOST_OHCIRAM_SIZE
Total size of OHCI RAM (in AHB SRAM Bank 1)
CONFIG_USBHOST_NEDS
Number of endpoint descriptors
CONFIG_USBHOST_NTDS
Number of transfer descriptors
CONFIG_USBHOST_TDBUFFERS
Number of transfer descriptor buffers
CONFIG_USBHOST_TDBUFSIZE
Size of one transfer descriptor buffer
CONFIG_USBHOST_IOBUFSIZE
Size of one end-user I/O buffer. This can be zero if the
application can guarantee that all end-user I/O buffers
reside in AHB SRAM.
Configurations
^^^^^^^^^^^^^^
Each Detron configuration is maintained in a sudirectory and can be
selected as follow:
cd tools
./configure.sh detron/<subdir>
cd -
. ./setenv.sh
Where <subdir> is one of the following:
hidkbd:
This configuration directory, performs a simple test of the USB host
HID keyboard class driver using the test logic in examples/hidkbd.
nsh:
Configures the NuttShell (nsh) located at examples/nsh. The
Configuration enables only the serial NSH interfaces.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.

4
configs/detron/src/Makefile
View File

@ -53,9 +53,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/ea3131/README.txt
View File

@ -118,7 +118,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc31xx,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/arm, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

4
configs/ea3131/src/Makefile
View File

@ -71,9 +71,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/arm}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/arm
endif
all: libboard$(LIBEXT)

4
configs/eagle100/src/Makefile
View File

@ -52,9 +52,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/kwikstik-k40/README.txt
View File

@ -133,7 +133,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/k40,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

8
configs/kwikstik-k40/ostest/Make.defs
View File

@ -41,24 +41,24 @@ ifeq ($(CONFIG_KINETIS_CODESOURCERYW),y)
# CodeSourcery under Windows
CROSSDEV = arm-none-eabi-
WINTOOL = y
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=soft
endif
ifeq ($(CONFIG_KINETIS_CODESOURCERYL),y)
# CodeSourcery under Linux
CROSSDEV = arm-none-eabi-
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=soft
MAXOPTIMIZATION = -O2
endif
ifeq ($(CONFIG_KINETIS_DEVKITARM),y)
# devkitARM under Windows
CROSSDEV = arm-eabi-
WINTOOL = y
ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -mfloat-abi=soft
endif
ifeq ($(CONFIG_KINETIS_BUILDROOT),y)
# NuttX buildroot under Linux or Cygwin
CROSSDEV = arm-elf-
ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
ARCHCPUFLAGS = -mtune=cortex-m4 -march=armv7e-m -mfloat-abi=soft
MAXOPTIMIZATION = -Os
endif

4
configs/kwikstik-k40/src/Makefile
View File

@ -59,9 +59,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/lm3s6965-ek/README.txt
View File

@ -198,7 +198,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lm3s,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

4
configs/lm3s6965-ek/src/Makefile
View File

@ -56,9 +56,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/lm3s8962-ek/README.txt
View File

@ -187,7 +187,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lm3s,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

4
configs/lm3s8962-ek/src/Makefile
View File

@ -56,9 +56,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/lpcxpresso-lpc1768/README.txt
View File

@ -327,7 +327,7 @@ Code Red IDE
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

4
configs/lpcxpresso-lpc1768/src/Makefile
View File

@ -62,9 +62,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

806
configs/mbed/README.txt
View File

@ -1,403 +1,403 @@
README
^^^^^^
README for NuttX port to the mbed.org LPC1768 board (http://mbed.org/)
Contents
^^^^^^^^
Development Environment
GNU Toolchain Options
IDEs
NuttX buildroot Toolchain
USB Device Controller Functions
mbed Configuration Options
USB Host Configuration
Configurations
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment.
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The devkitARM GNU toolchain,
3. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the NuttX buildroot toolchain. However,
the make system is setup to default to use the devkitARM toolchain. To use
the CodeSourcery or devkitARM toolchain, you simply need add one of the
following configuration options to your .config (or defconfig) file:
CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
the PATH in the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
Linux native toolchains. There are several limitations to using a Windows based
toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had not effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
Support has been added for making dependencies with the windows-native toolchains.
That support can be enabled by modifying your Make.defs file as follows:
- MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
If you have problems with the dependency build (for example, if you are not
building on C:), then you may need to modify tools/mkdeps.sh
NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
^^^^
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project (There is a simple RIDE project
in the RIDE subdirectory).
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/lpc17x/lpc17_vectors.S.
NuttX buildroot Toolchain
^^^^^^^^^^^^^^^^^^^^^^^^^
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh mbed/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-4.3.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
detailed PLUS some special instructions that you will need to follow if you
are building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: This is an OABI toolchain.
mbed Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
be set to:
CONFIG_ARCH=arm
CONFIG_ARCH_family - For use in C code:
CONFIG_ARCH_ARM=y
CONFIG_ARCH_architecture - For use in C code:
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
CONFIG_ARCH_CHIP=lpc17xx
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
CONFIG_ARCH_CHIP_LPC1768=y
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
CONFIG_ARCH_BOARD=mbed (for the mbed.org board)
CONFIG_ARCH_BOARD_name - For use in C code
CONFIG_ARCH_BOARD_MBED=y
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
of delay loops
CONFIG_ENDIAN_BIG - define if big endian (default is little
endian)
CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
CONFIG_DRAM_SIZE=(32*1024) (32Kb)
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
CONFIG_DRAM_START - The start address of installed DRAM
CONFIG_DRAM_START=0x10000000
CONFIG_DRAM_END - Last address+1 of installed RAM
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
cause a 100 second delay during boot-up. This 100 second delay
serves no purpose other than it allows you to calibratre
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LPC17_FLASH=n
LPC17xx specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
This specific the size of the receive buffer
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
being sent. This specific the size of the transmit buffer
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
CONFIG_UARTn_2STOP - Two stop bits
LPC17xx specific PHY/Ethernet device driver settings. These setting
also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
CONFIG_PHY_AUTONEG - Enable auto-negotion
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
the higest priority.
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
CONFIG_DEBUG.
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
Also needs CONFIG_DEBUG.
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
Automatically set if CONFIG_NET_IGMP is selected.
LPC17xx USB Device Configuration
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
Handle USB Start-Of-Frame events.
Enable reading SOF from interrupt handler vs. simply reading on demand.
Probably a bad idea... Unless there is some issue with sampling the SOF
from hardware asynchronously.
CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
Enable high priority interrupts. I have no idea why you might want to
do that
CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
Number of DMA descriptors to allocate in SRAM.
CONFIG_LPC17_USBDEV_DMA
Enable lpc17xx-specific DMA support
CONFIG_LPC17_USBDEV_NOVBUS
Define if the hardware implementation does not support the VBUS signal
CONFIG_LPC17_USBDEV_NOLED
Define if the hardware implementation does not support the LED output
LPC17xx USB Host Configuration
CONFIG_USBHOST_OHCIRAM_SIZE
Total size of OHCI RAM (in AHB SRAM Bank 1)
CONFIG_USBHOST_NEDS
Number of endpoint descriptors
CONFIG_USBHOST_NTDS
Number of transfer descriptors
CONFIG_USBHOST_TDBUFFERS
Number of transfer descriptor buffers
CONFIG_USBHOST_TDBUFSIZE
Size of one transfer descriptor buffer
CONFIG_USBHOST_IOBUFSIZE
Size of one end-user I/O buffer. This can be zero if the
application can guarantee that all end-user I/O buffers
reside in AHB SRAM.
USB Host Configuration
^^^^^^^^^^^^^^^^^^^^^^
The mbed board can be easily modified to support a USB host interface
(Remember to add 2 resistors of 15K to D+ and D- pins). The hidkbd
configuration assumes that this change has been made.
The NuttShell (NSH) mbed can also be modified in order to support USB
host operations. To make these modifications, do the following:
1. First configure to build the NSH configuration from the top-level
NuttX directory:
cd tools
./configure mbed/nsh
cd ..
2. Then edit the top-level .config file to enable USB host. Make the
following changes:
CONFIG_LPC17_USBHOST=n
CONFIG_USBHOST=n
CONFIG_SCHED_WORKQUEUE=y
When this change is made, NSH should be extended to support USB flash
devices. When a FLASH device is inserted, you should see a device
appear in the /dev (psuedo) directory. The device name should be
like /dev/sda, /dev/sdb, etc. The USB mass storage device, is present
it can be mounted from the NSH command line like:
ls /dev
mount -t vfat /dev/sda /mnt/flash
Files on the connect USB flash device should then be accessible under
the mountpoint /mnt/flash.
Configurations
^^^^^^^^^^^^^^
Each mbed configuration is maintained in a sudirectory and can be selected
as follow:
cd tools
./configure.sh mbed/<subdir>
cd -
. ./setenv.sh
Where <subdir> is one of the following:
hidkbd:
This configuration directory, performs a simple test of the USB host
HID keyboard class driver using the test logic in examples/hidkbd.
This configuration assumes that you have modified your mbed for USB
host support.
nsh:
Configures the NuttShell (nsh) located at examples/nsh. The
Configuration enables only the serial NSH interfaces. See notes
above for enabling USB host support in this configuration.
README
^^^^^^
README for NuttX port to the mbed.org LPC1768 board (http://mbed.org/)
Contents
^^^^^^^^
Development Environment
GNU Toolchain Options
IDEs
NuttX buildroot Toolchain
USB Device Controller Functions
mbed Configuration Options
USB Host Configuration
Configurations
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment.
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The devkitARM GNU toolchain,
3. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the NuttX buildroot toolchain. However,
the make system is setup to default to use the devkitARM toolchain. To use
the CodeSourcery or devkitARM toolchain, you simply need add one of the
following configuration options to your .config (or defconfig) file:
CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
the PATH in the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
Linux native toolchains. There are several limitations to using a Windows based
toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had not effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
Support has been added for making dependencies with the windows-native toolchains.
That support can be enabled by modifying your Make.defs file as follows:
- MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
If you have problems with the dependency build (for example, if you are not
building on C:), then you may need to modify tools/mkdeps.sh
NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
^^^^
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project (There is a simple RIDE project
in the RIDE subdirectory).
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/lpc17x/lpc17_vectors.S.
NuttX buildroot Toolchain
^^^^^^^^^^^^^^^^^^^^^^^^^
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh mbed/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-4.3.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
detailed PLUS some special instructions that you will need to follow if you
are building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: This is an OABI toolchain.
mbed Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
be set to:
CONFIG_ARCH=arm
CONFIG_ARCH_family - For use in C code:
CONFIG_ARCH_ARM=y
CONFIG_ARCH_architecture - For use in C code:
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
CONFIG_ARCH_CHIP=lpc17xx
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
CONFIG_ARCH_CHIP_LPC1768=y
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
CONFIG_ARCH_BOARD=mbed (for the mbed.org board)
CONFIG_ARCH_BOARD_name - For use in C code
CONFIG_ARCH_BOARD_MBED=y
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
of delay loops
CONFIG_ENDIAN_BIG - define if big endian (default is little
endian)
CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
CONFIG_DRAM_SIZE=(32*1024) (32Kb)
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
CONFIG_DRAM_START - The start address of installed DRAM
CONFIG_DRAM_START=0x10000000
CONFIG_DRAM_END - Last address+1 of installed RAM
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
cause a 100 second delay during boot-up. This 100 second delay
serves no purpose other than it allows you to calibratre
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LPC17_FLASH=n
LPC17xx specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
This specific the size of the receive buffer
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
being sent. This specific the size of the transmit buffer
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
CONFIG_UARTn_2STOP - Two stop bits
LPC17xx specific PHY/Ethernet device driver settings. These setting
also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
CONFIG_PHY_AUTONEG - Enable auto-negotion
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
the higest priority.
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
CONFIG_DEBUG.
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
Also needs CONFIG_DEBUG.
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
Automatically set if CONFIG_NET_IGMP is selected.
LPC17xx USB Device Configuration
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
Handle USB Start-Of-Frame events.
Enable reading SOF from interrupt handler vs. simply reading on demand.
Probably a bad idea... Unless there is some issue with sampling the SOF
from hardware asynchronously.
CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
Enable high priority interrupts. I have no idea why you might want to
do that
CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
Number of DMA descriptors to allocate in SRAM.
CONFIG_LPC17_USBDEV_DMA
Enable lpc17xx-specific DMA support
CONFIG_LPC17_USBDEV_NOVBUS
Define if the hardware implementation does not support the VBUS signal
CONFIG_LPC17_USBDEV_NOLED
Define if the hardware implementation does not support the LED output
LPC17xx USB Host Configuration
CONFIG_USBHOST_OHCIRAM_SIZE
Total size of OHCI RAM (in AHB SRAM Bank 1)
CONFIG_USBHOST_NEDS
Number of endpoint descriptors
CONFIG_USBHOST_NTDS
Number of transfer descriptors
CONFIG_USBHOST_TDBUFFERS
Number of transfer descriptor buffers
CONFIG_USBHOST_TDBUFSIZE
Size of one transfer descriptor buffer
CONFIG_USBHOST_IOBUFSIZE
Size of one end-user I/O buffer. This can be zero if the
application can guarantee that all end-user I/O buffers
reside in AHB SRAM.
USB Host Configuration
^^^^^^^^^^^^^^^^^^^^^^
The mbed board can be easily modified to support a USB host interface
(Remember to add 2 resistors of 15K to D+ and D- pins). The hidkbd
configuration assumes that this change has been made.
The NuttShell (NSH) mbed can also be modified in order to support USB
host operations. To make these modifications, do the following:
1. First configure to build the NSH configuration from the top-level
NuttX directory:
cd tools
./configure mbed/nsh
cd ..
2. Then edit the top-level .config file to enable USB host. Make the
following changes:
CONFIG_LPC17_USBHOST=n
CONFIG_USBHOST=n
CONFIG_SCHED_WORKQUEUE=y
When this change is made, NSH should be extended to support USB flash
devices. When a FLASH device is inserted, you should see a device
appear in the /dev (psuedo) directory. The device name should be
like /dev/sda, /dev/sdb, etc. The USB mass storage device, is present
it can be mounted from the NSH command line like:
ls /dev
mount -t vfat /dev/sda /mnt/flash
Files on the connect USB flash device should then be accessible under
the mountpoint /mnt/flash.
Configurations
^^^^^^^^^^^^^^
Each mbed configuration is maintained in a sudirectory and can be selected
as follow:
cd tools
./configure.sh mbed/<subdir>
cd -
. ./setenv.sh
Where <subdir> is one of the following:
hidkbd:
This configuration directory, performs a simple test of the USB host
HID keyboard class driver using the test logic in examples/hidkbd.
This configuration assumes that you have modified your mbed for USB
host support.
nsh:
Configures the NuttShell (nsh) located at examples/nsh. The
Configuration enables only the serial NSH interfaces. See notes
above for enabling USB host support in this configuration.

4
configs/mbed/src/Makefile
View File

@ -56,9 +56,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

5
configs/ne64badge/src/Makefile
View File

@ -52,10 +52,9 @@ OBJS = $(AOBJS) $(COBJS)
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common
endif
all: libboard$(LIBEXT)

974
configs/nucleus2g/README.txt
View File

@ -1,487 +1,487 @@
README
^^^^^^
README for NuttX port to the Nucleus 2G LPC1768 board from 2G Engineering
(http://www.2g-eng.com/)
Contents
^^^^^^^^
2G-Engineering Nucleus Board
Development Environment
GNU Toolchain Options
IDEs
NuttX buildroot Toolchain
LEDs
Nucleus 2G Configuration Options
Configurations
Nucleus 2G Board
^^^^^^^^^^^^^^^^
GPIO Usage
P0[0]/RD1/TXD3/SDA1 P0[0]/CAN_RX1
P0[1]/TD1/RXD3/SCL P0[1]/CAN_TX1
P0[2]/TXD0/AD0[7] TX0
P0[3]/RXD0/AD0[6] RX0
P0[4] P0[4]/CAN1_STB
P0[5] P0[5]/CAN2_STB
P0[6]/I2SRX_SDA/SSEL1/MAT2[0] GPI/O_CS1
P0[7]/I2STX_CLK/SCK1/MAT2[1] SCLK1
P0[8]/I2STX_WS/MISO1/MAT2[2] MISO1
P0[9]/I2STX_SDA/MOSI1/MAT2[3] MOSI1
P0[10] P0[10]/CAN1_TERM
P0[11] P0[11]/CAN2_TERM
P0[15]/TXD1/SCK0/SCK MMC_CLK
P0[16]/RXD1/SSEL0/SSEL MMC_CD
P0[17]/CTS1/MISO0/MISO MMC_DATA0
P0[18]/DCD1/MOSI0/MOSI MMC_MISO
P0[19]/DSR1/SDA1 GPI/O_CS2
P0[20]/DTR1/SCL1 GPI/O_CS3
P0[21]/RI1/MCIPWR/RD1 P0[21]
P0[22]/RTS1/TD1 P0[22]
P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] AD0
P0[24]/AD0[1]/I2SRX_WS/CAP3[1] AD1
P0[25]/AD0[2]/I2SRX_SDA/TXD3 AD2
P0[26]/AD0[3]/AOUT/RXD3 AD3
P0[27]/SDA0/USB_SDA SDA
P0[28]/SCL0 SCL
P0[29]/USB_D+ USB+
P0[30]/USB_D- USB-
P1[0] - P1[17] Not connected
P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] USB_LINK
P1[19]-P[29] P[19]-P[29]
P1[30]/VBUS/AD0[4] USB_+5
P1[31]/SCK1/AD0[5] AD5
P2[0] P2[0]/LED1_A
P2[1] P2[1]/LED1_B
P2[2] P2[2]/LED2_A
P2[3] P2[3]/LED2_B
P2[4] P2[4]
P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 232_POWERAVE
P2[6]/PCAP1[0]/RI1/TRACECLK 232_VALID
P2[7]/RD2/RTS1 P2[7]/CAN_RX2
P2[8]/TD2/TXD2 P2[8]/CAN_TX2
P2[9]/USB_CONNECT/RXD2 USB_CONNECT
P2[10]/EINT0/NMI BOOTLOADER
P2[11]/EINT1/I2STX_CLK HEARTBEAT
P2[12]/EINT2/I2STX_WS EXTRA_LED
P2[13]/EINT3/I2STX_SDA 5V_ENABLE
P3[25]-P3[26] Not connected
P4[28]-P4[29] P4[28]-P4[29]
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment.
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The devkitARM GNU toolchain,
3. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the NuttX buildroot toolchain. However,
the make system is setup to default to use the devkitARM toolchain. To use
the CodeSourcery or devkitARM toolchain, you simply need add one of the
following configuration options to your .config (or defconfig) file:
CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
the PATH in the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
Linux native toolchains. There are several limitations to using a Windows based
toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had not effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
Support has been added for making dependencies with the windows-native toolchains.
That support can be enabled by modifying your Make.defs file as follows:
- MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
If you have problems with the dependency build (for example, if you are not
building on C:), then you may need to modify tools/mkdeps.sh
NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
^^^^
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project (There is a simple RIDE project
in the RIDE subdirectory).
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/lpc17x/lpc17_vectors.S.
NuttX buildroot Toolchain
^^^^^^^^^^^^^^^^^^^^^^^^^
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh nucleus2g/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-4.3.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
detailed PLUS some special instructions that you will need to follow if you
are building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: This is an OABI toolchain.
LEDs
^^^^
If CONFIG_ARCH_LEDS is defined, then support for the Nucleus-2G LEDs will be
included in the build. See:
- configs/nucleus2g/include/board.h - Defines LED constants, types and
prototypes the LED interface functions.
- configs/nucleus2g/src/nucleus2g_internal.h - GPIO settings for the LEDs.
- configs/nucleus2g/src/up_leds.c - LED control logic.
The Nucleus2G has 3 LEDs... two on the Babel CAN board and a "heartbeat" LED."
The LEDs on the Babel CAN board are capabl of OFF/GREEN/RED/AMBER status.
In normal usage, the two LEDs on the Babel CAN board would show CAN status, but if
CONFIG_ARCH_LEDS is defined, these LEDs will be controlled as follows for NuttX
debug functionality (where NC means "No Change").
During the boot phases. LED1 and LED2 will show boot status.
/* LED1 LED2 HEARTBEAT */
#define LED_STARTED 0 /* OFF OFF OFF */
#define LED_HEAPALLOCATE 1 /* GREEN OFF OFF */
#define LED_IRQSENABLED 2 /* OFF GREEN OFF */
#define LED_STACKCREATED 3 /* OFF OFF OFF */
#define LED_INIRQ 4 /* NC NC ON (momentary) */
#define LED_SIGNAL 5 /* NC NC ON (momentary) */
#define LED_ASSERTION 6 /* NC NC ON (momentary) */
#define LED_PANIC 7 /* NC NC ON (2Hz flashing) */
#undef LED_IDLE /* Sleep mode indication not supported */
After the system is booted, this logic will no longer use LEDs 1 and 2. They
are then available for use the application software using lpc17_led1() and
lpc17_led2():
enum lpc17_ledstate_e
{
LPC17_LEDSTATE_OFF = 0,
LPC17_LEDSTATE_GREEN = 1,
LPC17_LEDSTATE_RED = 2,
LPC17_LEDSTATE_AMBER = (LPC17_LEDSTATE_GREEN|LPC17_LEDSTATE_RED),
};
EXTERN void lpc17_led1(enum lpc17_ledstate_e state);
EXTERN void lpc17_led2(enum lpc17_ledstate_e state);
The heartbeat LED is illuminated during all interrupt and signal procressing.
Normally, it will glow dimly to inicate that the LPC17xx is taking interrupts.
On an assertion PANIC, it will flash at 2Hz.
Nucleus 2G Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
be set to:
CONFIG_ARCH=arm
CONFIG_ARCH_family - For use in C code:
CONFIG_ARCH_ARM=y
CONFIG_ARCH_architecture - For use in C code:
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
CONFIG_ARCH_CHIP=lpc17xx
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
CONFIG_ARCH_CHIP_LPC1768=y
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
CONFIG_ARCH_BOARD=nucleus2g (for the Nucleus 2G)
CONFIG_ARCH_BOARD_name - For use in C code
CONFIG_ARCH_BOARD_NUCLEUS2G=y
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
of delay loops
CONFIG_ENDIAN_BIG - define if big endian (default is little
endian)
CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
CONFIG_DRAM_SIZE=(32*1024) (32Kb)
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
CONFIG_DRAM_START - The start address of installed DRAM
CONFIG_DRAM_START=0x10000000
CONFIG_DRAM_END - Last address+1 of installed RAM
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
cause a 100 second delay during boot-up. This 100 second delay
serves no purpose other than it allows you to calibratre
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LPC17_FLASH=n
LPC17xx specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
This specific the size of the receive buffer
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
being sent. This specific the size of the transmit buffer
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
CONFIG_UARTn_2STOP - Two stop bits
LPC17xx specific PHY/Ethernet device driver settings. These setting
also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
CONFIG_PHY_AUTONEG - Enable auto-negotion
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
the higest priority.
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
CONFIG_DEBUG.
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
Also needs CONFIG_DEBUG.
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
Automatically set if CONFIG_NET_IGMP is selected.
LPC17xx USB Device Configuration
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
Handle USB Start-Of-Frame events.
Enable reading SOF from interrupt handler vs. simply reading on demand.
Probably a bad idea... Unless there is some issue with sampling the SOF
from hardware asynchronously.
CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
Enable high priority interrupts. I have no idea why you might want to
do that
CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
Number of DMA descriptors to allocate in SRAM.
CONFIG_LPC17_USBDEV_DMA
Enable lpc17xx-specific DMA support
CONFIG_LPC17_USBDEV_NOVBUS
Define if the hardware implementation does not support the VBUS signal
CONFIG_LPC17_USBDEV_NOLED
Define if the hardware implementation does not support the LED output
LPC17xx USB Host Configuration (the Nucleus2G does not support USB Host)
CONFIG_USBHOST_OHCIRAM_SIZE
Total size of OHCI RAM (in AHB SRAM Bank 1)
CONFIG_USBHOST_NEDS
Number of endpoint descriptors
CONFIG_USBHOST_NTDS
Number of transfer descriptors
CONFIG_USBHOST_TDBUFFERS
Number of transfer descriptor buffers
CONFIG_USBHOST_TDBUFSIZE
Size of one transfer descriptor buffer
CONFIG_USBHOST_IOBUFSIZE
Size of one end-user I/O buffer. This can be zero if the
application can guarantee that all end-user I/O buffers
reside in AHB SRAM.
Configurations
^^^^^^^^^^^^^^
Each Nucleus 2G configuration is maintained in a
sudirectory and can be selected as follow:
cd tools
./configure.sh nucleus2g/<subdir>
cd -
. ./setenv.sh
Where <subdir> is one of the following:
nsh:
Configures the NuttShell (nsh) located at examples/nsh. The
Configuration enables only the serial NSH interfaces.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.
usbserial:
This configuration directory exercises the USB serial class
driver at examples/usbserial. See examples/README.txt for
more information.
usbstorage:
This configuration directory exercises the USB mass storage
class driver at examples/usbstorage. See examples/README.txt for
more information.
README
^^^^^^
README for NuttX port to the Nucleus 2G LPC1768 board from 2G Engineering
(http://www.2g-eng.com/)
Contents
^^^^^^^^
2G-Engineering Nucleus Board
Development Environment
GNU Toolchain Options
IDEs
NuttX buildroot Toolchain
LEDs
Nucleus 2G Configuration Options
Configurations
Nucleus 2G Board
^^^^^^^^^^^^^^^^
GPIO Usage
P0[0]/RD1/TXD3/SDA1 P0[0]/CAN_RX1
P0[1]/TD1/RXD3/SCL P0[1]/CAN_TX1
P0[2]/TXD0/AD0[7] TX0
P0[3]/RXD0/AD0[6] RX0
P0[4] P0[4]/CAN1_STB
P0[5] P0[5]/CAN2_STB
P0[6]/I2SRX_SDA/SSEL1/MAT2[0] GPI/O_CS1
P0[7]/I2STX_CLK/SCK1/MAT2[1] SCLK1
P0[8]/I2STX_WS/MISO1/MAT2[2] MISO1
P0[9]/I2STX_SDA/MOSI1/MAT2[3] MOSI1
P0[10] P0[10]/CAN1_TERM
P0[11] P0[11]/CAN2_TERM
P0[15]/TXD1/SCK0/SCK MMC_CLK
P0[16]/RXD1/SSEL0/SSEL MMC_CD
P0[17]/CTS1/MISO0/MISO MMC_DATA0
P0[18]/DCD1/MOSI0/MOSI MMC_MISO
P0[19]/DSR1/SDA1 GPI/O_CS2
P0[20]/DTR1/SCL1 GPI/O_CS3
P0[21]/RI1/MCIPWR/RD1 P0[21]
P0[22]/RTS1/TD1 P0[22]
P0[23]/AD0[0]/I2SRX_CLK/CAP3[0] AD0
P0[24]/AD0[1]/I2SRX_WS/CAP3[1] AD1
P0[25]/AD0[2]/I2SRX_SDA/TXD3 AD2
P0[26]/AD0[3]/AOUT/RXD3 AD3
P0[27]/SDA0/USB_SDA SDA
P0[28]/SCL0 SCL
P0[29]/USB_D+ USB+
P0[30]/USB_D- USB-
P1[0] - P1[17] Not connected
P1[18]/USB_UP_LED/PWM1[1]/CAP1[0] USB_LINK
P1[19]-P[29] P[19]-P[29]
P1[30]/VBUS/AD0[4] USB_+5
P1[31]/SCK1/AD0[5] AD5
P2[0] P2[0]/LED1_A
P2[1] P2[1]/LED1_B
P2[2] P2[2]/LED2_A
P2[3] P2[3]/LED2_B
P2[4] P2[4]
P2[5]/PWM1[6]/DTR1/TRACEDATA[0] 232_POWERAVE
P2[6]/PCAP1[0]/RI1/TRACECLK 232_VALID
P2[7]/RD2/RTS1 P2[7]/CAN_RX2
P2[8]/TD2/TXD2 P2[8]/CAN_TX2
P2[9]/USB_CONNECT/RXD2 USB_CONNECT
P2[10]/EINT0/NMI BOOTLOADER
P2[11]/EINT1/I2STX_CLK HEARTBEAT
P2[12]/EINT2/I2STX_WS EXTRA_LED
P2[13]/EINT3/I2STX_SDA 5V_ENABLE
P3[25]-P3[26] Not connected
P4[28]-P4[29] P4[28]-P4[29]
Development Environment
^^^^^^^^^^^^^^^^^^^^^^^
Either Linux or Cygwin on Windows can be used for the development environment.
The source has been built only using the GNU toolchain (see below). Other
toolchains will likely cause problems. Testing was performed using the Cygwin
environment.
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the following different
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The devkitARM GNU toolchain,
3. The NuttX buildroot Toolchain (see below).
All testing has been conducted using the NuttX buildroot toolchain. However,
the make system is setup to default to use the devkitARM toolchain. To use
the CodeSourcery or devkitARM toolchain, you simply need add one of the
following configuration options to your .config (or defconfig) file:
CONFIG_LPC17_CODESOURCERYW=y : CodeSourcery under Windows
CONFIG_LPC17_CODESOURCERYL=y : CodeSourcery under Linux
CONFIG_LPC17_DEVKITARM=y : devkitARM under Windows
CONFIG_LPC17_BUILDROOT=y : NuttX buildroot under Linux or Cygwin (default)
If you are not using CONFIG_LPC17_BUILDROOT, then you may also have to modify
the PATH in the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows)and devkitARM are Windows native toolchains.
The CodeSourcey (for Linux) and NuttX buildroot toolchains are Cygwin and/or
Linux native toolchains. There are several limitations to using a Windows based
toolchain in a Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
but you might easily find some new path problems. If so, check out 'cygpath -w'
2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
are used in Nuttx (e.g., include/arch). The make system works around these
problems for the Windows tools by copying directories instead of linking them.
But this can also cause some confusion for you: For example, you may edit
a file in a "linked" directory and find that your changes had not effect.
That is because you are building the copy of the file in the "fake" symbolic
directory. If you use a Windows toolchain, you should get in the habit of
making like this:
make clean_context all
An alias in your .bashrc file might make that less painful.
3. Dependencies are not made when using Windows versions of the GCC. This is
because the dependencies are generated using Windows pathes which do not
work with the Cygwin make.
Support has been added for making dependencies with the windows-native toolchains.
That support can be enabled by modifying your Make.defs file as follows:
- MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
If you have problems with the dependency build (for example, if you are not
building on C:), then you may need to modify tools/mkdeps.sh
NOTE 1: The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
NOTE 2: The devkitARM toolchain includes a version of MSYS make. Make sure that
the paths to Cygwin's /bin and /usr/bin directories appear BEFORE the devkitARM
path or will get the wrong version of make.
IDEs
^^^^
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project (There is a simple RIDE project
in the RIDE subdirectory).
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
simply use the NuttX makefile to build the system. That is almost for free
under Linux. Under Windows, you will need to set up the "Cygwin GCC" empty
makefile project in order to work with Windows (Google for "Eclipse Cygwin" -
there is a lot of help on the internet).
Native Build
------------
Here are a few tips before you start that effort:
1) Select the toolchain that you will be using in your .config file
2) Start the NuttX build at least one time from the Cygwin command line
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/lpc17xx,
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.
Startup files will probably cause you some headaches. The NuttX startup file
is arch/arm/src/lpc17x/lpc17_vectors.S.
NuttX buildroot Toolchain
^^^^^^^^^^^^^^^^^^^^^^^^^
A GNU GCC-based toolchain is assumed. The files */setenv.sh should
be modified to point to the correct path to the Cortex-M3 GCC toolchain (if
different from the default in your PATH variable).
If you have no Cortex-M3 toolchain, one can be downloaded from the NuttX
SourceForge download site (https://sourceforge.net/project/showfiles.php?group_id=189573).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
cd tools
./configure.sh nucleus2g/<sub-dir>
2. Download the latest buildroot package into <some-dir>
3. unpack the buildroot tarball. The resulting directory may
have versioning information on it like buildroot-x.y.z. If so,
rename <some-dir>/buildroot-x.y.z to <some-dir>/buildroot.
4. cd <some-dir>/buildroot
5. cp configs/cortexm3-defconfig-4.3.3 .config
6. make oldconfig
7. make
8. Edit setenv.h, if necessary, so that the PATH variable includes
the path to the newly built binaries.
See the file configs/README.txt in the buildroot source tree. That has more
detailed PLUS some special instructions that you will need to follow if you
are building a Cortex-M3 toolchain for Cygwin under Windows.
NOTE: This is an OABI toolchain.
LEDs
^^^^
If CONFIG_ARCH_LEDS is defined, then support for the Nucleus-2G LEDs will be
included in the build. See:
- configs/nucleus2g/include/board.h - Defines LED constants, types and
prototypes the LED interface functions.
- configs/nucleus2g/src/nucleus2g_internal.h - GPIO settings for the LEDs.
- configs/nucleus2g/src/up_leds.c - LED control logic.
The Nucleus2G has 3 LEDs... two on the Babel CAN board and a "heartbeat" LED."
The LEDs on the Babel CAN board are capabl of OFF/GREEN/RED/AMBER status.
In normal usage, the two LEDs on the Babel CAN board would show CAN status, but if
CONFIG_ARCH_LEDS is defined, these LEDs will be controlled as follows for NuttX
debug functionality (where NC means "No Change").
During the boot phases. LED1 and LED2 will show boot status.
/* LED1 LED2 HEARTBEAT */
#define LED_STARTED 0 /* OFF OFF OFF */
#define LED_HEAPALLOCATE 1 /* GREEN OFF OFF */
#define LED_IRQSENABLED 2 /* OFF GREEN OFF */
#define LED_STACKCREATED 3 /* OFF OFF OFF */
#define LED_INIRQ 4 /* NC NC ON (momentary) */
#define LED_SIGNAL 5 /* NC NC ON (momentary) */
#define LED_ASSERTION 6 /* NC NC ON (momentary) */
#define LED_PANIC 7 /* NC NC ON (2Hz flashing) */
#undef LED_IDLE /* Sleep mode indication not supported */
After the system is booted, this logic will no longer use LEDs 1 and 2. They
are then available for use the application software using lpc17_led1() and
lpc17_led2():
enum lpc17_ledstate_e
{
LPC17_LEDSTATE_OFF = 0,
LPC17_LEDSTATE_GREEN = 1,
LPC17_LEDSTATE_RED = 2,
LPC17_LEDSTATE_AMBER = (LPC17_LEDSTATE_GREEN|LPC17_LEDSTATE_RED),
};
EXTERN void lpc17_led1(enum lpc17_ledstate_e state);
EXTERN void lpc17_led2(enum lpc17_ledstate_e state);
The heartbeat LED is illuminated during all interrupt and signal procressing.
Normally, it will glow dimly to inicate that the LPC17xx is taking interrupts.
On an assertion PANIC, it will flash at 2Hz.
Nucleus 2G Configuration Options
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
CONFIG_ARCH - Identifies the arch/ subdirectory. This should
be set to:
CONFIG_ARCH=arm
CONFIG_ARCH_family - For use in C code:
CONFIG_ARCH_ARM=y
CONFIG_ARCH_architecture - For use in C code:
CONFIG_ARCH_CORTEXM3=y
CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
CONFIG_ARCH_CHIP=lpc17xx
CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
chip:
CONFIG_ARCH_CHIP_LPC1768=y
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
CONFIG_ARCH_BOARD=nucleus2g (for the Nucleus 2G)
CONFIG_ARCH_BOARD_name - For use in C code
CONFIG_ARCH_BOARD_NUCLEUS2G=y
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
of delay loops
CONFIG_ENDIAN_BIG - define if big endian (default is little
endian)
CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
CONFIG_DRAM_SIZE=(32*1024) (32Kb)
There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
CONFIG_DRAM_START - The start address of installed DRAM
CONFIG_DRAM_START=0x10000000
CONFIG_DRAM_END - Last address+1 of installed RAM
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO - The LPC17xx supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
stack. If defined, this symbol is the size of the interrupt
stack in bytes. If not defined, the user task stacks will be
used during interrupt handling.
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
cause a 100 second delay during boot-up. This 100 second delay
serves no purpose other than it allows you to calibratre
CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LPC17_FLASH=n
LPC17xx specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
This specific the size of the receive buffer
CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
being sent. This specific the size of the transmit buffer
CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
CONFIG_UARTn_2STOP - Two stop bits
LPC17xx specific PHY/Ethernet device driver settings. These setting
also require CONFIG_NET and CONFIG_LPC17_ETHERNET.
CONFIG_PHY_KS8721 - Selects Micrel KS8721 PHY
CONFIG_PHY_AUTONEG - Enable auto-negotion
CONFIG_PHY_SPEED100 - Select 100Mbit vs. 10Mbit speed.
CONFIG_PHY_FDUPLEX - Select full (vs. half) duplex
CONFIG_NET_EMACRAM_SIZE - Size of EMAC RAM. Default: 16Kb
CONFIG_NET_NTXDESC - Configured number of Tx descriptors. Default: 18
CONFIG_NET_NRXDESC - Configured number of Rx descriptors. Default: 18
CONFIG_NET_PRIORITY - Ethernet interrupt priority. The is default is
the higest priority.
CONFIG_NET_WOL - Enable Wake-up on Lan (not fully implemented).
CONFIG_NET_REGDEBUG - Enabled low level register debug. Also needs
CONFIG_DEBUG.
CONFIG_NET_DUMPPACKET - Dump all received and transmitted packets.
Also needs CONFIG_DEBUG.
CONFIG_NET_HASH - Enable receipt of near-perfect match frames.
CONFIG_NET_MULTICAST - Enable receipt of multicast (and unicast) frames.
Automatically set if CONFIG_NET_IGMP is selected.
LPC17xx USB Device Configuration
CONFIG_LPC17_USBDEV_FRAME_INTERRUPT
Handle USB Start-Of-Frame events.
Enable reading SOF from interrupt handler vs. simply reading on demand.
Probably a bad idea... Unless there is some issue with sampling the SOF
from hardware asynchronously.
CONFIG_LPC17_USBDEV_EPFAST_INTERRUPT
Enable high priority interrupts. I have no idea why you might want to
do that
CONFIG_LPC17_USBDEV_NDMADESCRIPTORS
Number of DMA descriptors to allocate in SRAM.
CONFIG_LPC17_USBDEV_DMA
Enable lpc17xx-specific DMA support
CONFIG_LPC17_USBDEV_NOVBUS
Define if the hardware implementation does not support the VBUS signal
CONFIG_LPC17_USBDEV_NOLED
Define if the hardware implementation does not support the LED output
LPC17xx USB Host Configuration (the Nucleus2G does not support USB Host)
CONFIG_USBHOST_OHCIRAM_SIZE
Total size of OHCI RAM (in AHB SRAM Bank 1)
CONFIG_USBHOST_NEDS
Number of endpoint descriptors
CONFIG_USBHOST_NTDS
Number of transfer descriptors
CONFIG_USBHOST_TDBUFFERS
Number of transfer descriptor buffers
CONFIG_USBHOST_TDBUFSIZE
Size of one transfer descriptor buffer
CONFIG_USBHOST_IOBUFSIZE
Size of one end-user I/O buffer. This can be zero if the
application can guarantee that all end-user I/O buffers
reside in AHB SRAM.
Configurations
^^^^^^^^^^^^^^
Each Nucleus 2G configuration is maintained in a
sudirectory and can be selected as follow:
cd tools
./configure.sh nucleus2g/<subdir>
cd -
. ./setenv.sh
Where <subdir> is one of the following:
nsh:
Configures the NuttShell (nsh) located at examples/nsh. The
Configuration enables only the serial NSH interfaces.
ostest:
This configuration directory, performs a simple OS test using
examples/ostest.
usbserial:
This configuration directory exercises the USB serial class
driver at examples/usbserial. See examples/README.txt for
more information.
usbstorage:
This configuration directory exercises the USB mass storage
class driver at examples/usbstorage. See examples/README.txt for
more information.

4
configs/nucleus2g/src/Makefile
View File

@ -56,9 +56,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

1786
configs/olimex-lpc1766stk/README.txt
View File

File diff suppressed because it is too large Load Diff

4
configs/olimex-lpc1766stk/src/Makefile
View File

@ -59,9 +59,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

5
configs/qemu-i486/src/Makefile
View File

@ -49,10 +49,9 @@ OBJS = $(AOBJS) $(COBJS)
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common
endif
all: libboard$(LIBEXT)

2
configs/sam3u-ek/README.txt
View File

@ -114,7 +114,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/sam3u,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

4
configs/sam3u-ek/knsh/defconfig
View File

@ -100,9 +100,9 @@ CONFIG_SAM3U_BUILDROOT=y
#
# Cortex-M3 features
#
# CONFIG_CORTEXM3_MPU - Enabled the MPU
# CONFIG_ARMV7M_MPU - Enabled the MPU
#
CONFIG_CORTEXM3_MPU=y
CONFIG_ARMV7M_MPU=y
#
# Individual subsystems can be enabled:

4
configs/sam3u-ek/src/Makefile
View File

@ -59,9 +59,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/stm3210e-eval/README.txt
View File

@ -118,7 +118,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/stm32,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

8
configs/stm3210e-eval/RIDE/nuttx.rapp
View File

@ -7,8 +7,8 @@
<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_serial.c" Header="stm32_serial.c" Marker="-1" OutputFile=".\stm32_serial.o" sate="0" />
<NodeC Path="..\..\..\arch\arm\src\stm32\stm32_start.c" Header="stm32_start.c" Marker="-1" OutputFile=".\stm32_start.o" sate="0" />
<NodeC Path=".\bigfatstub.c" Header="bigfatstub.c" Marker="-1" OutputFile=".\bigfatstub.o" sate="0" />
<NodeC Path="..\..\..\arch\arm\src\cortexm3\up_svcall.c" Header="up_svcall.c" Marker="-1" OutputFile=".\up_svcall.o" sate="0" />
<NodeC Path="..\..\..\arch\arm\src\cortexm3\up_hardfault.c" Header="up_hardfault.c" Marker="-1" OutputFile=".\up_hardfault.o" sate="0" />
<NodeC Path="..\..\..\arch\arm\src\armv7-m\up_svcall.c" Header="up_svcall.c" Marker="-1" OutputFile=".\up_svcall.o" sate="0" />
<NodeC Path="..\..\..\arch\arm\src\armv7-m\up_hardfault.c" Header="up_hardfault.c" Marker="-1" OutputFile=".\up_hardfault.o" sate="0" />
<NodeC Path="..\src\up_leds.c" Header="up_leds.c" Marker="-1" OutputFile=".\up_leds.o" sate="0" />
<NodeC Path="..\src\up_boot.c" Header="up_boot.c" Marker="-1" OutputFile=".\up_boot.o" sate="0" />
<NodeC Path="..\..\..\sched\irq_unexpectedisr.c" Header="irq_unexpectedisr.c" Marker="-1" OutputFile=".\irq_unexpectedisr.o" sate="0" />
@ -21,7 +21,7 @@
</Section>
<Section Header="Directories" >
<Property Header="IncDir" Value=".;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\common;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\cortexm3;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\stm32;C:\cygwin\home\Owner\projects\nuttx\nuttx\include;C:\cygwin\home\Owner\projects\nuttx\nuttx\sched" Removable="1" />
<Property Header="IncDir" Value=".;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\common;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\armv7-m;C:\cygwin\home\Owner\projects\nuttx\nuttx\arch\arm\src\stm32;C:\cygwin\home\Owner\projects\nuttx\nuttx\include;C:\cygwin\home\Owner\projects\nuttx\nuttx\sched" Removable="1" />
</Section>
@ -80,4 +80,4 @@
</Set>
</Config>
</Options>
</ApplicationBuild>
</ApplicationBuild>

4
configs/stm3210e-eval/src/Makefile
View File

@ -65,9 +65,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)

2
configs/vsn/README.txt
View File

@ -118,7 +118,7 @@ IDEs
before trying to create your project. This is necessary to create
certain auto-generated files and directories that will be needed.
3) Set up include pathes: You will need include/, arch/arm/src/stm32,
arch/arm/src/common, arch/arm/src/cortexm3, and sched/.
arch/arm/src/common, arch/arm/src/armv7-m, and sched/.
4) All assembly files need to have the definition option -D __ASSEMBLY__
on the command line.

4
configs/vsn/src/Makefile
View File

@ -67,9 +67,9 @@ ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/cortexm3}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/armv7-m}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/cortexm3
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/armv7-m
endif
all: libboard$(LIBEXT)