arch/arm/src/imxrt: Add eDMA interrupt decode logic.
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@ -260,17 +260,28 @@ static void imxrt_dmaterminate(struct imxrt_dmach_s *dmach, int result)
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static void imxrt_dmach_interrupt(struct imxrt_dmach_s *dmach)
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{
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uintptr_t regaddr;
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uint32_t regval32;
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uint16_t regval16;
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uint8_t regval8;
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unsigned int chan;
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int result;
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/* Is (or was) DMA active on this channel? */
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/* Check for a pending interrupt on this channel */
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if (dmach->state == IMXRT_DMA_ACTIVE)
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chan = dmach->chan;
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regval32 = getreg32(IMXRT_EDMA_INT);
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if ((regval32 & EDMA_INT(chan)) != 0)
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{
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/* An interrupt is pending. This should only happen if the channel is
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* active.
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*/
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DEBUGASSERT(dmach->state == IMXRT_DMA_ACTIVE);
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/* Yes.. Get the eDMA TCD Control and Status register value. */
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regaddr = IMXRT_EDMA_TCD_CSR(dmach->chan);
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regaddr = IMXRT_EDMA_TCD_CSR(chan);
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/* Check if the transfer is done */
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@ -278,21 +289,34 @@ static void imxrt_dmach_interrupt(struct imxrt_dmach_s *dmach)
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{
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/* Clear the pending DONE interrupt status. */
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regval8 = EDMA_CDNE(dmach->chan);
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regval8 = EDMA_CDNE(chan);
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putreg8(regval8, IMXRT_EDMA_CDNE);
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result = OK;
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}
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/* Check if any errors have occurred. */
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#warning Missing logic
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else
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{
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/* Clear the pending error interrupt status. */
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#warning Missing logic
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/* Check if any errors have occurred. */
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result = -EIO;
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regval32 = getreg32(IMXRT_EDMA_ERR);
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if ((regval32 & EDMA_ERR(n)(chan)) != 0)
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{
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dmaerr("ERROR: eDMA ES=%08lx\n",
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(unsigned long)getreg32(IMXRT_EDMA_ES));
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/* Clear the pending error interrupt status. */
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regval8 = EDMA_CERR(chan);
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putreg32(regval8, IMXRT_EDMA_CERR);
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result = -EIO;
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}
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}
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/* Clear the pending interrupt */
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regval8 = EDMA_CINT(chan);
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putreg32(regval8, IMXRT_EDMA_CINT);
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result = -EIO;
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/* Terminate the transfer */
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imxrt_dmaterminate(dmach, result);
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@ -312,7 +336,7 @@ static int imxrt_edma_interrupt(int irq, void *context, FAR void *arg)
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struct imxrt_dmach_s *dmach;
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unsigned int chan;
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/* 'arg' should the the DMA channel instance.
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/* 'arg' should the DMA channel instance.
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*
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* NOTE that there are only 16 vectors for 32 DMA channels. The 'arg' will
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* always be the lower-numbered DMA channel. The other DMA channel will
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