SAM3/4: Loop counter for PLL delay must be volatile or it may get optimized away

arch/arm/src/sam34/sam3u_clockconfig.c

@@ -151,7 +151,8 @@ static inline void sam_supcsetup(void)
 
 static void sam_pmcwait(uint32_t bit)
 {
-  uint32_t delay;
+  volatile uint32_t delay;
+
   for (delay = 0;
        (getreg32(SAM_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
        delay++);

configs/sam3u-ek/src/up_touchscreen.c

@@ -195,6 +195,7 @@ static bool tsc_busy(FAR struct ads7843e_config_s *state)
       last = busy;
     }
 #endif
+
   return busy;
 }
 

drivers/serial/serialirq.c

@@ -84,7 +84,7 @@ void uart_xmitchars(FAR uart_dev_t *dev)
 {
   uint16_t nbytes = 0;
 
-  /* Send while we still have data & room in the fifo */
+  /* Send while we still have data in the TX buffer & room in the fifo */
 
   while (dev->xmit.head != dev->xmit.tail && uart_txready(dev))
     {
@@ -103,6 +103,11 @@ void uart_xmitchars(FAR uart_dev_t *dev)
 
   /* When all of the characters have been sent from the buffer disable the TX
    * interrupt.
+   *
+   * Potential bug?  If nbytes == 0 && (dev->xmit.head == dev->xmit.tail) &&
+   * dev->xmitwaiting == true, then disabling the TX interrupt will leave
+   * the uart_write() logic waiting to TX to complete with no TX interrupts.
+   * Can that happen?
    */
 
   if (dev->xmit.head == dev->xmit.tail)