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lm3s6918 now does context switches

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1790 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2009-05-18 22:14:40 +00:00
parent b44a8db1a4
commit 9d329e414a
2 changed files with 33 additions and 9 deletions
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32
arch/arm/src/common/up_initialstate.c
View File

@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/common/up_initialstate.c
*
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -40,10 +40,16 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <string.h>
#include <nuttx/arch.h>
#include "up_internal.h"
#include "up_arch.h"
#ifdef __thumb2__
# include "cortexm3_psr.h"
#endif
/****************************************************************************
* Private Definitions
****************************************************************************/
@ -81,18 +87,36 @@ void up_initial_state(_TCB *tcb)
/* Initialize the initial exception register context structure */
memset(xcp, 0, sizeof(struct xcptcontext));
/* Save the initial stack point */
xcp->regs[REG_SP] = (uint32)tcb->adj_stack_ptr;
xcp->regs[REG_PC] = (uint32)tcb->start;
#ifdef __thumb2__
/* Save the task entry point (stripping off the thumb bit) */
xcp->regs[REG_PC] = (uint32)tcb->start & ~1;
/* Specify thumb mode */
xcp->regs[REG_XPSR] = CORTEXM3_XPSR_T;
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
xcp->regs[REG_PRIMASK] = 1;
# endif
#else
#else /* __thumb2__ */
/* Save the task entry point */
xcp->regs[REG_PC] = (uint32)tcb->start;
/* Enable or disable interrupts, based on user configuration */
# ifdef CONFIG_SUPPRESS_INTERRUPTS
xcp->regs[REG_CPSR] = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
# else
xcp->regs[REG_CPSR] = SVC_MODE | PSR_F_BIT;
# endif
#endif
#endif /* __thumb2__ */
}

10
arch/arm/src/lm3s/lm3s_vectors.S
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@ -298,7 +298,7 @@ lm3s_irqcommon:
* as current stack pointer, then things are relatively easy.
*/
cmp r0, r1
cmp r0, r1 /* Context switch? */
beq 1f /* Branch if no context switch */
/* We are returning with a pending context switch. This case is different
@ -307,11 +307,11 @@ lm3s_irqcommon:
* values to the stack.
*/
add r1, r0, #SW_XCPT_REGS /* r2=offset HW save area */
ldmia r1, {r4-r11} /* Eight registers in HW save area */
add r1, r0, #SW_XCPT_SIZE /* R1=Address of HW save area in reg array */
ldmia r1, {r4-r11} /* Fetch eight registers in HW save area */
ldr r1, [r0, #(4*REG_SP)] /* R1=Value of SP before interrupt */
stmdb r1!, {r4-r11} /* Eight registers in HW save area */
ldmia r0!, {r2-r11} /* Recover R4-R11 + 2 temp values */
stmdb r1!, {r4-r11} /* Store eight registers in HW save area */
ldmia r0, {r2-r11} /* Recover R4-R11 + 2 temp values */
b 2f /* Re-join common logic */
/* We are returning with no context switch. We simply need to "unwind"