LP43xx... disable debug traps on hardfaults
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4929 42af7a65-404d-4744-a932-0658087f49c3
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@ -1,4 +1,4 @@
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/************************************************************************************
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/********************************************************************************************
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* arch/arm/src/armv7-m/nvic.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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@ -31,26 +31,26 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H
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#define __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H
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/************************************************************************************
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/********************************************************************************************
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* Included Files
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************************************************************************************/
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********************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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/********************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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********************************************************************************************/
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/* NVIC base address ****************************************************************/
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/* NVIC base address ************************************************************************/
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#define ARMV7M_NVIC_BASE 0xe000e000
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/* NVIC register offsets ************************************************************/
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/* NVIC register offsets ********************************************************************/
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#define NVIC_ICTR_OFFSET 0x0004 /* Interrupt controller type register */
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#define NVIC_SYSTICK_CTRL_OFFSET 0x0010 /* SysTick control and status register */
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@ -203,6 +203,10 @@
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#define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */
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#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
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#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
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#define NVIC_DHCSR_OFFSET 0x0df0 /* Debug Halting Control and Status Register */
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#define NVIC_DCRSR_OFFSET 0x0df4 /* Debug Core Register Selector Register */
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#define NVIC_DCRDR_OFFSET 0x0df8 /* Debug Core Register Data Register */
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#define NVIC_DEMCR_OFFSET 0x0dfc /* Debug Exception and Monitor Control Register */
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#define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */
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#define NVIC_FPCCR_OFFSET 0x0f34 /* Floating-point Context Control Register */
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#define NVIC_FPCAR_OFFSET 0x0f38 /* Floating-point Context Address Register */
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@ -222,7 +226,7 @@
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#define NVIC_CID2_OFFSET 0x0ff8 /* Component identification register bits 23:16 (CID0) */
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#define NVIC_CID3_OFFSET 0x0ffc /* Component identification register bits 23:16 (CID0) */
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/* NVIC register addresses **********************************************************/
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/* NVIC register addresses ******************************************************************/
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#define NVIC_ICTR (ARMV7M_NVIC_BASE + NVIC_ICTR_OFFSET)
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#define NVIC_SYSTICK_CTRL (ARMV7M_NVIC_BASE + NVIC_SYSTICK_CTRL_OFFSET)
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@ -372,6 +376,10 @@
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#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
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#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
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#define NVIC_CPACR (ARMV7M_NVIC_BASE + NVIC_CPACR_OFFSET)
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#define NVIC_DHCSR (ARMV7M_NVIC_BASE + NVIC_DHCSR_OFFSET)
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#define NVIC_DCRSR (ARMV7M_NVIC_BASE + NVIC_DCRSR_OFFSET)
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#define NVIC_DCRDR (ARMV7M_NVIC_BASE + NVIC_DCRDR_OFFSET)
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#define NVIC_DEMCR (ARMV7M_NVIC_BASE + NVIC_DEMCR_OFFSET)
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#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
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#define NVIC_FPCCR (ARMV7M_NVIC_BASE + NVIC_FPCCR_OFFSET)
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#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
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@ -387,7 +395,7 @@
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#define NVIC_CID2 (ARMV7M_NVIC_BASE + NVIC_CID2_OFFSET)
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#define NVIC_CID3 (ARMV7M_NVIC_BASE + NVIC_CID3_OFFSET)
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/* NVIC register bit definitions ****************************************************/
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/* NVIC register bit definitions ************************************************************/
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/* Interrrupt controller type (INCTCTL_TYPE) */
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@ -492,16 +500,32 @@
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#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
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#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
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/************************************************************************************
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/* Debug Exception and Monitor Control Register (DEMCR) */
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#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */
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#define NVIC_DEMCR_VCMMERR (1 << 4) /* Bit 4: Debug trap on Memory Management faults */
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#define NVIC_DEMCR_VCNOCPERR (1 << 5) /* Bit 5: Debug trap on Usage Fault access to non-present coprocessor */
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#define NVIC_DEMCR_VCCHKERR (1 << 6) /* Bit 6: Debug trap on Usage Fault enabled checking errors */
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#define NVIC_DEMCR_VCSTATERR (1 << 7) /* Bit 7: Debug trap on Usage Fault state error */
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#define NVIC_DEMCR_VCBUSERR (1 << 8) /* Bit 8: Debug Trap on normal Bus error */
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#define NVIC_DEMCR_VCINTERR (1 << 9) /* Bit 9: Debug Trap on interrupt/exception service errors */
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#define NVIC_DEMCR_VCHARDERR (1 << 10) /* Bit 10: Debug trap on Hard Fault */
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#define NVIC_DEMCR_MONEN (1 << 16) /* Bit 16: Enable the debug monitor */
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#define NVIC_DEMCR_MONPEND (1 << 17) /* Bit 17: Pend the monitor to activate when priority permits */
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#define NVIC_DEMCR_MONSTEP (1 << 18) /* Bit 18: Steps the core */
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#define NVIC_DEMCR_MONREQ (1 << 19) /* Bit 19: Monitor wake-up mode */
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#define NVIC_DEMCR_TRCENA (1 << 24) /* Bit 24: Enable trace and debug blocks */
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/********************************************************************************************
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* Public Types
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************************************************************************************/
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********************************************************************************************/
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/************************************************************************************
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/********************************************************************************************
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* Public Data
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************************************************************************************/
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********************************************************************************************/
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/************************************************************************************
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/********************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_NVIC_H */
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@ -271,6 +271,9 @@ static int lpc43_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
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void up_irqinitialize(void)
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{
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uint32_t regaddr;
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#ifdef CONFIG_DEBUG
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uint32_t regval;
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#endif
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int num_priority_registers;
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/* Disable all interrupts */
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@ -357,6 +360,14 @@ void up_irqinitialize(void)
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lpc43_dumpnvic("initial", LPC43M4_IRQ_NIRQS);
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/* If a debugger is connected, try to prevent it from catching hardfaults */
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#ifdef CONFIG_DEBUG
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regval = getreg32(NVIC_DEMCR);
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regval &= ~NVIC_DEMCR_VCHARDERR;
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putreg32(regval, NVIC_DEMCR);
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#endif
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/* And finally, enable interrupts */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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@ -360,6 +360,12 @@ Code Red IDE
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configuration file when you build NuttX. That option is necessary to build
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in debugging symbols.
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NOTE 3: There are few things that NuttX has to do differently if you
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are using a debugger. Make sure that you also set CONFIG_DEBUG=y. Nothing
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also is needed and no debug output will be generated; but NuttX will
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use CONFIG_DEBUG=y to mean that a debugger is attached and will deal
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with certain resets and debug controls appropriately.
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Troubleshooting. This page provides some troubleshooting information that
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you can use to verify that the LPCLink is working correctly:
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