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Merged in K-man23/nuttx/stm32f411-fix (pull request #34)

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Add support for SPI 4 and 5 on stm32f411 chips
This commit is contained in:
Gregory Nutt 2016-05-27 13:15:21 -06:00
commit 9d475e4f48
3 changed files with 26 additions and 10 deletions
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4
arch/arm/include/stm32/chip.h
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@ -1568,7 +1568,7 @@
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NSPI 5 /* SPI1-5 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
# define STM32_NI2C 3 /* I2C1-3 */
@ -1606,7 +1606,7 @@
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NSPI 5 /* SPI1-5 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */
# define STM32_NI2C 3 /* I2C1-3 */

8
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
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@ -628,7 +628,8 @@
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \
defined(CONFIG_STM32_STM32F411)
# define GPIO_SPI4_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN5)
# define GPIO_SPI4_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN13)
# define GPIO_SPI4_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTE|GPIO_PIN6)
@ -643,7 +644,7 @@
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411)
# define GPIO_SPI5_MISO_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN8)
# define GPIO_SPI5_MISO_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN7)
# define GPIO_SPI5_MOSI_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN9)
@ -652,7 +653,10 @@
# define GPIO_SPI5_NSS_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN5)
# define GPIO_SPI5_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN7)
# define GPIO_SPI5_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTH|GPIO_PIN6)
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define GPIO_SPI6_MISO (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN12)
# define GPIO_SPI6_MOSI (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN14)
# define GPIO_SPI6_NSS (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PORTG|GPIO_PIN8)

24
arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
View File

@ -356,7 +356,8 @@
#define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \
defined(CONFIG_STM32_STM32F411)
# define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */
#endif
#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */
@ -364,8 +365,11 @@
#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */
#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411)
# define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define RCC_APB2RSTR_SPI6RST (1 << 21) /* Bit 21: SPI 6 reset */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
@ -500,7 +504,8 @@
#define RCC_APB2ENR_SDIOEN (1 << 11) /* Bit 11: SDIO clock enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \
defined(CONFIG_STM32_STM32F411)
# define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI4 clock enable */
#endif
#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */
@ -508,8 +513,11 @@
#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM10 clock enable */
#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM11 clock enable */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411)
# define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI5 clock enable */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define RCC_APB2ENR_SPI6EN (1 << 21) /* Bit 21: SPI6 clock enable */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
@ -649,7 +657,8 @@
#define RCC_APB2LPENR_SDIOLPEN (1 << 11) /* Bit 11: SDIO clock enable during Sleep mode */
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during Sleep mode */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \
defined(CONFIG_STM32_STM32F411)
# define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 clock enable during Sleep mode */
#endif
#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */
@ -657,8 +666,11 @@
#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM10 clock enable during Sleep mode */
#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM11 clock enable during Sleep mode */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
defined(CONFIG_STM32_STM32F469) || defined(CONFIG_STM32_STM32F411)
# define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI5 clock enable during Sleep mode */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define RCC_APB2LPENR_SPI6LPEN (1 << 21) /* Bit 21: SPI6 clock enable during Sleep mode */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \