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Fix nuttx coding style

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Remove spaces
Remove extra */
This commit is contained in:
simbit18 2023-12-13 14:36:43 +01:00 committed by Alin Jerpelea
parent c3a234fe99
commit 9d50d180b1
12 changed files with 24 additions and 24 deletions
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4
arch/arm/include/at32/chip.h
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@ -86,7 +86,7 @@
#if defined(CONFIG_ARCH_CHIP_AT32F435RC) /* LQFP 64 10x10x1.4 256Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 0 /* No FSMC */
# define AT32_NATIM 3 /* 3 advanced timers TIM1 and 8 */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* 2 basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */
@ -434,7 +434,7 @@
#elif defined(CONFIG_ARCH_CHIP_AT32F437VM) /* LQFP-100 14x14x1.4 4032Kb FLASH 384Kb SRAM */
# define AT32_NFSMC 1 /* FSMC */
# define AT32_NATIM 3 /* Two advanced timers TIM1 and 8 */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIM 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define AT32_NGTIMNDMA 8 /* 16-bit general timers TIM9-14 without DMA */
# define AT32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define AT32_NDMA 2 /* DMA1-2 */

20
arch/arm/src/at32/hardware/at32_spi.h
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@ -128,16 +128,16 @@
#define SPI_CTRL1_MDIV_SHIFT (3) /* Master clock frequency division */
#define SPI_CTRL1_MDIV_MASK (7 << SPI_CTRL1_MDIV_SHIFT)
# define SPI_CTRL1_MDIV_2 (0 << SPI_CTRL1_MDIV_SHIFT) /* Div 2 */
# define SPI_CTRL1_MDIV_4 (1 << SPI_CTRL1_MDIV_SHIFT) /* Div 4 */
# define SPI_CTRL1_MDIV_8 (2 << SPI_CTRL1_MDIV_SHIFT) /* Div 8 */
# define SPI_CTRL1_MDIV_16 (3 << SPI_CTRL1_MDIV_SHIFT) /* Div 16 */
# define SPI_CTRL1_MDIV_32 (4 << SPI_CTRL1_MDIV_SHIFT) /* Div 32 */
# define SPI_CTRL1_MDIV_64 (5 << SPI_CTRL1_MDIV_SHIFT) /* Div 64 */
# define SPI_CTRL1_MDIV_128 (6 << SPI_CTRL1_MDIV_SHIFT) /* Div 128 */
# define SPI_CTRL1_MDIV_256 (7 << SPI_CTRL1_MDIV_SHIFT) /* Div 256 */
# define SPI_CTRL1_MDIV_512 (8 << SPI_CTRL1_MDIV_SHIFT) /* Div 512 */
# define SPI_CTRL1_MDIV_1024 (9 << SPI_CTRL1_MDIV_SHIFT) /* Div 1024 */
# define SPI_CTRL1_MDIV_2 (0 << SPI_CTRL1_MDIV_SHIFT) /* Div 2 */
# define SPI_CTRL1_MDIV_4 (1 << SPI_CTRL1_MDIV_SHIFT) /* Div 4 */
# define SPI_CTRL1_MDIV_8 (2 << SPI_CTRL1_MDIV_SHIFT) /* Div 8 */
# define SPI_CTRL1_MDIV_16 (3 << SPI_CTRL1_MDIV_SHIFT) /* Div 16 */
# define SPI_CTRL1_MDIV_32 (4 << SPI_CTRL1_MDIV_SHIFT) /* Div 32 */
# define SPI_CTRL1_MDIV_64 (5 << SPI_CTRL1_MDIV_SHIFT) /* Div 64 */
# define SPI_CTRL1_MDIV_128 (6 << SPI_CTRL1_MDIV_SHIFT) /* Div 128 */
# define SPI_CTRL1_MDIV_256 (7 << SPI_CTRL1_MDIV_SHIFT) /* Div 256 */
# define SPI_CTRL1_MDIV_512 (8 << SPI_CTRL1_MDIV_SHIFT) /* Div 512 */
# define SPI_CTRL1_MDIV_1024 (9 << SPI_CTRL1_MDIV_SHIFT) /* Div 1024 */
#define SPI_CTRL1_SPIEN (1 << 6) /* SPI enable */
#define SPI_CTRL1_LTF (1 << 7) /* LSB transmit first */

2
arch/arm/src/at32/hardware/at32f43xxx_gpio.h
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@ -40,7 +40,7 @@
#define AT32_GPIO_MUXL_OFFSET (0x20) /* GPIO muxing register (pin0~7) */
#define AT32_GPIO_MUXH_OFFSET (0x24) /* GPIO muxing register (pin8~15)*/
#define AT32_GPIO_CLR_OFFSET (0x28) /* GPIO clear bit */
#define AT32_GPIO_HDRV_OFFSET (0x3C) /* GPIO high driver */
#define AT32_GPIO_HDRV_OFFSET (0x3C) /* GPIO high driver */
/* Register Addresses *******************************************************/

2
arch/arm/src/at32/hardware/at32f43xxx_rcc.h
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@ -102,7 +102,7 @@
#define CRM_PLL_CFG_PLL_NS_MASK (0x1FF << CRM_PLL_CFG_PLL_NS_SHIFT)
# define CRM_PLL_CFG_PLL_NS(n) ((n) << CRM_PLL_CFG_PLL_NS_SHIFT) /* n = 31..500 */
#define CRM_PLL_CFG_PLL_FR_SHIFT (16) /* PLL post-division */
#define CRM_PLL_CFG_PLL_FR_SHIFT (16) /* PLL post-division */
#define CRM_PLL_CFG_PLL_FR_MASK (7 << CRM_PLL_CFG_PLL_FR_SHIFT)
# define CRM_PLL_CFG_PLL_FR_1 (0 << CRM_PLL_CFG_PLL_FR_SHIFT) /* div 1 */
# define CRM_PLL_CFG_PLL_FR_2 (1 << CRM_PLL_CFG_PLL_FR_SHIFT) /* div 2 */

4
arch/arm/src/efm32/hardware/efm32_letimer.h
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@ -82,8 +82,8 @@
#define EFM32_LETIMER_CMD_OFFSET 0x0004 /* Command Register */
#define EFM32_LETIMER_STATUS_OFFSET 0x0008 /* Status Register */
#define EFM32_LETIMER_CNT_OFFSET 0x000c /* Counter Value Register */
#define EFM32_LETIMER_COMP0_OFFSET 0x0010 /* Compare Value Register */ 0
#define EFM32_LETIMER_COMP1_OFFSET 0x0014 /* Compare Value Register */ 1
#define EFM32_LETIMER_COMP0_OFFSET 0x0010 /* Compare Value Register 0 */
#define EFM32_LETIMER_COMP1_OFFSET 0x0014 /* Compare Value Register 1 */
#define EFM32_LETIMER_REP0_OFFSET 0x0018 /* Repeat Counter Register 0 */
#define EFM32_LETIMER_REP1_OFFSET 0x001c /* Repeat Counter Register 1 */
#define EFM32_LETIMER_IF_OFFSET 0x0020 /* Interrupt Flag Register */

2
arch/arm/src/stm32/hardware/stm32_tim_v1v2.h
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@ -867,7 +867,7 @@
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */
#define ATIM_BDTR_BKE (1 << 12) /* Bit 12: Break enable */

2
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h
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@ -725,7 +725,7 @@
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */

2
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h
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@ -727,7 +727,7 @@
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */

2
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
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@ -745,7 +745,7 @@
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */

2
arch/arm/src/stm32h7/hardware/stm32_tim.h
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@ -763,7 +763,7 @@
# define ATIM_BDTR_LOCKOFF (0 << ATIM_BDTR_LOCK_SHIFT) /* 00: LOCK OFF - No bit is write protected */
# define ATIM_BDTR_LOCK1 (1 << ATIM_BDTR_LOCK_SHIFT) /* 01: LOCK Level 1 protection */
# define ATIM_BDTR_LOCK2 (2 << ATIM_BDTR_LOCK_SHIFT) /* 10: LOCK Level 2 protection */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */ */
# define ATIM_BDTR_LOCK3 (3 << ATIM_BDTR_LOCK_SHIFT) /* 11: LOCK Level 3 protection */
#define ATIM_BDTR_OSSI (1 << 10) /* Bit 10: Off-State Selection for Idle mode */
#define ATIM_BDTR_OSSR (1 << 11) /* Bit 11: Off-State Selection for Run mode */

4
arch/xtensa/src/esp32s3/esp32s3_wireless.c
View File

@ -784,7 +784,7 @@ const esp_phy_init_data_t *esp_phy_get_init_data(void)
kmm_free(init_data_store);
return NULL;
}
#else /* CONFIG_ESP32S3_PHY_DEFAULT_INIT_IF_INVALID */
#else /* CONFIG_ESP32S3_PHY_DEFAULT_INIT_IF_INVALID */
wlerr("ERROR: Failed to validate PHY data partition\n");
kmm_free(init_data_store);
return NULL;
@ -828,7 +828,7 @@ void esp_phy_release_init_data(const esp_phy_init_data_t *init_data)
kmm_free((uint8_t *)init_data - sizeof(phy_init_magic_pre));
}
#else /* CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION */
#else /* CONFIG_ESP32S3_PHY_INIT_DATA_IN_PARTITION */
/****************************************************************************
* Name: esp_phy_get_init_data

2
include/nuttx/sensors/ioctl.h
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@ -364,7 +364,7 @@
/* Set proximity sensor cancellation level */
#define SNIOC_PS_CANC_LVL _SNIOC(0x0095) /* uint16_t level */
#define SNIOC_PS_CANC_LVL _SNIOC(0x0095) /* uint16_t level */
/* IOCTL commands for MPU60x0 IMU */