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Support for the STM32F429 from Ken Pettit

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This commit is contained in:
Gregory Nutt 2013-11-07 16:47:43 -06:00
parent cdc9bafd54
commit 9d653bdfee
15 changed files with 589 additions and 187 deletions
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2
ChangeLog
View File

@ -5988,4 +5988,6 @@
for a forthcoming SSC (aka I2S) driver for the SAMA5. The
initial check-in is just the SAMA5 SPI driver gutted and hacked
to use the I2S interface. More coming (2013-11-7).
* arch/arm/src/stm32 and arch/arm/include/stm32: Added support for
the STM32F429. From Ken Pettit (2013-11-7).

108
arch/arm/include/stm32/chip.h
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@ -1516,6 +1516,114 @@
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 6 /* SPI1-6 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437/429/439 */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 6 /* SPI1-6 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA
* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 4 /* SPI1-4 */
# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */
# define STM32_NI2C 3 /* I2C1-3 */
# define STM32_NCAN 2 /* CAN1-2 */
# define STM32_NSDIO 1 /* SDIO */
# define STM32_NLCD 0 /* No LCD */
# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
# define STM32_NGPIO 139 /* GPIOA-I */
# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32_NCRC 1 /* CRC */
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
#else
# error "Unsupported STM32 chip"

10
arch/arm/include/stm32/stm32f40xxx_irq.h
View File

@ -153,7 +153,7 @@
#define STM32_IRQ_RNG (STM32_IRQ_INTERRUPTS+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */
#ifndef CONFIG_STM32_STM32F427
#if !defined(CONFIG_STM32_STM32F427) && !defined(CONFIG_STM32_STM32F429)
# define NR_IRQS (STM32_IRQ_INTERRUPTS+82)
#else
# define STM32_IRQ_UART7 (STM32_IRQ_INTERRUPTS+82) /* 82: UART7 interrupt */
@ -161,8 +161,16 @@
# define STM32_IRQ_SPI4 (STM32_IRQ_INTERRUPTS+84) /* 84: SPI4 interrupt */
# define STM32_IRQ_SPI5 (STM32_IRQ_INTERRUPTS+85) /* 85: SPI5 interrupt */
# define STM32_IRQ_SPI6 (STM32_IRQ_INTERRUPTS+86) /* 86: SPI6 interrupt */
#if defined(CONFIG_STM32_STM32F429)
# define STM32_IRQ_SAI1 (STM32_IRQ_INTERRUPTS+87) /* 87: SAI1 interrupt */
# define STM32_IRQ_LTDCINT (STM32_IRQ_INTERRUPTS+88) /* 88: LTDCINT interrupt */
# define STM32_IRQ_LTDCERRINT (STM32_IRQ_INTERRUPTS+89) /* 89: LTDCERRINT interrupt */
# define STM32_IRQ_DMA2D (STM32_IRQ_INTERRUPTS+90) /* 90: DMA2D interrupt */
# define NR_IRQS (STM32_IRQ_INTERRUPTS+91)
#else
# define NR_IRQS (STM32_IRQ_INTERRUPTS+87)
#endif
#endif
/****************************************************************************************************
* Public Types

51
arch/arm/src/stm32/Kconfig
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@ -508,6 +508,41 @@ config ARCH_CHIP_STM32F427I
select STM32_STM32F427
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429V
bool "STM32F429V"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429Z
bool "STM32F429Z"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429I
bool "STM32F429I"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429B
bool "STM32F429B"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F429N
bool "STM32F429N"
select ARCH_CORTEXM4
select STM32_STM32F40XX
select STM32_STM32F429
select ARCH_HAVE_FPU
endchoice
config STM32_STM32L15XX
@ -562,6 +597,10 @@ config STM32_STM32F40XX
config STM32_STM32F427
bool
# This is really 429/439, but we treat the two the same.
config STM32_STM32F429
bool
config STM32_DFU
bool "DFU bootloader"
default n
@ -753,21 +792,21 @@ config STM32_SPI3
config STM32_SPI4
bool "SPI4"
default n
depends on STM32_STM32F427
depends on STM32_STM32F427 || STM32_STM32F429
select SPI
select STM32_SPI
config STM32_SPI5
bool "SPI5"
default n
depends on STM32_STM32F427
depends on STM32_STM32F427 || STM32_STM32F429
select SPI
select STM32_SPI
config STM32_SPI6
bool "SPI6"
default n
depends on STM32_STM32F427
depends on STM32_STM32F427 || STM32_STM32F429
select SPI
select STM32_SPI
@ -904,14 +943,14 @@ config STM32_USART6
config STM32_UART7
bool "UART7"
default n
depends on STM32_STM32F427
depends on STM32_STM32F427 || STM32_STM32F429
select ARCH_HAVE_UART7
select STM32_USART
config STM32_UART8
bool "UART8"
default n
depends on STM32_STM32F427
depends on STM32_STM32F427 || STM32_STM32F429
select ARCH_HAVE_UART8
select STM32_USART
@ -1133,7 +1172,7 @@ endmenu
config STM32_FLASH_PREFETCH
bool "Enable FLASH Pre-fetch"
depends on STM32_STM32F20XX || STM32_STM32F40XX
default y if STM32_STM32F427
default y if STM32_STM32F427 || STM32_STM32F429
default n
---help---
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled

10
arch/arm/src/stm32/chip/stm32_flash.h
View File

@ -94,7 +94,7 @@
# define STM32_FLASH_OPTCR_OFFSET 0x0014
#endif
#if defined(CONFIG_STM32_STM32F427)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define STM32_FLASH_OPTCR1_OFFSET 0x0018
#endif
@ -113,7 +113,7 @@
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
#endif
#if defined(CONFIG_STM32_STM32F427)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define STM32_FLASH_OPTCR1 (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR1_OFFSET)
#endif
@ -193,7 +193,7 @@
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
#if defined(CONFIG_STM32_STM32F427)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
#else
# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */
@ -208,7 +208,7 @@
# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
#endif
#if defined(CONFIG_STM32_STM32F427)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
#endif
@ -236,7 +236,7 @@
/* Flash Option Control Register (OPTCR1) */
#if defined(CONFIG_STM32_STM32F427)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */
# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
#endif

2
arch/arm/src/stm32/chip/stm32_i2c.h
View File

@ -51,7 +51,7 @@
#define STM32_I2C_SR2_OFFSET 0x0018 /* Status register 2 (16-bit) */
#define STM32_I2C_CCR_OFFSET 0x001c /* Clock control register (16-bit) */
#define STM32_I2C_TRISE_OFFSET 0x0020 /* TRISE Register (16-bit) */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define STM32_I2C_FLTR_OFFSET 0x0024 /* FLTR Register (16-bit) */
#endif

12
arch/arm/src/stm32/chip/stm32_pwr.h
View File

@ -92,7 +92,7 @@
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */
# if defined(CONFIG_STM32_STM32F427)
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define PWR_CR_ADCDC1 (1 << 13) /* Bit 13: see AN4073 for details */
# define PWR_CR_VOS_MASK (3 << 14) /* Bits 14-15: Regulator voltage scaling output selection */
# define PWR_CR_VOS_SCALE_1 (3 << 14) /* Fmax = 168MHz */
@ -114,6 +114,11 @@
# define PWR_CR_LPRUN (1 << 14) /* Low power run mode */
#endif
#if defined(CONFIG_STM32_STM32F429)
# define PWR_CR_ODEN (1 << 16) /* Over Drive enable */
# define PWR_CR_ODSWEN (1 << 17) /* Over Drive switch enabled */
#endif
/* Power control/status register */
#define PWR_CSR_WUF (1 << 0) /* Bit 0: Wakeup Flag */
@ -144,4 +149,9 @@
# define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */
#endif
#if defined(CONFIG_STM32_STM32F429)
# define PWR_CSR_ODRDY (1 << 16) /* Over Drive generator ready */
# define PWR_CSR_ODSWRDY (1 << 17) /* Over Drive Switch ready */
#endif
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_PWR_H */

16
arch/arm/src/stm32/chip/stm32f40xxx_dma.h
View File

@ -438,19 +438,19 @@
#define DMAMAP_USART2_TX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN4)
#define DMAMAP_UART5_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN4)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_UART8_TX STM32_DMA_MAP(DMA1,DMA_STREAM0,DMA_CHAN5)
# define DMAMAP_UART7_TX STM32_DMA_MAP(DMA1,DMA_STREAM1,DMA_CHAN5)
#endif
#define DMAMAP_TIM3_CH4 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
#define DMAMAP_TIM3_UP STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN5)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_UART7_RX STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN5)
#endif
#define DMAMAP_TIM3_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
#define DMAMAP_TIM3_TRIG STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN5)
#define DMAMAP_TIM3_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN5)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_UART8_RX STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN5)
#endif
#define DMAMAP_TIM3_CH3 STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN5)
@ -485,7 +485,7 @@
#define DMAMAP_DCMI_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN1)
#define DMAMAP_ADC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN1)
#define DMAMAP_ADC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN1)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_SPI6_TX STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN1)
# define DMAMAP_SPI6_RX STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN1)
#endif
@ -493,7 +493,7 @@
#define DMAMAP_ADC3_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN2)
#define DMAMAP_ADC3_2 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN2)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_SPI5_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN2)
# define DMAMAP_SPI5_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN2)
#endif
@ -506,7 +506,7 @@
#define DMAMAP_SPI1_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN3)
#define DMAMAP_SPI1_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN3)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_SPI4_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN4)
# define DMAMAP_SPI4_TX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN4)
#endif
@ -519,7 +519,7 @@
#define DMAMAP_USART6_RX_1 STM32_DMA_MAP(DMA2,DMA_STREAM1,DMA_CHAN5)
#define DMAMAP_USART6_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN5)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_SPI4_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN5)
# define DMAMAP_SPI4_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN5)
#endif
@ -540,7 +540,7 @@
#define DMAMAP_TIM8_CH1_2 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN7)
#define DMAMAP_TIM8_CH2_2 STM32_DMA_MAP(DMA2,DMA_STREAM3,DMA_CHAN7)
#define DMAMAP_TIM8_CH3_2 STM32_DMA_MAP(DMA2,DMA_STREAM4,DMA_CHAN7)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define DMAMAP_SPI5_RX_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN7)
# define DMAMAP_SPI5_TX_2 STM32_DMA_MAP(DMA2,DMA_STREAM6,DMA_CHAN7)
#endif

126
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
View File

@ -301,6 +301,19 @@
#define GPIO_FSMC_NWAIT (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
#define GPIO_FSMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
#ifdef CONFIG_STM32_STM32F429
# define GPIO_FSMC_SDCKE0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
# define GPIO_FSMC_SDNE0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
# define GPIO_FSMC_SDCKE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_FSMC_SDNE1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_FSMC_SDNWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
# define GPIO_FSMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
# define GPIO_FSMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
# define GPIO_FSMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
# define GPIO_FSMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
# define GPIO_FSMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
#endif
/* I2C */
#define GPIO_I2C1_SCL_1 (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
@ -331,7 +344,7 @@
#define GPIO_I2S2_CK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2S2_CK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
#define GPIO_I2S2_CK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_I2S2_CK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
#endif
#define GPIO_I2S2_MCK (GPIO_ALT|GPIO_AF5|GPIO_PORTC|GPIO_PIN6)
@ -342,7 +355,7 @@
#define GPIO_I2S2_WS_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
#define GPIO_I2S2_WS_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN9)
#define GPIO_I2S2_WS_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN0)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_I2S2_WS_6 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN6)
#endif
@ -355,7 +368,7 @@
#define GPIO_I2S3_MCK (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN7)
#define GPIO_I2S3_SD_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2S3_SD_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_I2S3_SD_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
#endif
#define GPIO_I2S3_WS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN4)
@ -383,6 +396,15 @@
#define GPIO_OTGFS_SDA (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN9)
#define GPIO_OTGFS_SOF (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
#ifdef CONFIG_STM32_STM32F429
# define GPIO_OTG2FS_DM (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN14)
# define GPIO_OTG2FS_DP (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN15)
# define GPIO_OTG2FS_ID (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN12)
# define GPIO_OTG2FS_SCL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
# define GPIO_OTG2FS_SDA (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
# define GPIO_OTG2FS_SOF (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN4)
#endif
#define GPIO_OTGHS_DM (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN14)
#define GPIO_OTGHS_DP (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN15)
#define GPIO_OTGHS_ID (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN12)
@ -391,6 +413,7 @@
#define GPIO_OTGHS_SCL (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN10)
#define GPIO_OTGHS_SDA (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN11)
#define GPIO_OTGHS_SOF (GPIO_ALT|GPIO_AF12|GPIO_PORTA|GPIO_PIN4)
#define GPIO_OTGHS_ULPI_CK (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN5)
#define GPIO_OTGHS_ULPI_D0 (GPIO_ALT|GPIO_AF10|GPIO_PORTA|GPIO_PIN3)
#define GPIO_OTGHS_ULPI_D1 (GPIO_ALT|GPIO_AF10|GPIO_PORTB|GPIO_PIN0)
@ -446,7 +469,7 @@
#define GPIO_SPI2_SCK_1 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN10)
#define GPIO_SPI2_SCK_2 (GPIO_ALT|GPIO_AF5|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SPI2_SCK_3 (GPIO_ALT|GPIO_AF5|GPIO_PORTI|GPIO_PIN1)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_SPI2_SCK_4 (GPIO_ALT|GPIO_AF5|GPIO_PORTD|GPIO_PIN3)
#endif
@ -454,7 +477,7 @@
#define GPIO_SPI3_MISO_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN11)
#define GPIO_SPI3_MOSI_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN5)
#define GPIO_SPI3_MOSI_2 (GPIO_ALT|GPIO_AF6|GPIO_PORTC|GPIO_PIN12)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_SPI3_MOSI_3 (GPIO_ALT|GPIO_AF6|GPIO_PORTD|GPIO_PIN6)
#endif
#define GPIO_SPI3_NSS_1 (GPIO_ALT|GPIO_AF6|GPIO_PORTA|GPIO_PIN15)
@ -729,7 +752,7 @@
#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define GPIO_UART7_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN7)
# define GPIO_UART7_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN6)
# define GPIO_UART7_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN8)
@ -739,5 +762,94 @@
# define GPIO_UART8_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1)
#endif
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H */
/* LCD-TFT Display Controller (LTDC) */
#if defined(CONFIG_STM32_STM32F429)
# define GPIO_LTDC_R0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
# define GPIO_LTDC_R0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN15)
# define GPIO_LTDC_R1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
# define GPIO_LTDC_R1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN0)
# define GPIO_LTDC_R2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
# define GPIO_LTDC_R2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN8)
# define GPIO_LTDC_R2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN1)
# define GPIO_LTDC_R3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
//# define GPIO_LTDC_R3_ (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
# define GPIO_LTDC_R3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN9)
# define GPIO_LTDC_R3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN2)
# define GPIO_LTDC_R4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
# define GPIO_LTDC_R4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN10)
# define GPIO_LTDC_R4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN3)
# define GPIO_LTDC_R5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
# define GPIO_LTDC_R5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN11)
# define GPIO_LTDC_R5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN4)
# define GPIO_LTDC_R6_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
//# define GPIO_LTDC_R6_ (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
# define GPIO_LTDC_R6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN12)
# define GPIO_LTDC_R6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN5)
# define GPIO_LTDC_R7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6)
# define GPIO_LTDC_R7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN15)
# define GPIO_LTDC_R7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN6)
# define GPIO_LTDC_G0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN5)
# define GPIO_LTDC_G0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN7)
# define GPIO_LTDC_G1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN6)
# define GPIO_LTDC_G1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN8)
# define GPIO_LTDC_G2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
# define GPIO_LTDC_G2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN13)
# define GPIO_LTDC_G2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN9)
# define GPIO_LTDC_G3_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
//# define GPIO_LTDC_G3_ (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN11)
# define GPIO_LTDC_G3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN14)
# define GPIO_LTDC_G3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN10)
# define GPIO_LTDC_G4_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
# define GPIO_LTDC_G4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN15)
# define GPIO_LTDC_G4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN11)
# define GPIO_LTDC_G5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
# define GPIO_LTDC_G5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN0)
# define GPIO_LTDC_G5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN0)
# define GPIO_LTDC_G6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
# define GPIO_LTDC_G6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN1)
# define GPIO_LTDC_G6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN1)
# define GPIO_LTDC_G7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN3)
# define GPIO_LTDC_G7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN2)
# define GPIO_LTDC_G7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN2)
# define GPIO_LTDC_B0_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN4)
# define GPIO_LTDC_B0_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN12)
# define GPIO_LTDC_B1_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
# define GPIO_LTDC_B1_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN13)
# define GPIO_LTDC_B2_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
# define GPIO_LTDC_B2_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10)
# define GPIO_LTDC_B2_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN14)
# define GPIO_LTDC_B3_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
# define GPIO_LTDC_B3_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN10)
# define GPIO_LTDC_B3_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTJ|GPIO_PIN15)
# define GPIO_LTDC_B4_1 (GPIO_ALT|GPIO_AF9 |GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12)
# define GPIO_LTDC_B4_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN12)
# define GPIO_LTDC_B4_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN4)
# define GPIO_LTDC_B4_4 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN3)
# define GPIO_LTDC_B5_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
# define GPIO_LTDC_B5_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN5)
# define GPIO_LTDC_B5_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN4)
# define GPIO_LTDC_B6_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
# define GPIO_LTDC_B6_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN6)
# define GPIO_LTDC_B6_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN5)
# define GPIO_LTDC_B7_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
# define GPIO_LTDC_B7_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN7)
# define GPIO_LTDC_B7_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN6)
# define GPIO_LTDC_VSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
# define GPIO_LTDC_VSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN9)
# define GPIO_LTDC_VSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13)
# define GPIO_LTDC_HSYNC_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
# define GPIO_LTDC_HSYNC_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
# define GPIO_LTDC_HSYNC_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN12)
# define GPIO_LTDC_DE_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN10)
# define GPIO_LTDC_DE_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN13)
# define GPIO_LTDC_DE_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTK|GPIO_PIN7)
# define GPIO_LTDC_CLK_1 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7)
# define GPIO_LTDC_CLK_2 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN14)
# define GPIO_LTDC_CLK_3 (GPIO_ALT|GPIO_AF14|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN14)
#endif
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H */

26
arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
View File

@ -65,7 +65,7 @@
#define STM32_RCC_CSR_OFFSET 0x0074 /* Control/status register */
#define STM32_RCC_SSCGR_OFFSET 0x0080 /* Spread spectrum clock generation register */
#define STM32_RCC_PLLI2SCFGR_OFFSET 0x0084 /* PLLI2S configuration register */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define STM32_RCC_DCKCFGR_OFFSET 0x008c /* Dedicated clocks configuration register */
#endif
@ -94,7 +94,7 @@
#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
#define STM32_RCC_SSCGR (STM32_RCC_BASE+STM32_RCC_SSCGR_OFFSET)
#define STM32_RCC_PLLI2SCFGR (STM32_RCC_BASE+STM32_RCC_PLLI2SCFGR_OFFSET)
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define STM32_RCC_DCKCFGR (STM32_RCC_BASE+STM32_RCC_DCKCFGR_OFFSET)
#endif
@ -288,7 +288,7 @@
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: USART 7 reset */
# define RCC_APB1RSTR_UART8RST (1 << 31) /* Bit 31: USART 8 reset */
#endif
@ -302,14 +302,14 @@
#define RCC_APB2RSTR_ADCRST (1 << 8) /* Bit 8: ADC interface reset (common to all ADCs) */
#define RCC_APB2RSTR_SDIORST (1 << 11) /* Bit 11: SDIO reset */
#define RCC_APB2RSTR_SPI1RST (1 << 12) /* Bit 12: SPI1 reset */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB2RSTR_SPI4RST (1 << 13) /* Bit 13: SPI4 reset */
#endif
#define RCC_APB2RSTR_SYSCFGRST (1 << 14) /* Bit 14: System configuration controller reset */
#define RCC_APB2RSTR_TIM9RST (1 << 16) /* Bit 16: TIM9 reset */
#define RCC_APB2RSTR_TIM10RST (1 << 17) /* Bit 17: TIM10 reset */
#define RCC_APB2RSTR_TIM11RST (1 << 18) /* Bit 18: TIM11 reset */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB2RSTR_SPI5RST (1 << 20) /* Bit 20: SPI 5 reset */
# define RCC_APB2RSTR_SPI6RST (1 << 21) /* Bit 21: SPI 6 reset */
#endif
@ -375,7 +375,7 @@
#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */
# define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */
#endif
@ -391,14 +391,14 @@
#define RCC_APB2ENR_ADC3EN (1 << 10) /* Bit 10: ADC3 clock enable */
#define RCC_APB2ENR_SDIOEN (1 << 11) /* Bit 11: SDIO clock enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 clock enable */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB2ENR_SPI4EN (1 << 13) /* Bit 13: SPI4 clock enable */
#endif
#define RCC_APB2ENR_SYSCFGEN (1 << 14) /* Bit 14: System configuration controller clock enable */
#define RCC_APB2ENR_TIM9EN (1 << 16) /* Bit 16: TIM9 clock enable */
#define RCC_APB2ENR_TIM10EN (1 << 17) /* Bit 17: TIM10 clock enable */
#define RCC_APB2ENR_TIM11EN (1 << 18) /* Bit 18: TIM11 clock enable */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB2ENR_SPI5EN (1 << 20) /* Bit 20: SPI5 clock enable */
# define RCC_APB2ENR_SPI6EN (1 << 21) /* Bit 21: SPI6 clock enable */
#endif
@ -420,7 +420,7 @@
#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_AHB1LPENR_SRAM3LPEN (1 << 19) /* Bit 19: SRAM 3 interface clock enable during Sleep mode */
#endif
#define RCC_AHB1LPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
@ -471,7 +471,7 @@
#define RCC_APB1LPENR_CAN2LPEN (1 << 26) /* Bit 26: CAN 2 clock enable during Sleep mode */
#define RCC_APB1LPENR_PWRLPEN (1 << 28) /* Bit 28: Power interface clock enable during Sleep mode */
#define RCC_APB1LPENR_DACLPEN (1 << 29) /* Bit 29: DAC interface clock enable during Sleep mode */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB1LPENR_UART7LPEN (1 << 30) /* Bit 30: UART7 clock enable during Sleep mode */
# define RCC_APB1LPENR_UART8LPEN (1 << 31) /* Bit 31: UART8 clock enable during Sleep mode */
#endif
@ -487,14 +487,14 @@
#define RCC_APB2LPENR_ADC3LPEN (1 << 10) /* Bit 10: ADC3 clock enable during Sleep mode */
#define RCC_APB2LPENR_SDIOLPEN (1 << 11) /* Bit 11: SDIO clock enable during Sleep mode */
#define RCC_APB2LPENR_SPI1LPEN (1 << 12) /* Bit 12: SPI1 clock enable during Sleep mode */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB2LPENR_SPI4LPEN (1 << 13) /* Bit 13: SPI4 clock enable during Sleep mode */
#endif
#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) /* Bit 14: System configuration controller clock enable during Sleep mode */
#define RCC_APB2LPENR_TIM9LPEN (1 << 16) /* Bit 16: TIM9 clock enable during Sleep mode */
#define RCC_APB2LPENR_TIM10LPEN (1 << 17) /* Bit 17: TIM10 clock enable during Sleep mode */
#define RCC_APB2LPENR_TIM11LPEN (1 << 18) /* Bit 18: TIM11 clock enable during Sleep mode */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_APB2LPENR_SPI5LPEN (1 << 20) /* Bit 20: SPI5 clock enable during Sleep mode */
# define RCC_APB2LPENR_SPI6LPEN (1 << 21) /* Bit 21: SPI6 clock enable during Sleep mode */
#endif
@ -546,7 +546,7 @@
/* Dedicated clocks configuration register */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define RCC_DCKCFGR_TIMPRE (1 << 24) /* Bit 24: Timer clock prescaler selection */
#endif

2
arch/arm/src/stm32/chip/stm32f40xxx_syscfg.h
View File

@ -89,7 +89,7 @@
/* SYSCFG peripheral mode configuration register */
#define SYSCFG_PMC_MII_RMII_SEL (1 << 23) /* Bit 23: Ethernet PHY interface selection */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define SYSCFG_PMC_ADC3DC2 (1 << 18) /* Bit 18: See AN4073 */
# define SYSCFG_PMC_ADC2DC2 (1 << 17) /* Bit 17: See AN4073 */
# define SYSCFG_PMC_ADC1DC2 (1 << 16) /* Bit 16: See AN4073 */

11
arch/arm/src/stm32/chip/stm32f40xxx_vectors.h
View File

@ -52,7 +52,7 @@
/* Reserve interrupt table entries for I/O interrupts. */
# ifdef CONFIG_STM32_STM32F427
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define ARMV7M_PERIPHERAL_INTERRUPTS 87
# else
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
@ -143,7 +143,7 @@ VECTOR(stm32_cryp, STM32_IRQ_CRYP) /* Vector 16+79: CRYP crypto gl
VECTOR(stm32_hash, STM32_IRQ_HASH) /* Vector 16+80: Hash and Rng global interrupt */
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* Vector 16+81: FPU global interrupt */
#ifdef CONFIG_STM32_STM32F427
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
VECTOR(stm32_uart7, STM32_IRQ_UART7) /* Vector 16+82: UART7 interrupt */
VECTOR(stm32_uart8, STM32_IRQ_UART8) /* Vector 16+83: UART8 interrupt */
VECTOR(stm32_spi4, STM32_IRQ_SPI4) /* Vector 16+84: SPI4 interrupt */
@ -151,4 +151,11 @@ VECTOR(stm32_spi5, STM32_IRQ_SPI5) /* Vector 16+85: SPI5 interrupt
VECTOR(stm32_spi6, STM32_IRQ_SPI6) /* Vector 16+86: SPI6 interrupt */
#endif
#if defined(CONFIG_STM32_STM32F429)
VECTOR(stm32_sai1, STM32_IRQ_SAI1) /* Vector 16+87: SAI1 interrupt */
VECTOR(stm32_ltdcint, STM32_IRQ_LTDCINT) /* Vector 16+88: LTDC interrupt */
VECTOR(stm32_ltdcerrint, STM32_IRQ_LTDCERRINT) /* Vector 16+89: LTDC Error interrupt */
VECTOR(stm32_dma2d, STM32_IRQ_DMA2D) /* Vector 16+90: DMA2D interrupt */
#endif
#endif /* CONFIG_ARMV7M_CMNVECTOR */

8
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -229,15 +229,15 @@
*
* 3) 64Kib of CCM SRAM beginning at address 0x1000:0000
*
* The STM32F427/437 parts have another 64KiB of System SRAM for a total of
* 256KiB.
* The STM32F427/437/429/439 parts have another 64KiB of System SRAM for a total
* of 256KiB.
*
* 3) 64Kib of System SRAM beginning at address 0x2002:0000
*
* As determined by ld.script, g_heapbase lies in the 112KiB memory
* region and that extends to 0x2001:0000. But the first and second memory
* regions are contiguous and treated as one in this logic that extends to
* 0x2002:0000 (or 0x2003:0000 for the F427/F437).
* 0x2002:0000 (or 0x2003:0000 for the F427/F437/F429/F439).
*
* As a complication, CCM SRAM cannot be used for DMA. So, if STM32 DMA is enabled,
* CCM SRAM should probably be excluded from the heap or the application must take
@ -257,7 +257,7 @@
/* Set the end of system SRAM */
# if defined(CONFIG_STM32_STM32F427)
# if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define SRAM1_END 0x20030000
# else
# define SRAM1_END 0x20020000

363
arch/arm/src/stm32/stm32_fsmc.h
View File

@ -94,6 +94,18 @@
#define STM32_FSMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */
#define STM32_FSMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */
#if defined(CONFIG_STM32_STM32F429)
# define STM32_FSMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
# define STM32_FSMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
# define STM32_FSMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register?, Bank 0 */
# define STM32_FSMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register?, Bank 1 */
# define STM32_FSMC_SDCMR_OFFSET 0x0150 /* SDRAM Config register? */
# define STM32_FSMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe? */
# define STM32_FSMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
#endif
/* Register Addresses ***************************************************************/
#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE+STM32_FSMC_BCR_OFFSET(n))
@ -140,154 +152,235 @@
#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE+STM32_FSMC_ECCR2_OFFSET )
#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE+STM32_FSMC_ECCR3_OFFSET )
#if defined(CONFIG_STM32_STM32F429)
# define STM32_FSMC_SDCR1 (STM32_FSMC_BASE+STM32_FSMC_SDCR1_OFFSET)
# define STM32_FSMC_SDCR2 (STM32_FSMC_BASE+STM32_FSMC_SDCR2_OFFSET)
# define STM32_FSMC_SDTR1 (STM32_FSMC_BASE+STM32_FSMC_SDTR1_OFFSET)
# define STM32_FSMC_SDTR2 (STM32_FSMC_BASE+STM32_FSMC_SDTR2_OFFSET)
# define STM32_FSMC_SDCMR (STM32_FSMC_BASE+STM32_FSMC_SDCMR_OFFSET)
# define STM32_FSMC_SDRTR (STM32_FSMC_BASE+STM32_FSMC_SDRTR_OFFSET)
# define STM32_FSMC_SDSR (STM32_FSMC_BASE+STM32_FSMC_SDSR_OFFSET)
#endif
/* Register Bitfield Definitions ****************************************************/
#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT)
#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT)
#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#define FSMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
#define FSMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
#define FSMC_BCR_MTYP_SHIFT (2) /* Memory type */
#define FSMC_BCR_MTYP_MASK (3 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_SRAM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_ROM (0 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_PSRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_CRAM (1 << FSMC_BCR_MTYP_SHIFT)
# define FSMC_BCR_NOR (2 << FSMC_BCR_MTYP_SHIFT)
#define FSMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
#define FSMC_BCR_MWID_MASK (3 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID8 (0 << FSMC_BCR_MWID_SHIFT)
# define FSMC_BCR_MWID16 (1 << FSMC_BCR_MWID_SHIFT)
#define FSMC_BCR_FACCEN (1 << 6) /* Flash access enable */
#define FSMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
#define FSMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
#define FSMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
#define FSMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
#endif
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
#define FSMC_BCR_RSTVALUE 0x000003d2
#define FSMC_BCR_RSTVALUE 0x000003d2
#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT)
# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT)
# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT)
# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT)
# define FSMC_BTR_BUSTRUN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT)
# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT)
# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BTR_ADDSET_MASK (15 << FSMC_BTR_ADDSET_SHIFT)
# define FSMC_BTR_ADDSET(n) ((n-1) << FSMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BTR_ADDHLD_MASK (15 << FSMC_BTR_ADDHLD_SHIFT)
# define FSMC_BTR_ADDHLD(n) ((n-1) << FSMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BTR_DATAST_MASK (255 << FSMC_BTR_DATAST_SHIFT)
# define FSMC_BTR_DATAST(n) ((n-1) << FSMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
#define FSMC_BTR_BUSTURN_MASK (15 << FSMC_BTR1_BUSTURN_SHIFT)
# define FSMC_BTR_BUSTRUN(n) ((n-1) << FSMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BTR_CLKDIV_MASK (15 << FSMC_BTR_CLKDIV_SHIFT)
# define FSMC_BTR_CLKDIV(n) ((n-1) << FSMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BTR_DATLAT_MASK (15 << FSMC_BTR_DATLAT_SHIFT)
# define FSMC_BTR_DATLAT(n) ((n-2) << FSMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BTR_ACCMOD_MASK (3 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODA (0 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODB (1 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODC (2 << FSMC_BTR_ACCMOD_SHIFT)
# define FSMC_BTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_BTR_RSTVALUE 0xffffffff
#define FSMC_BTR_RSTVALUE 0xffffffff
#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT)
# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT)
# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT)
# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT)
# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT)
# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
#define FSMC_BWTR_ADDSET_MASK (15 << FSMC_BWTR_ADDSET_SHIFT)
# define FSMC_BWTR_ADDSET(n) ((n-1) << FSMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
#define FSMC_BWTR_ADDHLD_MASK (15 << FSMC_BWTR_ADDHLD_SHIFT)
# define FSMC_BWTR_ADDHLD(n) ((n-1) << FSMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
#define FSMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
#define FSMC_BWTR_DATAST_MASK (255 << FSMC_BWTR_DATAST_SHIFT)
# define FSMC_BWTR_DATAST(n) ((n-1) << FSMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
#define FSMC_BWTR_CLKDIV_MASK (15 << FSMC_BWTR_CLKDIV_SHIFT)
# define FSMC_BWTR_CLKDIV(n) ((n-1) << FSMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
#define FSMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
#define FSMC_BWTR_DATLAT_MASK (15 << FSMC_BWTR_DATLAT_SHIFT)
# define FSMC_BWTR_DATLAT(n) ((n-2) << FSMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
#define FSMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
#define FSMC_BWTR_ACCMOD_MASK (3 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODA (0 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODB (1 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODC (2 << FSMC_BWTR_ACCMOD_SHIFT)
# define FSMC_BWTR_ACCMODD (3 << FSMC_BTR_ACCMOD_SHIFT)
#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR_PTYP (1 << 3) /* Memory type */
#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT)
#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT)
# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK)
# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT)
# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FSMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
#define FSMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
#define FSMC_PCR_PTYP (1 << 3) /* Memory type */
#define FSMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
#define FSMC_PCR_PWID_MASK (3 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID8 (0 << FSMC_PCR_PWID_SHIFT)
# define FSMC_PCR_PWID16 (1 << FSMC_PCR_PWID_SHIFT)
#define FSMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
#define FSMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
#define FSMC_PCR_TCLR_MASK (15 << FSMC_PCR_TCLR_SHIFT)
# define FSMC_PCR_TCLR(n) ((n-1) << FSMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
#define FSMC_PCR_TAR_MASK (15 << FSMC_PCR_TAR_MASK)
# define FSMC_PCR_TAR(n) ((n-1) << FSMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
#define FSMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
#define FSMC_PCR_ECCPS_MASK (7 << FSMC_PCR_ECCPS_SHIFT)
# define FSMC_PCR_ECCPS256 (0 << FSMC_PCR_ECCPS_SHIFT) /* 256 bytes */
# define FSMC_PCR_ECCPS512 (1 << FSMC_PCR_ECCPS_SHIFT) /* 512 bytes */
# define FSMC_PCR_ECCPS1024 (2 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
# define FSMC_PCR_ECCPS2048 (3 << FSMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
# define FSMC_PCR_ECCPS4096 (4 << FSMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
# define FSMC_PCR_ECCPS8192 (5 << FSMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FSMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
#define FSMC_SR_ILS (1 << 1) /* Interrupt Level status */
#define FSMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
#define FSMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
#define FSMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
#define FSMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
#define FSMC_SR_FEMPT (1 << 6) /* FIFO empty */
#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT)
# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT)
# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT)
# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT)
# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
#define FSMC_PMEM_MEMSET_MASK (255 << FSMC_PMEM_MEMSET_SHIFT)
# define FSMC_PMEM_MEMSET(n) ((n-1) << FSMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
#define FSMC_PMEM_MEMWAIT_MASK (255 << FSMC_PMEM_MEMWAIT_SHIFT)
# define FSMC_PMEM_MEMWAIT(n) ((n-1) << FSMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
#define FSMC_PMEM_MEMHOLD_MASK (255 << FSMC_PMEM_MEMHOLD_SHIFT)
# define FSMC_PMEM_MEMHOLD(n) ((n) << FSMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
#define FSMC_PMEM_MEMHIZ_MASK (255 << FSMC_PMEM_MEMHIZ_SHIFT)
# define FSMC_PMEM_MEMHIZ(n) ((n) << FSMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT)
# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT)
# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT)
# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT)
# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
#define FSMC_PATT_ATTSET_MASK (255 << FSMC_PATT_ATTSET_SHIFT)
# define FSMC_PATT_ATTSET(n) ((n-1) << FSMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
#define FSMC_PATT_ATTWAIT_MASK (255 << FSMC_PATT_ATTWAIT_SHIFT)
# define FSMC_PATT_ATTWAIT(n) ((n-1) << FSMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
#define FSMC_PATT_ATTHOLD_MASK (255 << FSMC_PATT_ATTHOLD_SHIFT)
# define FSMC_PATT_ATTHOLD(n) ((n) << FSMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
#define FSMC_PATT_ATTHIZ_MASK (255 << FSMC_PATT_ATTHIZ_SHIFT)
# define FSMC_PATT_ATTHIZ(n) ((n) << FSMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PIO4_IOSET_SHIFT (0) /* IOribute memory setup time */
#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT)
# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IOribute memory wait time */
#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT)
# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IOribute memory hold time */
#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT)
# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IOribute memory databus HiZ time */
#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT)
# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#define FSMC_PIO4_IOSET_SHIFT (0) /* IOribute memory setup time */
#define FSMC_PIO4_IOSET_MASK (255 << FSMC_PIO4_IOSET_SHIFT)
# define FSMC_PIO4_IOSET(n) ((n-1) << FSMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
#define FSMC_PIO4_IOWAIT_SHIFT (8) /* IOribute memory wait time */
#define FSMC_PIO4_IOWAIT_MASK (255 << FSMC_PIO4_IOWAIT_SHIFT)
# define FSMC_PIO4_IOWAIT(n) ((n-1) << FSMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
#define FSMC_PIO4_IOHOLD_SHIFT (16) /* IOribute memory hold time */
#define FSMC_PIO4_IOHOLD_MASK (255 << FSMC_PIO4_IOHOLD_SHIFT)
# define FSMC_PIO4_IOHOLD(n) ((n) << FSMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
#define FSMC_PIO4_IOHIZ_SHIFT (24) /* IOribute memory databus HiZ time */
#define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT)
# define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
#if defined(CONFIG_STM32_STM32F429)
# define FSMC_SDRAM_CR_COLBITS_8 0x00000000
# define FSMC_SDRAM_CR_COLBITS_9 0x00000001
# define FSMC_SDRAM_CR_COLBITS_10 0x00000002
# define FSMC_SDRAM_CR_COLBITS_11 0x00000003
# define FSMC_SDRAM_CR_ROWBITS_11 0x00000000
# define FSMC_SDRAM_CR_ROWBITS_12 0x00000004
# define FSMC_SDRAM_CR_ROWBITS_13 0x00000008
# define FSMC_SDRAM_CR_WIDTH_8 0x00000000
# define FSMC_SDRAM_CR_WIDTH_16 0x00000010
# define FSMC_SDRAM_CR_WIDTH_32 0x00000020
# define FSMC_SDRAM_CR_BANKS_2 0x00000000
# define FSMC_SDRAM_CR_BANKS_4 0x00000040
# define FSMC_SDRAM_CR_CASLAT_1 0x00000080
# define FSMC_SDRAM_CR_CASLAT_2 0x00000100
# define FSMC_SDRAM_CR_CASLAT_3 0x00000180
# define FSMC_SDRAM_CR_WRITE_PROT 0x00000200
# define FSMC_SDRAM_CR_SDCLK_DISABLE 0x00000000
# define FSMC_SDRAM_CR_SDCLK_2X 0x00000800
# define FSMC_SDRAM_CR_SDCLK_3X 0x00000C00
# define FSMC_SDRAM_CR_BURST_READ 0x00001000
# define FSMC_SDRAM_CR_RPIPE_0 0x00000000
# define FSMC_SDRAM_CR_RPIPE_1 0x00002000
# define FSMC_SDRAM_CR_RPIPE_2 0x00004000
# define FSMC_SDRAM_TR_TMRD_SHIFT 0
# define FSMC_SDRAM_TR_TXSR_SHIFT 4
# define FSMC_SDRAM_TR_TRAS_SHIFT 8
# define FSMC_SDRAM_TR_TRC_SHIFT 12
# define FSMC_SDRAM_TR_TWR_SHIFT 16
# define FSMC_SDRAM_TR_TRP_SHIFT 20
# define FSMC_SDRAM_TR_TRCD_SHIFT 24
# define FSMC_SDRAM_MODE_CMD_NORMAL 0
# define FSMC_SDRAM_MODE_CMD_CLK_ENABLE 1
# define FSMC_SDRAM_MODE_CMD_PALL 2
# define FSMC_SDRAM_MODE_CMD_AUTO_REFRESH 3
# define FSMC_SDRAM_MODE_CMD_LOAD_MODE 4
# define FSMC_SDRAM_MODE_CMD_SELF_REFRESH 5
# define FSMC_SDRAM_MODE_CMD_POWER_DOWN 6
# define FSMC_SDRAM_CMD_BANK_1 0x00000010
# define FSMC_SDRAM_CMD_BANK_2 0x00000008
# define FSMC_SDRAM_AUTO_REFRESH_SHIFT 5
# define FSMC_SDRAM_MODEREG_SHIFT 9
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FSMC_SDRAM_MODEREG_SHIFT)
# define FSMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FSMC_SDRAM_MODEREG_SHIFT)
#endif
/************************************************************************************
* Public Types

29
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -622,7 +622,7 @@ static void stm32_stdclockconfig(void)
putreg32(regval, STM32_RCC_APB1ENR);
regval = getreg32(STM32_PWR_CR);
#if defined(CONFIG_STM32_STM32F427)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
regval &= ~PWR_CR_VOS_MASK;
regval |= PWR_CR_VOS_SCALE_1;
#else
@ -665,8 +665,29 @@ static void stm32_stdclockconfig(void)
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
{
}
#if defined(CONFIG_STM32_STM32F429)
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
regval = getreg32(STM32_PWR_CR);
regval |= PWR_CR_ODEN;
putreg32(regval, STM32_PWR_CR);
while((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
{
}
regval = getreg32(STM32_PWR_CR);
regval |= PWR_CR_ODSWEN;
putreg32(regval, STM32_PWR_CR);
while((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
{
}
#endif
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
#ifdef CONFIG_STM32_FLASH_PREFETCH
@ -685,7 +706,9 @@ static void stm32_stdclockconfig(void)
/* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
{
}
}
}
#endif