SAM4CM: Fixes from Macs N
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@ -64,7 +64,7 @@
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UNUSED(SAM_IRQ_RESERVED_7) /* Vector 16+7: Reserved */
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UNUSED(SAM_IRQ_RESERVED_7) /* Vector 16+7: Reserved */
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VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */
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VECTOR(sam_uart0, SAM_IRQ_UART0) /* Vector 16+8: Universal Asynchronous Receiver Transmitter 0 */
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UNUSED(SAM_IRQ_RESERVED_9) /* Vector 16+9: Reserved */
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UNUSED(SAM_IRQ_RESERVED_9) /* Vector 16+9: Reserved */
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//VECTOR(sam_smc, SAM_IRQ_SMC) /* Vector 16+10: Static Memory Controller */
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UNUSED(SAM_IRQ_RESERVED_10) /* Vector 16+10: Unused */
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VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */
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VECTOR(sam_pioa, SAM_IRQ_PIOA) /* Vector 16+11: Parallel I/O Controller A */
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VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */
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VECTOR(sam_piob, SAM_IRQ_PIOB) /* Vector 16+12: Parallel I/O Controller B */
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UNUSED(SAM_IRQ_RESERVED_13) /* Vector 16+13: Reserved */
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UNUSED(SAM_IRQ_RESERVED_13) /* Vector 16+13: Reserved */
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@ -414,19 +414,19 @@
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/* PMC Programmable Clock Register (0,1,2) */
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/* PMC Programmable Clock Register (0,1,2) */
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#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
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#define PMC_PCK_CSS_SHIFT (0) /* Bits 0-2: Master Clock Source Selection */
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#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_MASK)
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#define PMC_PCK_CSS_MASK (7 << PMC_PCK_CSS_SHIFT)
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# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_MASK) /* Slow Clock */
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# define PMC_PCK_CSS_SLOW (0 << PMC_PCK_CSS_SHIFT) /* Slow Clock */
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# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_MASK) /* Main Clock */
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# define PMC_PCK_CSS_MAIN (1 << PMC_PCK_CSS_SHIFT) /* Main Clock */
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# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_MASK) /* PLLA Clock */
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# define PMC_PCK_CSS_PLLA (2 << PMC_PCK_CSS_SHIFT) /* PLLA Clock */
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#if defined(CONFIG_ARCH_CHIP_SAM4S)
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#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
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# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_MASK) /* PLLB Clock */
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# define PMC_PCK_CSS_PLLB (3 << PMC_PCK_CSS_SHIFT) /* PLLB Clock */
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#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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#elif defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
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defined(CONFIG_ARCH_CHIP_SAM3U)
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defined(CONFIG_ARCH_CHIP_SAM3U)
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# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_MASK) /* UPLL Clock */
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# define PMC_PCK_CSS_UPLL (3 << PMC_PCK_CSS_SHIFT) /* UPLL Clock */
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#endif
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#endif
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# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_MASK) /* Master Clock */
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# define PMC_PCK_CSS_MCK (4 << PMC_PCK_CSS_SHIFT) /* Master Clock */
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#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
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#define PMC_PCK_PRES_SHIFT (4) /* Bits 4-6: Programmable Clock Prescaler */
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#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
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#define PMC_PCK_PRES_MASK (7 << PMC_PCK_PRES_SHIFT)
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@ -239,16 +239,16 @@ static inline void sam_pmcsetup(void)
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//putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
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//putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
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#endif
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#endif
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/* Setup PLLA and wait for LOCKA */
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putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
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sam_pmcwait(PMC_INT_LOCKA);
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#ifdef CONFIG_ARCH_CHIP_SAM4CM
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#ifdef CONFIG_ARCH_CHIP_SAM4CM
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/* Setup PLLB and wait for LOCKB */
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/* Setup PLLB and wait for LOCKB */
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putreg32(BOARD_CKGR_PLLBR, SAM_PMC_CKGR_PLLBR);
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putreg32(BOARD_CKGR_PLLBR, SAM_PMC_CKGR_PLLBR);
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sam_pmcwait(PMC_INT_LOCKB);
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sam_pmcwait(PMC_INT_LOCKB);
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#else
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/* Setup PLLA and wait for LOCKA */
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putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
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sam_pmcwait(PMC_INT_LOCKA);
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#endif
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#endif
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#ifdef CONFIG_USBDEV
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#ifdef CONFIG_USBDEV
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