Rename board_led_initialize to board_autoled_initiaize
This commit is contained in:
Gregory Nutt
parent
4131081e72
commit
9db4b4ca7e
@ -125,7 +125,7 @@ __start:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
bl board_led_initialize
|
||||
bl board_autoled_initialize
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STACK_COLORATION
|
||||
|
||||
@ -225,8 +225,9 @@ void up_boot(void)
|
||||
/* Set up the board-specific LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
board_led_initialize();
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
|
||||
@ -216,8 +216,9 @@ void up_boot(void)
|
||||
/* Set up the board-specific LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
board_led_initialize();
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
|
||||
@ -592,7 +592,7 @@ __start:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
bl board_led_initialize
|
||||
bl board_autoled_initialize
|
||||
#endif
|
||||
|
||||
/* Then jump to OS entry */
|
||||
|
||||
@ -193,7 +193,7 @@ __start:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
bl board_led_initialize
|
||||
bl board_autoled_initialize
|
||||
#endif
|
||||
|
||||
/* Then jump to OS entry */
|
||||
|
||||
@ -37,11 +37,11 @@
|
||||
* Included Files
|
||||
*****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h> /* NuttX configuration settings */
|
||||
#include <nuttx/config.h> /* NuttX configuration settings */
|
||||
#include <arch/board/board.h> /* Board-specific settings */
|
||||
|
||||
#include "arm.h" /* ARM-specific settings */
|
||||
#include "chip.h" /* Chip-specific settings */
|
||||
#include "arm.h" /* ARM-specific settings */
|
||||
#include "chip.h" /* Chip-specific settings */
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
@ -59,18 +59,18 @@
|
||||
* External references
|
||||
*****************************************************************************/
|
||||
|
||||
.globl str71x_prccuinit /* Clock initialization */
|
||||
.globl up_lowsetup /* Early initialization of UART */
|
||||
.globl str71x_prccuinit /* Clock initialization */
|
||||
.globl up_lowsetup /* Early initialization of UART */
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
.globl up_earlyserialinit /* Early initialization of serial driver */
|
||||
.globl up_earlyserialinit /* Early initialization of serial driver */
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
.globl board_led_initialize /* Boot LED setup */
|
||||
.globl board_autoled_initialize /* Boot LED setup */
|
||||
#endif
|
||||
#ifdef CONFIG_DEBUG
|
||||
.globl up_lowputc /* Low-level debug output */
|
||||
.globl up_lowputc /* Low-level debug output */
|
||||
#endif
|
||||
.globl os_start /* NuttX entry point */
|
||||
.globl os_start /* NuttX entry point */
|
||||
|
||||
/*****************************************************************************
|
||||
* Macros
|
||||
@ -87,8 +87,8 @@
|
||||
|
||||
.macro showprogress, code
|
||||
#ifdef CONFIG_DEBUG
|
||||
mov r0, #\code
|
||||
bl up_lowputc
|
||||
mov r0, #\code
|
||||
bl up_lowputc
|
||||
#endif
|
||||
.endm
|
||||
|
||||
@ -107,32 +107,32 @@
|
||||
/* In order to use the external memory, certain GPIO pins must be
|
||||
* configured in the alternate function:
|
||||
*
|
||||
* GPIO ALT Description
|
||||
* GPIO ALT Description
|
||||
* P2.0-3 CS.0-3 External memory chip select for banks 0,1,3,4
|
||||
* P2.4-7 A.20-23 External memory extended address bus (needed for
|
||||
* address space > 1Mb)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STR71X_BIGEXTMEM
|
||||
# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */
|
||||
# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */
|
||||
#else
|
||||
# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */
|
||||
# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */
|
||||
#endif
|
||||
|
||||
ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode
|
||||
ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET]
|
||||
orr \value, \value, #EXTMEM_GPIO_BITSET
|
||||
str \value, [\base, #STR71X_GPIO_PC0_OFFSET]
|
||||
ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET]
|
||||
orr \value, \value, #EXTMEM_GPIO_BITSET
|
||||
str \value, [\base, #STR71X_GPIO_PC1_OFFSET]
|
||||
ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET]
|
||||
orr \value, \value, #EXTMEM_GPIO_BITSET
|
||||
str \value, [\base, #STR71X_GPIO_PC2_OFFSET]
|
||||
ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode
|
||||
ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET]
|
||||
orr \value, \value, #EXTMEM_GPIO_BITSET
|
||||
str \value, [\base, #STR71X_GPIO_PC0_OFFSET]
|
||||
ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET]
|
||||
orr \value, \value, #EXTMEM_GPIO_BITSET
|
||||
str \value, [\base, #STR71X_GPIO_PC1_OFFSET]
|
||||
ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET]
|
||||
orr \value, \value, #EXTMEM_GPIO_BITSET
|
||||
str \value, [\base, #STR71X_GPIO_PC2_OFFSET]
|
||||
|
||||
/* Enable bank 0 */
|
||||
|
||||
ldr \base, =STR71X_EMI_BASE
|
||||
ldr \base, =STR71X_EMI_BASE
|
||||
|
||||
#ifdef CONFIG_STR71X_BANK0
|
||||
|
||||
@ -156,11 +156,11 @@
|
||||
# define EXTMEM_BANK0_WAITSTATES (CONFIG_STR71X_BANK0_WAITSTATES << 2)
|
||||
# endif
|
||||
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE)
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE)
|
||||
#else
|
||||
mov \value, #0
|
||||
mov \value, #0
|
||||
#endif
|
||||
str \value, [\base, #STR71X_EMI_BCON0_OFFSET]
|
||||
str \value, [\base, #STR71X_EMI_BCON0_OFFSET]
|
||||
|
||||
/* Enable bank 1 */
|
||||
|
||||
@ -186,11 +186,11 @@
|
||||
# define EXTMEM_BANK1_WAITSTATES (CONFIG_STR71X_BANK1_WAITSTATES << 2)
|
||||
# endif
|
||||
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE)
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE)
|
||||
#else
|
||||
mov \value, #0
|
||||
mov \value, #0
|
||||
#endif
|
||||
str \value, [\base, #STR71X_EMI_BCON1_OFFSET]
|
||||
str \value, [\base, #STR71X_EMI_BCON1_OFFSET]
|
||||
|
||||
/* Enable bank 2 */
|
||||
|
||||
@ -216,11 +216,11 @@
|
||||
# define EXTMEM_BANK2_WAITSTATES (CONFIG_STR71X_BANK2_WAITSTATES << 2)
|
||||
# endif
|
||||
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE)
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE)
|
||||
#else
|
||||
mov \value, #0
|
||||
mov \value, #0
|
||||
#endif
|
||||
str \value, [\base, #STR71X_EMI_BCON2_OFFSET]
|
||||
str \value, [\base, #STR71X_EMI_BCON2_OFFSET]
|
||||
|
||||
/* Enable bank 3 */
|
||||
|
||||
@ -246,11 +246,11 @@
|
||||
# define EXTMEM_BANK3_WAITSTATES (CONFIG_STR71X_BANK3_WAITSTATES << 2)
|
||||
# endif
|
||||
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE)
|
||||
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE)
|
||||
#else
|
||||
mov \value, #0
|
||||
mov \value, #0
|
||||
#endif
|
||||
str \value, [\base, #STR71X_EMI_BCON3_OFFSET]
|
||||
str \value, [\base, #STR71X_EMI_BCON3_OFFSET]
|
||||
#endif
|
||||
.endm
|
||||
|
||||
@ -277,42 +277,42 @@
|
||||
.macro eicinit, eicbase, value, irqno, offset
|
||||
/* Disable and clear all interrupts */
|
||||
|
||||
ldr \eicbase, =STR71X_EIC_BASE
|
||||
ldr \eicbase, =STR71X_EIC_BASE
|
||||
|
||||
/* Disable FIQ and IRQ */
|
||||
|
||||
mov \value, #0
|
||||
str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET]
|
||||
mov \value, #0
|
||||
str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET]
|
||||
|
||||
/* Disable all channel interrupts */
|
||||
|
||||
str \value, [\eicbase, #STR71X_EIC_IER_OFFSET]
|
||||
str \value, [\eicbase, #STR71X_EIC_IER_OFFSET]
|
||||
|
||||
/* Clear all pending IRQs */
|
||||
|
||||
ldr \value, =0xffffffff
|
||||
str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET]
|
||||
ldr \value, =0xffffffff
|
||||
str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET]
|
||||
|
||||
/* Disable FIQ channels/clear pending FIQs */
|
||||
|
||||
mov \value, #0x0c
|
||||
str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET]
|
||||
mov \value, #0x0c
|
||||
str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET]
|
||||
|
||||
/* Reset the current priority register */
|
||||
|
||||
mov \value, #0
|
||||
str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET]
|
||||
mov \value, #0
|
||||
str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET]
|
||||
|
||||
/* Zero IVR 31:16 */
|
||||
|
||||
str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
|
||||
str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
|
||||
|
||||
/* Set up the loop to initialize each SIR register. Start
|
||||
* with IRQ number 0 and SIR0
|
||||
*/
|
||||
|
||||
mov \irqno, #0
|
||||
ldr \offset, =STR71X_EIC_SIR_OFFSET
|
||||
mov \irqno, #0
|
||||
ldr \offset, =STR71X_EIC_SIR_OFFSET
|
||||
|
||||
/* Then loop for each EIC channel */
|
||||
eicloop:
|
||||
@ -325,22 +325,22 @@ eicloop:
|
||||
* are all disabled.
|
||||
*/
|
||||
|
||||
mov \value, \irqno, lsl #16
|
||||
str \value, [\eicbase, \offset]
|
||||
mov \value, \irqno, lsl #16
|
||||
str \value, [\eicbase, \offset]
|
||||
|
||||
/* Increment the offset to the next SIR register and inrement
|
||||
* the IRQ number.
|
||||
*/
|
||||
|
||||
add \offset, \offset, #4
|
||||
add \irqno, \irqno, #1
|
||||
add \offset, \offset, #4
|
||||
add \irqno, \irqno, #1
|
||||
|
||||
/* Continue to loop until all of the SIR registers have been
|
||||
* initializeed.
|
||||
*/
|
||||
|
||||
cmp \irqno, #STR71X_EIC_NCHANNELS
|
||||
blt eicloop
|
||||
cmp \irqno, #STR71X_EIC_NCHANNELS
|
||||
blt eicloop
|
||||
.endm
|
||||
|
||||
/*****************************************************************************
|
||||
@ -355,25 +355,26 @@ eicloop:
|
||||
#ifndef CONFIG_STR71X_DISABLE_PERIPHINIT
|
||||
/* Set up APB1 and APB2 addresses */
|
||||
|
||||
ldr \base1, =STR71X_APB1_BASE
|
||||
ldr \base2, =STR71X_APB2_BASE
|
||||
ldr \base1, =STR71X_APB1_BASE
|
||||
ldr \base2, =STR71X_APB2_BASE
|
||||
|
||||
/* Disable all APB1 peripherals */
|
||||
|
||||
ldr \value, =STR71X_APB1_APB1ALL
|
||||
ldr \value, =STR71X_APB1_APB1ALL
|
||||
strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET]
|
||||
|
||||
/* Disable all(or most) APB2 peripherals */
|
||||
ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC)
|
||||
|
||||
ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC)
|
||||
strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET]
|
||||
|
||||
/* Allow EMI and USB */
|
||||
|
||||
ldr \base1, =STR71X_RCCU_BASE
|
||||
ldr \base1, =STR71X_RCCU_BASE
|
||||
#ifdef CONFIG_STR71X_USB
|
||||
ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL)
|
||||
ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL)
|
||||
#else
|
||||
ldr \value, =STR71X_RCCUPER_EMI
|
||||
ldr \value, =STR71X_RCCUPER_EMI
|
||||
#endif
|
||||
strh \value, [\base1, #STR71X_RCCU_PER_OFFSET]
|
||||
#endif
|
||||
@ -391,15 +392,16 @@ eicloop:
|
||||
*****************************************************************************/
|
||||
|
||||
.macro remap, base, value
|
||||
|
||||
/* Read the PCU BOOTCR register */
|
||||
|
||||
ldr \base, =STR71X_PCU_BASE
|
||||
ldr \base, =STR71X_PCU_BASE
|
||||
ldrh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET]
|
||||
|
||||
/* Mask out the old boot mode bits and set the boot mode to FLASH */
|
||||
|
||||
bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK
|
||||
orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH
|
||||
bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK
|
||||
orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH
|
||||
|
||||
/* Save the modified BOOTCR register */
|
||||
|
||||
@ -426,16 +428,16 @@ eicloop:
|
||||
.globl _vector_table
|
||||
.type _vector_table, %function
|
||||
_vector_table:
|
||||
ldr pc, .Lresethandler /* 0x00: Reset */
|
||||
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
|
||||
ldr pc, .Lswihandler /* 0x08: Software interrupt */
|
||||
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
|
||||
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
|
||||
.long 0 /* 0x14: Reserved vector */
|
||||
ldr pc, .Lirqhandler /* 0x18: IRQ */
|
||||
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
|
||||
ldr pc, .Lresethandler /* 0x00: Reset */
|
||||
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
|
||||
ldr pc, .Lswihandler /* 0x08: Software interrupt */
|
||||
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
|
||||
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
|
||||
.long 0 /* 0x14: Reserved vector */
|
||||
ldr pc, .Lirqhandler /* 0x18: IRQ */
|
||||
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
|
||||
|
||||
.globl __start
|
||||
.globl __start
|
||||
.globl up_vectorundefinsn
|
||||
.globl up_vectorswi
|
||||
.globl up_vectorprefetch
|
||||
@ -444,7 +446,7 @@ _vector_table:
|
||||
.globl up_vectorfiq
|
||||
|
||||
.Lresethandler:
|
||||
.long __start
|
||||
.long __start
|
||||
.Lundefinedhandler:
|
||||
.long up_vectorundefinsn
|
||||
.Lswihandler:
|
||||
@ -478,16 +480,16 @@ __start:
|
||||
* the aliased copy
|
||||
*/
|
||||
|
||||
ldr pc, =__flashstart
|
||||
ldr pc, =__flashstart
|
||||
__flashstart:
|
||||
.rept 9
|
||||
nop /* Wait for OSC stabilization*/
|
||||
nop /* Wait for OSC stabilization */
|
||||
.endr
|
||||
|
||||
/* Setup the initial processor mode */
|
||||
|
||||
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
|
||||
msr cpsr, r0
|
||||
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
|
||||
msr cpsr, r0
|
||||
|
||||
/* Initialize the external memory interface (EMI) */
|
||||
|
||||
@ -499,7 +501,7 @@ __flashstart:
|
||||
|
||||
/* Disable all peripherals except EIC */
|
||||
|
||||
periphinit r0, r1, r2
|
||||
periphinit r0, r1, r2
|
||||
|
||||
/* Map memory appropriately for configuration */
|
||||
|
||||
@ -507,42 +509,42 @@ __flashstart:
|
||||
|
||||
/* Setup system stack (and get the BSS range) */
|
||||
|
||||
adr r0, LC0
|
||||
ldmia r0, {r4, r5, sp}
|
||||
adr r0, LC0
|
||||
ldmia r0, {r4, r5, sp}
|
||||
|
||||
/* Clear system BSS section */
|
||||
|
||||
mov r0, #0
|
||||
1: cmp r4, r5
|
||||
mov r0, #0
|
||||
1: cmp r4, r5
|
||||
strcc r0, [r4], #4
|
||||
bcc 1b
|
||||
bcc 1b
|
||||
|
||||
/* Copy system .data sections from FLASH to new home in RAM. */
|
||||
|
||||
adr r3, LC2
|
||||
adr r3, LC2
|
||||
ldmia r3, {r0, r1, r2}
|
||||
|
||||
2: ldmia r0!, {r3 - r10}
|
||||
stmia r1!, {r3 - r10}
|
||||
cmp r1, r2
|
||||
blt 2b
|
||||
cmp r1, r2
|
||||
blt 2b
|
||||
|
||||
/* Initialize clocking */
|
||||
|
||||
bl str71x_prccuinit
|
||||
bl str71x_prccuinit
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon
|
||||
* as possible.
|
||||
*/
|
||||
|
||||
bl up_lowsetup
|
||||
bl up_lowsetup
|
||||
showprogress 'A'
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
mov fp, #0
|
||||
mov fp, #0
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
bl up_earlyserialinit
|
||||
bl up_earlyserialinit
|
||||
#endif
|
||||
|
||||
showprogress 'B'
|
||||
@ -550,17 +552,17 @@ __flashstart:
|
||||
/* Call C++ constructors */
|
||||
|
||||
#ifdef CONFIG_CPLUSPLUS
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
ldr r0, =__ctors_start__
|
||||
ldr r1, =__ctors_end__
|
||||
ctor_loop:
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0], #4
|
||||
stmfd sp!, {r0-r1}
|
||||
mov lr, pc
|
||||
mov pc, r2
|
||||
ldmfd sp!, {r0-r1}
|
||||
b ctor_loop
|
||||
cmp r0, r1
|
||||
beq ctor_end
|
||||
ldr r2, [r0], #4
|
||||
stmfd sp!, {r0-r1}
|
||||
mov lr, pc
|
||||
mov pc, r2
|
||||
ldmfd sp!, {r0-r1}
|
||||
b ctor_loop
|
||||
ctor_end:
|
||||
|
||||
showprogress 'C'
|
||||
@ -570,27 +572,27 @@ ctor_end:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
bl board_led_initialize
|
||||
bl board_autoled_initialize
|
||||
#endif
|
||||
|
||||
/* Then jump to OS entry */
|
||||
|
||||
b os_start
|
||||
b os_start
|
||||
|
||||
/* Call destructors -- never get here */
|
||||
|
||||
#if 0 /* CONFIG_CPLUSPLUS */
|
||||
ldr r0, =__dtors_start__
|
||||
ldr r1, =__dtors_end__
|
||||
ldr r0, =__dtors_start__
|
||||
ldr r1, =__dtors_end__
|
||||
dtor_loop:
|
||||
cmp r0, r1
|
||||
beq dtor_end
|
||||
ldr r2, [r0], #4
|
||||
cmp r0, r1
|
||||
beq dtor_end
|
||||
ldr r2, [r0], #4
|
||||
stmfd sp!, {r0-r1}
|
||||
mov lr, pc
|
||||
mov pc, r2
|
||||
mov lr, pc
|
||||
mov pc, r2
|
||||
ldmfd sp!, {r0-r1}
|
||||
b dtor_loop
|
||||
b dtor_loop
|
||||
dtor_end:
|
||||
#endif
|
||||
|
||||
@ -626,4 +628,3 @@ g_idle_topstack:
|
||||
.size g_idle_topstack, .-g_idle_topstack
|
||||
|
||||
.end
|
||||
|
||||
|
||||
@ -60,8 +60,8 @@
|
||||
.macro showprogress, code
|
||||
#ifdef CONFIG_DEBUG
|
||||
.globl _up_lowputc
|
||||
mov.b r#\code1l /* Character to print */
|
||||
jsr.a _up_lowputc /* Print it */
|
||||
mov.b r#\code1l /* Character to print */
|
||||
jsr.a _up_lowputc /* Print it */
|
||||
#endif
|
||||
.endm
|
||||
|
||||
@ -71,11 +71,11 @@
|
||||
|
||||
/* The near RAM memory map is as follows:
|
||||
*
|
||||
* 0x00400 - DATA Size: Determined by linker
|
||||
* BSS Size: Determined by linker
|
||||
* 0x00400 - DATA Size: Determined by linker
|
||||
* BSS Size: Determined by linker
|
||||
* Interrupt stack Size: CONFIG_ARCH_INTERRUPTSTACK
|
||||
* Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE
|
||||
* Heap Size: Everything remaining
|
||||
* Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE
|
||||
* Heap Size: Everything remaining
|
||||
* 0x00bff - (end+1)
|
||||
*/
|
||||
|
||||
@ -174,48 +174,48 @@ __start:
|
||||
/* Set the interrupt and user stack pointers */
|
||||
|
||||
mov.w #_enbss, R0
|
||||
ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */
|
||||
ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */
|
||||
add.w #CONFIG_IDLETHREAD_STACKSIZE, R0
|
||||
fset U /* Set bit 7 (U) to select the user stack pointer */
|
||||
ldc R0, sp /* Set the user stack pointer */
|
||||
fset U /* Set bit 7 (U) to select the user stack pointer */
|
||||
ldc R0, sp /* Set the user stack pointer */
|
||||
|
||||
/* Set BCLK speed. At reset, the processor clock (BLCK) defaults to a divisor of 8.
|
||||
* This sets clock to F1 (divide by 1) on XIN: BCLK = XIN frequency.
|
||||
*/
|
||||
|
||||
mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */
|
||||
mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1
|
||||
* CM17 & CM16 defaults to 0 after reset and
|
||||
* so we only need to reset CM06 to 0 */
|
||||
mov.b #0x00,M16C_PRCR /* protect CM0 */
|
||||
mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */
|
||||
mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1
|
||||
* CM17 & CM16 defaults to 0 after reset and
|
||||
* so we only need to reset CM06 to 0 */
|
||||
mov.b #0x00,M16C_PRCR /* protect CM0 */
|
||||
|
||||
/* The two MS bits of the interrupt cause select register must be set to
|
||||
* enable the use of INT4 and INT5
|
||||
*/
|
||||
|
||||
mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */
|
||||
ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */
|
||||
mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */
|
||||
ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */
|
||||
|
||||
/* Set up INTB to point to location of variable vector table */
|
||||
|
||||
mov.w _g_svarvect, r0 /* R0 = lower 16-bits */
|
||||
mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */
|
||||
ldc r1, intbh
|
||||
ldc r0, intbl
|
||||
mov.w _g_svarvect, r0 /* R0 = lower 16-bits */
|
||||
mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */
|
||||
ldc r1, intbh
|
||||
ldc r0, intbl
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible. */
|
||||
|
||||
.globl _up_lowsetup /* Early initialization of UART */
|
||||
.globl _up_lowsetup /* Early initialization of UART */
|
||||
jsr.a _up_lowsetup
|
||||
showprogress 'A'
|
||||
|
||||
/* Clear near .bss sections */
|
||||
|
||||
mov.b #0x00, r0l /* r0l: 0 */
|
||||
mov.w _g_snbss, a1 /* a1: start of near .bss */
|
||||
mov.w _g_enbss, r3 /* r3: end of near .bss */
|
||||
sub.w a1, r3 /* r3: size of near .bss */
|
||||
sstr.b /* Clear near .bss */
|
||||
mov.b #0x00, r0l /* r0l: 0 */
|
||||
mov.w _g_snbss, a1 /* a1: start of near .bss */
|
||||
mov.w _g_enbss, r3 /* r3: end of near .bss */
|
||||
sub.w a1, r3 /* r3: size of near .bss */
|
||||
sstr.b /* Clear near .bss */
|
||||
|
||||
/* Clear far .bss sections */
|
||||
|
||||
@ -227,12 +227,12 @@ __start:
|
||||
|
||||
/* Initialize near .data sections (.rodata is not moved) */
|
||||
|
||||
mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */
|
||||
mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */
|
||||
mov.w _g_sndata, a1 /* a1: start of near .data */
|
||||
mov.w _g_endata, r3 /* r3: end of near .data */
|
||||
sub.w a1, r3 /* r3: size of near .data */
|
||||
smovf.b /* Copy source to near .data */
|
||||
mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */
|
||||
mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */
|
||||
mov.w _g_sndata, a1 /* a1: start of near .data */
|
||||
mov.w _g_endata, r3 /* r3: end of near .data */
|
||||
sub.w a1, r3 /* r3: size of near .data */
|
||||
smovf.b /* Copy source to near .data */
|
||||
|
||||
/* Initialize far .data sections (.rodata is not moved) */
|
||||
|
||||
@ -245,8 +245,8 @@ __start:
|
||||
/* Perform early console initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
.globl _up_earlyconsoleinit /* Early initialization of console driver */
|
||||
jsr.a _up_earlyconsoleinit /* Call it */
|
||||
.globl _up_earlyconsoleinit /* Early initialization of console driver */
|
||||
jsr.a _up_earlyconsoleinit /* Call it */
|
||||
showprogress 'D'
|
||||
#endif
|
||||
|
||||
@ -260,8 +260,8 @@ __start:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
.globl _board_led_initialize /* Boot LED setup */
|
||||
jsr.a _board_led_initialize /* Call it */
|
||||
.globl _board_autoled_initialize /* Boot LED setup */
|
||||
jsr.a _board_autoled_initialize /* Call it */
|
||||
#endif
|
||||
showprogress '\n'
|
||||
|
||||
|
||||
@ -60,31 +60,32 @@
|
||||
|
||||
/* Called functions */
|
||||
|
||||
.globl _up_lowsetup /* Early initialization of UART */
|
||||
.globl _up_lowsetup /* Early initialization of UART */
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
.globl _up_earlyconsoleinit /* Early initialization of console driver */
|
||||
.globl _up_earlyconsoleinit /* Early initialization of console driver */
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
.globl _board_led_initialize /* Boot LED setup */
|
||||
.globl _board_autoled_initialize /* Boot LED setup */
|
||||
#endif
|
||||
#ifdef CONFIG_DEBUG
|
||||
.globl _up_lowputc /* Low-level debug output */
|
||||
.globl _up_lowputc /* Low-level debug output */
|
||||
#endif
|
||||
.globl _os_start /* NuttX entry point */
|
||||
.globl _os_start /* NuttX entry point */
|
||||
|
||||
/* Variables set up by the linker script */
|
||||
|
||||
.globl _sbss /* Start of BSS */
|
||||
.globl _ebss /* End of BSS */
|
||||
.globl _svect /* Start of the new vector location */
|
||||
.globl _sbss /* Start of BSS */
|
||||
.globl _ebss /* End of BSS */
|
||||
.globl _svect /* Start of the new vector location */
|
||||
|
||||
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
||||
.globl _eronly /* Where .data defaults are stored in FLASH */
|
||||
.global _sdata /* Start of .data in RAM */
|
||||
.globl _edata /* End of .data in RAM */
|
||||
.globl _eronly /* Where .data defaults are stored in FLASH */
|
||||
.global _sdata /* Start of .data in RAM */
|
||||
.globl _edata /* End of .data in RAM */
|
||||
#endif
|
||||
|
||||
/* Interrupt handlers */
|
||||
|
||||
.globl _up_invalid_handler
|
||||
#ifdef CONFIG_SH1_DMAC0
|
||||
.globl _up_dmac0_handler
|
||||
@ -161,9 +162,9 @@
|
||||
|
||||
.macro showprogress, code
|
||||
#ifdef CONFIG_DEBUG
|
||||
mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */
|
||||
jsr @r0 /* Call it */
|
||||
mov #\code, r4 /* Delay slot */
|
||||
mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */
|
||||
jsr @r0 /* Call it */
|
||||
mov #\code, r4 /* Delay slot */
|
||||
#endif
|
||||
.endm
|
||||
|
||||
@ -191,128 +192,128 @@ __vector_table:
|
||||
* vectors.
|
||||
*/
|
||||
|
||||
.long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */
|
||||
.long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */
|
||||
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
|
||||
.long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */
|
||||
.long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */
|
||||
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
|
||||
|
||||
.rept SH1_NCMN_VECTORS-4
|
||||
.rept SH1_NCMN_VECTORS-4
|
||||
.long _up_invalid_handler
|
||||
.endr
|
||||
|
||||
/* The remaining vectors are unique to the SH-1 703x family */
|
||||
|
||||
#ifdef CONFIG_SH1_DMAC0
|
||||
.long _up_dmac0_handler /* 72: DMAC0 DEI0 */
|
||||
.long _up_dmac0_handler /* 72: DMAC0 DEI0 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 72: DMAC0 DEI0 */
|
||||
.long _up_invalid_handler /* 72: DMAC0 DEI0 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 73: Reserved */
|
||||
.long _up_invalid_handler /* 73: Reserved */
|
||||
#ifdef CONFIG_SH1_DMAC1
|
||||
.long _up_dmac1_handler /* 74: DMAC1 DEI1 */
|
||||
.long _up_dmac1_handler /* 74: DMAC1 DEI1 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 74: DMAC1 DEI1 */
|
||||
.long _up_invalid_handler /* 74: DMAC1 DEI1 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 75: Reserved */
|
||||
.long _up_invalid_handler /* 75: Reserved */
|
||||
#ifdef CONFIG_SH1_DMAC2
|
||||
.long _up_dmac2_handler /* 76: DMAC2 DEI2 */
|
||||
.long _up_dmac2_handler /* 76: DMAC2 DEI2 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 76: DMAC2 DEI2 */
|
||||
.long _up_invalid_handler /* 76: DMAC2 DEI2 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 77: Reserved */
|
||||
.long _up_invalid_handler /* 77: Reserved */
|
||||
#ifdef CONFIG_SH1_DMAC3
|
||||
.long _up_dmac3_handler /* 78: DMAC3 DEI3 */
|
||||
.long _up_dmac3_handler /* 78: DMAC3 DEI3 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 78: DMAC3 DEI3 */
|
||||
.long _up_invalid_handler /* 78: DMAC3 DEI3 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 79: Reserved */
|
||||
.long _up_imia0_handler /* 80: ITU0 IMIA0 */
|
||||
.long _up_imib0_handler /* 81: IMIB0 */
|
||||
.long _up_ovi0_handler /* 82: OVI0 */
|
||||
.long _up_invalid_handler /* 83: Reserved */
|
||||
.long _up_invalid_handler /* 79: Reserved */
|
||||
.long _up_imia0_handler /* 80: ITU0 IMIA0 */
|
||||
.long _up_imib0_handler /* 81: IMIB0 */
|
||||
.long _up_ovi0_handler /* 82: OVI0 */
|
||||
.long _up_invalid_handler /* 83: Reserved */
|
||||
#ifdef CONFIG_SH1_ITU1
|
||||
.long _up_imia1_handler /* 84: ITU1 IMIA1 */
|
||||
.long _up_imib1_handler /* 85: IMIB1 */
|
||||
.long _up_ovi1_handler /* 86: OVI1 */
|
||||
.long _up_imia1_handler /* 84: ITU1 IMIA1 */
|
||||
.long _up_imib1_handler /* 85: IMIB1 */
|
||||
.long _up_ovi1_handler /* 86: OVI1 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 84: ITU1 IMIA1 */
|
||||
.long _up_invalid_handler /* 85: IMIB1 */
|
||||
.long _up_invalid_handler /* 86: OVI1 */
|
||||
.long _up_invalid_handler /* 84: ITU1 IMIA1 */
|
||||
.long _up_invalid_handler /* 85: IMIB1 */
|
||||
.long _up_invalid_handler /* 86: OVI1 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 87: Reserved */
|
||||
.long _up_invalid_handler /* 87: Reserved */
|
||||
#ifdef CONFIG_SH1_ITU2
|
||||
.long _up_imia2_handler /* 88: ITU2 IMIA2 */
|
||||
.long _up_imib2_handler /* 89: IMIB2 */
|
||||
.long _up_ovi2_handler /* 90: OVI2 */
|
||||
.long _up_imia2_handler /* 88: ITU2 IMIA2 */
|
||||
.long _up_imib2_handler /* 89: IMIB2 */
|
||||
.long _up_ovi2_handler /* 90: OVI2 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 88: ITU2 IMIA2 */
|
||||
.long _up_invalid_handler /* 89: IMIB2 */
|
||||
.long _up_invalid_handler /* 90: OVI2 */
|
||||
.long _up_invalid_handler /* 88: ITU2 IMIA2 */
|
||||
.long _up_invalid_handler /* 89: IMIB2 */
|
||||
.long _up_invalid_handler /* 90: OVI2 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 91: Reserved */
|
||||
.long _up_invalid_handler /* 91: Reserved */
|
||||
#ifdef CONFIG_SH1_ITU3
|
||||
.long _up_imia3_handler /* 92: ITU3 IMIA3 */
|
||||
.long _up_imib3_handler /* 93: IMIB3 */
|
||||
.long _up_ovi3_handler /* 94: OVI3 */
|
||||
.long _up_imia3_handler /* 92: ITU3 IMIA3 */
|
||||
.long _up_imib3_handler /* 93: IMIB3 */
|
||||
.long _up_ovi3_handler /* 94: OVI3 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 92: ITU3 IMIA3 */
|
||||
.long _up_invalid_handler /* 93: IMIB3 */
|
||||
.long _up_invalid_handler /* 94: OVI3 */
|
||||
.long _up_invalid_handler /* 92: ITU3 IMIA3 */
|
||||
.long _up_invalid_handler /* 93: IMIB3 */
|
||||
.long _up_invalid_handler /* 94: OVI3 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 95: Reserved */
|
||||
.long _up_invalid_handler /* 95: Reserved */
|
||||
#ifdef CONFIG_SH1_ITU4
|
||||
.long _up_imia4_handler /* 96: ITU4 IMIA4 */
|
||||
.long _up_imib4_handler /* 97: IMIB4 */
|
||||
.long _up_ovi4_handler /* 98: OVI4 */
|
||||
.long _up_imia4_handler /* 96: ITU4 IMIA4 */
|
||||
.long _up_imib4_handler /* 97: IMIB4 */
|
||||
.long _up_ovi4_handler /* 98: OVI4 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 96: ITU4 IMIA4 */
|
||||
.long _up_invalid_handler /* 97: IMIB4 */
|
||||
.long _up_invalid_handler /* 98: OVI4 */
|
||||
.long _up_invalid_handler /* 96: ITU4 IMIA4 */
|
||||
.long _up_invalid_handler /* 97: IMIB4 */
|
||||
.long _up_invalid_handler /* 98: OVI4 */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 99: Reserved */
|
||||
.long _up_invalid_handler /* 99: Reserved */
|
||||
#ifdef CONFIG_SH1_SCI0
|
||||
.long _up_eri0_handler /* 100: SCI0 ERI0 */
|
||||
.long _up_rxi0_handler /* 101: RxI0 */
|
||||
.long _up_txi0_handler /* 102: TxI0 */
|
||||
.long _up_tei0_handler /* 103: TEI0 */
|
||||
.long _up_eri0_handler /* 100: SCI0 ERI0 */
|
||||
.long _up_rxi0_handler /* 101: RxI0 */
|
||||
.long _up_txi0_handler /* 102: TxI0 */
|
||||
.long _up_tei0_handler /* 103: TEI0 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 100: SCI0 ERI0 */
|
||||
.long _up_invalid_handler /* 101: RxI0 */
|
||||
.long _up_invalid_handler /* 102: TxI0 */
|
||||
.long _up_invalid_handler /* 103: TEI0 */
|
||||
.long _up_invalid_handler /* 100: SCI0 ERI0 */
|
||||
.long _up_invalid_handler /* 101: RxI0 */
|
||||
.long _up_invalid_handler /* 102: TxI0 */
|
||||
.long _up_invalid_handler /* 103: TEI0 */
|
||||
#endif
|
||||
#ifdef CONFIG_SH1_SCI1
|
||||
.long _up_eri1_handler /* 104: SCI1 ERI1 */
|
||||
.long _up_rxi1_handler /* 105: RxI1 */
|
||||
.long _up_txi1_handler /* 106: TxI1 */
|
||||
.long _up_tei1_handler /* 107: TEI1 */
|
||||
.long _up_eri1_handler /* 104: SCI1 ERI1 */
|
||||
.long _up_rxi1_handler /* 105: RxI1 */
|
||||
.long _up_txi1_handler /* 106: TxI1 */
|
||||
.long _up_tei1_handler /* 107: TEI1 */
|
||||
#else
|
||||
.long _up_invalid_handler /* 104: SCI1 ERI1 */
|
||||
.long _up_invalid_handler /* 105: RxI1 */
|
||||
.long _up_invalid_handler /* 106: TxI1 */
|
||||
.long _up_invalid_handler /* 107: TEI1 */
|
||||
.long _up_invalid_handler /* 104: SCI1 ERI1 */
|
||||
.long _up_invalid_handler /* 105: RxI1 */
|
||||
.long _up_invalid_handler /* 106: TxI1 */
|
||||
.long _up_invalid_handler /* 107: TEI1 */
|
||||
#endif
|
||||
#ifdef CONFIG_SH1_PCU
|
||||
.long _up_pei_handler /* 108: Parity control unit PEI */
|
||||
.long _up_pei_handler /* 108: Parity control unit PEI */
|
||||
#else
|
||||
.long _up_invalid_handler /* 108: Parity control unit PEI */
|
||||
.long _up_invalid_handler /* 108: Parity control unit PEI */
|
||||
#endif
|
||||
#ifdef CONFIG_SH1_AD
|
||||
.long _up_aditi_handler /* 109: A/D ITI */
|
||||
.long _up_aditi_handler /* 109: A/D ITI */
|
||||
#else
|
||||
.long _up_invalid_handler /* 109: A/D ITI */
|
||||
.long _up_invalid_handler /* 109: A/D ITI */
|
||||
#endif
|
||||
.long _up_invalid_handler /* 110: Reserved */
|
||||
.long _up_invalid_handler /* 111: Reserved */
|
||||
.long _up_invalid_handler /* 110: Reserved */
|
||||
.long _up_invalid_handler /* 111: Reserved */
|
||||
#ifdef CONFIG_SH1_WDT
|
||||
.long _up_wdt_handler /* 112: WDT ITI */
|
||||
.long _up_wdt_handler /* 112: WDT ITI */
|
||||
#else
|
||||
.long _up_invalid_handler /* 112: WDT ITI */
|
||||
.long _up_invalid_handler /* 112: WDT ITI */
|
||||
#endif
|
||||
#ifdef CONFIG_SH1_CMI
|
||||
.long _up_cmi_handler /* 113: REF CMI */
|
||||
.long _up_cmi_handler /* 113: REF CMI */
|
||||
#else
|
||||
.long _up_invalid_handler /* 113: REF CMI */
|
||||
.long _up_invalid_handler /* 113: REF CMI */
|
||||
#endif
|
||||
.rept (SH1_LAST_VNDX-SH1_CMI_VNDX) /* 114-255: Reserved */
|
||||
.long _up_invalid_handler
|
||||
@ -346,15 +347,15 @@ __start:
|
||||
/* set up the bus controller for the EVB */
|
||||
|
||||
mov.l .Lwcr1, r0
|
||||
sub r1,r1
|
||||
sub r1,r1
|
||||
mov.w r1, @r0
|
||||
|
||||
/* Configure the BSR to use /LBS, /HBS, /WR */
|
||||
|
||||
mov.l .Lbcr, r0
|
||||
mov.w .Lbas, r1
|
||||
bra __start0
|
||||
mov.w r1, @r0
|
||||
mov.l .Lbcr, r0
|
||||
mov.w .Lbas, r1
|
||||
bra __start0
|
||||
mov.w r1, @r0
|
||||
|
||||
.align 2
|
||||
.Lstack:
|
||||
@ -369,67 +370,67 @@ __start:
|
||||
__start0:
|
||||
/* Copy the monitor vectors to a002000-a00211f */
|
||||
|
||||
mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */
|
||||
mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */
|
||||
mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */
|
||||
mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */
|
||||
mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */
|
||||
mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */
|
||||
1:
|
||||
mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */
|
||||
mov.l r2, @r1 /* Write into SRAM vector table */
|
||||
add #4, r0 /* R0: Address of next vector to read from monitor vector table */
|
||||
add #4, r1 /* R1: Address of next vector to write to SRAM vector table */
|
||||
cmp/gt r0, r3 /* Copy only only up to external interrupts at */
|
||||
bt 1b /* Continue looping until all copied */
|
||||
nop /* Delay slot */
|
||||
mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */
|
||||
mov.l r2, @r1 /* Write into SRAM vector table */
|
||||
add #4, r0 /* R0: Address of next vector to read from monitor vector table */
|
||||
add #4, r1 /* R1: Address of next vector to write to SRAM vector table */
|
||||
cmp/gt r0, r3 /* Copy only only up to external interrupts at */
|
||||
bt 1b /* Continue looping until all copied */
|
||||
nop /* Delay slot */
|
||||
|
||||
/* Update the VBR to show new adddress of vector table */
|
||||
|
||||
mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */
|
||||
ldc r0, vbr /* Set VBR to start of SRAM vector table */
|
||||
mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */
|
||||
ldc r0, vbr /* Set VBR to start of SRAM vector table */
|
||||
|
||||
/* Initialize data segement */
|
||||
|
||||
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
||||
mov.l .Lsdata, r0 /* R0: Start of .data segment */
|
||||
mov.l .Ledata, r1 /* R1: End+1 of .data segment */
|
||||
mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */
|
||||
mov.l .Lsdata, r0 /* R0: Start of .data segment */
|
||||
mov.l .Ledata, r1 /* R1: End+1 of .data segment */
|
||||
mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */
|
||||
2:
|
||||
mov.l @r2, r3 /* R3: Next byte from FLASH copy */
|
||||
mov.l r3, @r0 /* Copy to .data */
|
||||
add #4, r2 /* R2: Address of next byte to read from FLASH */
|
||||
add #4, r0 /* R0: Address to write next byte to .data */
|
||||
cmp/gt r0, r1 /* End of .data? */
|
||||
bt 2b /* Loop until end of data */
|
||||
nop /* Delay slot */
|
||||
mov.l @r2, r3 /* R3: Next byte from FLASH copy */
|
||||
mov.l r3, @r0 /* Copy to .data */
|
||||
add #4, r2 /* R2: Address of next byte to read from FLASH */
|
||||
add #4, r0 /* R0: Address to write next byte to .data */
|
||||
cmp/gt r0, r1 /* End of .data? */
|
||||
bt 2b /* Loop until end of data */
|
||||
nop /* Delay slot */
|
||||
#endif
|
||||
|
||||
/* Clear BSS */
|
||||
|
||||
mov.l .Lsbss, r0 /* R0: Start of BSS segment */
|
||||
mov.l .Lebss, r1 /* R1: End+1 of BSS segment */
|
||||
mov #0, r2 /* R2: Value = 0 */
|
||||
mov.l .Lsbss, r0 /* R0: Start of BSS segment */
|
||||
mov.l .Lebss, r1 /* R1: End+1 of BSS segment */
|
||||
mov #0, r2 /* R2: Value = 0 */
|
||||
3:
|
||||
mov.l r2, @r0 /* Clear the next word in BSS */
|
||||
add #4, r0 /* R0: Address of next byte to clear in BSS */
|
||||
cmp/ge r0, r1 /* End of BSS? */
|
||||
bt 3b /* Loop until the end of BSS */
|
||||
nop /* Delay slot */
|
||||
mov.l r2, @r0 /* Clear the next word in BSS */
|
||||
add #4, r0 /* R0: Address of next byte to clear in BSS */
|
||||
cmp/ge r0, r1 /* End of BSS? */
|
||||
bt 3b /* Loop until the end of BSS */
|
||||
nop /* Delay slot */
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon
|
||||
* as possible.
|
||||
*/
|
||||
|
||||
mov.l .Llowsetup, r0 /* Address of up_lowsetup */
|
||||
jsr @r0 /* Call it */
|
||||
or r0, r0 /* Delay slot */
|
||||
mov.l .Llowsetup, r0 /* Address of up_lowsetup */
|
||||
jsr @r0 /* Call it */
|
||||
or r0, r0 /* Delay slot */
|
||||
|
||||
showprogress 'A'
|
||||
|
||||
/* Perform early console initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */
|
||||
jsr @r0 /* Call it */
|
||||
or r0, r0 /* Delay slot */
|
||||
mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */
|
||||
jsr @r0 /* Call it */
|
||||
or r0, r0 /* Delay slot */
|
||||
#endif
|
||||
|
||||
showprogress 'B'
|
||||
@ -445,16 +446,16 @@ __start0:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
mov.l .Lledinit, r0 /* Address of board_led_initialize */
|
||||
jsr @r0 /* Call it */
|
||||
or r0, r0 /* Delay slot */
|
||||
mov.l .Lledinit, r0 /* Address of board_autoled_initialize */
|
||||
jsr @r0 /* Call it */
|
||||
or r0, r0 /* Delay slot */
|
||||
#endif
|
||||
|
||||
/* Then jump to NuttX entry */
|
||||
|
||||
mov.l .Losstart,r0
|
||||
jsr @r0
|
||||
or r0, r0
|
||||
mov.l .Losstart,r0
|
||||
jsr @r0
|
||||
or r0, r0
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
@ -471,16 +472,16 @@ __start0:
|
||||
.align 2
|
||||
#ifdef CONFIG_BOOT_RUNFROMFLASH
|
||||
.Leronly:
|
||||
.long _eronly
|
||||
.long _eronly
|
||||
.Lsdata:
|
||||
.long _sdata
|
||||
.long _sdata
|
||||
.Ledata:
|
||||
.long _edata
|
||||
.long _edata
|
||||
#endif
|
||||
.Lsbss:
|
||||
.long _sbss
|
||||
.long _sbss
|
||||
.Lebss:
|
||||
.long _ebss
|
||||
.long _ebss
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
.Learlyconsole:
|
||||
.long _up_earlyconsoleinit
|
||||
@ -492,13 +493,13 @@ __start0:
|
||||
.long _up_lowputc
|
||||
#endif
|
||||
.Lledinit:
|
||||
.long _board_led_initialize
|
||||
.long _board_autoled_initialize
|
||||
.Losstart:
|
||||
.long _os_start
|
||||
.long _os_start
|
||||
.Lsvect:
|
||||
.long _svect
|
||||
.long _svect
|
||||
.Lvectend:
|
||||
.long ((4*SH1_NCMN_VECTORS)-1)
|
||||
.long ((4*SH1_NCMN_VECTORS)-1)
|
||||
.size __start, .-__start
|
||||
|
||||
/*****************************************************************************
|
||||
@ -521,4 +522,3 @@ _g_idle_topstack:
|
||||
.size _g_idle_topstack, .-_g_idle_topstack
|
||||
|
||||
.end
|
||||
|
||||
|
||||
@ -54,7 +54,7 @@
|
||||
xref _z16f_clkinit:EROM
|
||||
xref _z16f_lowinit:EROM
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
xref _board_led_initialize:EROM
|
||||
xref _board_autoled_initialize:EROM
|
||||
#endif
|
||||
#if defined(USE_LOWUARTINIT)
|
||||
xref _z16f_lowuartinit:EROM
|
||||
@ -158,7 +158,7 @@ _z16f_reset:
|
||||
/* Initialize onboard LEDs */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
call _board_led_initialize
|
||||
call _board_autoled_initialize
|
||||
#endif
|
||||
/* Perform VERY early UART initialization so that we can use it here */
|
||||
|
||||
|
||||
@ -68,7 +68,7 @@
|
||||
xref _z16f_clkinit:ROM
|
||||
xref _z16f_lowinit:ROM
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
xref _board_led_initialize:ROM
|
||||
xref _board_autoled_initialize:ROM
|
||||
#endif
|
||||
xref _os_start:ROM
|
||||
xref _up_doirq:ROM
|
||||
|
||||
Loading…
Reference in New Issue
Block a user