Xtensa: Trivial interrupt-related changes
This commit is contained in:
Gregory Nutt
parent
30c4a41332
commit
9e1600b7d3
@ -32,8 +32,8 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* Note: Macros of the form XTENSA_HAVE_*** have a value of 1 if the option
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* is configured, and a value of 0 otherwise (or undefined if 0 is a valid
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* numeric option. These macros are always defined.
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* is configured, and a value of 0 otherwise. These macros are always
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* defined.
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*/
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/* ISA **********************************************************************/
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@ -445,7 +445,7 @@
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#define XTENSA_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
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#define XTENSA_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
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#define XTENSA_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
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#undef XTENSA_TIMER3_INTERRUPT
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#define XTENSA_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
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#define XTENSA_NMI_INTERRUPT 14 /* non-maskable interrupt */
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#define XTENSA_PROFILING_INTERRUPT 11 /* profiling interrupt */
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@ -49,6 +49,7 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Exceptions
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*
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* IRAM Offset Description
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@ -97,87 +98,90 @@
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/* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */
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#define XTENSA_IRQ_MAC 0 /* 1. *_INTR_STATUS_REG_0, bit 0 */
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#define XTENSA_IRQ_MAC_NMI 1 /* 2. *_INTR_STATUS_REG_0, bit 1 */
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#define XTENSA_IRQ_BB 2 /* 3. *_INTR_STATUS_REG_0, bit 2 */
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#define XTENSA_IRQ_BB_MAC 3 /* 4. *_INTR_STATUS_REG_0, bit 3 */
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#define XTENSA_IRQ_BT_BB 4 /* 5. *_INTR_STATUS_REG_0, bit 4 */
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#define XTENSA_IRQ_BT_BB_NMI 5 /* 6. *_INTR_STATUS_REG_0, bit 5 */
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#define XTENSA_IRQ_RWBT_IRQ 6 /* 7. *_INTR_STATUS_REG_0, bit 6 */
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#define XTENSA_IRQ_RWBLE_IRQ 7 /* 8. *_INTR_STATUS_REG_0, bit 7 */
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#define XTENSA_IRQ_RWBT_NMI 8 /* 9. *_INTR_STATUS_REG_0, bit 8 */
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#define XTENSA_IRQ_RWBLE_NMI 9 /* 10. *_INTR_STATUS_REG_0, bit 9 */
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#define XTENSA_IRQ_SREG0 0
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#define XTENSA_IRQ_MAC 0 /* INTR_STATUS_REG_0, bit 0 */
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#define XTENSA_IRQ_MAC_NMI 1 /* INTR_STATUS_REG_0, bit 1 */
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#define XTENSA_IRQ_BB 2 /* INTR_STATUS_REG_0, bit 2 */
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#define XTENSA_IRQ_BB_MAC 3 /* INTR_STATUS_REG_0, bit 3 */
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#define XTENSA_IRQ_BT_BB 4 /* INTR_STATUS_REG_0, bit 4 */
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#define XTENSA_IRQ_BT_BB_NMI 5 /* INTR_STATUS_REG_0, bit 5 */
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#define XTENSA_IRQ_RWBT_IRQ 6 /* INTR_STATUS_REG_0, bit 6 */
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#define XTENSA_IRQ_RWBLE_IRQ 7 /* INTR_STATUS_REG_0, bit 7 */
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#define XTENSA_IRQ_RWBT_NMI 8 /* INTR_STATUS_REG_0, bit 8 */
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#define XTENSA_IRQ_RWBLE_NMI 9 /* INTR_STATUS_REG_0, bit 9 */
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#define XTENSA_IRQ_SLC0 10 /* 11. *_INTR_STATUS_REG_0, bit 10 */
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#define XTENSA_IRQ_SLC1 11 /* 12. *_INTR_STATUS_REG_0, bit 11 */
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#define XTENSA_IRQ_UHCI0 12 /* 13. *_INTR_STATUS_REG_0, bit 12 */
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#define XTENSA_IRQ_UHCI1 13 /* 14. *_INTR_STATUS_REG_0, bit 13 */
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#define XTENSA_IRQ_TG_T0_LEVEL 14 /* 15. *_INTR_STATUS_REG_0, bit 14 */
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#define XTENSA_IRQ_TG_T1_LEVEL 15 /* 16. *_INTR_STATUS_REG_0, bit 15 */
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#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* 17. *_INTR_STATUS_REG_0, bit 16 */
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#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* 18. *_INTR_STATUS_REG_0, bit 17 */
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#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* 19. *_INTR_STATUS_REG_0, bit 18 */
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#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* 20. *_INTR_STATUS_REG_0, bit 19 */
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#define XTENSA_IRQ_SLC0 10 /* INTR_STATUS_REG_0, bit 10 */
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#define XTENSA_IRQ_SLC1 11 /* INTR_STATUS_REG_0, bit 11 */
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#define XTENSA_IRQ_UHCI0 12 /* INTR_STATUS_REG_0, bit 12 */
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#define XTENSA_IRQ_UHCI1 13 /* INTR_STATUS_REG_0, bit 13 */
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#define XTENSA_IRQ_TG_T0_LEVEL 14 /* INTR_STATUS_REG_0, bit 14 */
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#define XTENSA_IRQ_TG_T1_LEVEL 15 /* INTR_STATUS_REG_0, bit 15 */
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#define XTENSA_IRQ_TG_WDT_LEVEL 16 /* INTR_STATUS_REG_0, bit 16 */
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#define XTENSA_IRQ_TG_LACT_LEVEL 17 /* INTR_STATUS_REG_0, bit 17 */
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#define XTENSA_IRQ_TG1_T0_LEVEL 18 /* INTR_STATUS_REG_0, bit 18 */
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#define XTENSA_IRQ_TG1_T1_LEVEL 19 /* INTR_STATUS_REG_0, bit 19 */
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#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* 21. *_INTR_STATUS_REG_0, bit 20 */
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#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* 22. *_INTR_STATUS_REG_0, bit 21 */
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#define XTENSA_IRQ_CPU_GPIO 22 /* 23. *_INTR_STATUS_REG_0, bit 22 */
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#define XTENSA_IRQ_CPU_NMI 23 /* 24. *_INTR_STATUS_REG_0, bit 23 */
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#define XTENSA_IRQ_CPU_CPU0 24 /* 25. *_INTR_STATUS_REG_0, bit 24 */
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#define XTENSA_IRQ_CPU_CPU1 25 /* 26. *_INTR_STATUS_REG_0, bit 25 */
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#define XTENSA_IRQ_CPU_CPU2 26 /* 27. *_INTR_STATUS_REG_0, bit 26 */
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#define XTENSA_IRQ_CPU_CPU3 27 /* 28. *_INTR_STATUS_REG_0, bit 27 */
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#define XTENSA_IRQ_SPI0 28 /* 29. *_INTR_STATUS_REG_0, bit 28 */
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#define XTENSA_IRQ_SPI1 29 /* 30. *_INTR_STATUS_REG_0, bit 29 */
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#define XTENSA_IRQ_TG1_WDT_LEVEL 20 /* INTR_STATUS_REG_0, bit 20 */
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#define XTENSA_IRQ_G1_LACT_LEVEL 21 /* INTR_STATUS_REG_0, bit 21 */
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#define XTENSA_IRQ_CPU_GPIO 22 /* INTR_STATUS_REG_0, bit 22 */
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#define XTENSA_IRQ_CPU_NMI 23 /* INTR_STATUS_REG_0, bit 23 */
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#define XTENSA_IRQ_CPU_CPU0 24 /* INTR_STATUS_REG_0, bit 24 */
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#define XTENSA_IRQ_CPU_CPU1 25 /* INTR_STATUS_REG_0, bit 25 */
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#define XTENSA_IRQ_CPU_CPU2 26 /* INTR_STATUS_REG_0, bit 26 */
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#define XTENSA_IRQ_CPU_CPU3 27 /* INTR_STATUS_REG_0, bit 27 */
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#define XTENSA_IRQ_SPI0 28 /* INTR_STATUS_REG_0, bit 28 */
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#define XTENSA_IRQ_SPI1 29 /* INTR_STATUS_REG_0, bit 29 */
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#define XTENSA_IRQ_SPI2 30 /* 31. *_INTR_STATUS_REG_0, bit 30 */
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#define XTENSA_IRQ_SPI3 31 /* 32. *_INTR_STATUS_REG_0, bit 31 */
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#define XTENSA_IRQ_SPI2 30 /* INTR_STATUS_REG_0, bit 30 */
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#define XTENSA_IRQ_SPI3 31 /* INTR_STATUS_REG_0, bit 31 */
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/* PRO_INTR_STATUS_REG_1 / APP_INTR_STATUS_REG_1 */
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#define XTENSA_IRQ_I2S0 32 /* 33. *_INTR_STATUS_REG_1, bit 0 */
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#define XTENSA_IRQ_I2S1 33 /* 34. *_INTR_STATUS_REG_1, bit 1 */
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#define XTENSA_IRQ_UART 34 /* 35. *_INTR_STATUS_REG_1, bit 2 */
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#define XTENSA_IRQ_UART1 35 /* 36. *_INTR_STATUS_REG_1, bit 3 */
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#define XTENSA_IRQ_UART2 36 /* 37. *_INTR_STATUS_REG_1, bit 4 */
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#define XTENSA_IRQ_SDIO_HOST 37 /* 38. *_INTR_STATUS_REG_1, bit 5 */
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#define XTENSA_IRQ_EMAC 38 /* 39. *_INTR_STATUS_REG_1, bit 6 */
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#define XTENSA_IRQ_PWM0 39 /* 40. *_INTR_STATUS_REG_1, bit 7 */
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#define XTENSA_IRQ_PWM1 40 /* 41. *_INTR_STATUS_REG_1, bit 8 */
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#define XTENSA_IRQ_PWM2 41 /* 42. *_INTR_STATUS_REG_1, bit 9 */
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#define XTENSA_IRQ_SREG1 32
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#define XTENSA_IRQ_I2S0 32 /* INTR_STATUS_REG_1, bit 0 */
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#define XTENSA_IRQ_I2S1 33 /* INTR_STATUS_REG_1, bit 1 */
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#define XTENSA_IRQ_UART 34 /* INTR_STATUS_REG_1, bit 2 */
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#define XTENSA_IRQ_UART1 35 /* INTR_STATUS_REG_1, bit 3 */
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#define XTENSA_IRQ_UART2 36 /* INTR_STATUS_REG_1, bit 4 */
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#define XTENSA_IRQ_SDIO_HOST 37 /* INTR_STATUS_REG_1, bit 5 */
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#define XTENSA_IRQ_EMAC 38 /* INTR_STATUS_REG_1, bit 6 */
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#define XTENSA_IRQ_PWM0 39 /* INTR_STATUS_REG_1, bit 7 */
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#define XTENSA_IRQ_PWM1 40 /* INTR_STATUS_REG_1, bit 8 */
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#define XTENSA_IRQ_PWM2 41 /* INTR_STATUS_REG_1, bit 9 */
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#define XTENSA_IRQ_PWM3 42 /* 43. *_INTR_STATUS_REG_1, bit 10 */
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#define XTENSA_IRQ_LEDC 43 /* 44. *_INTR_STATUS_REG_1, bit 11 */
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#define XTENSA_IRQ_EFUSE 44 /* 45. *_INTR_STATUS_REG_1, bit 12 */
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#define XTENSA_IRQ_CAN 45 /* 46. *_INTR_STATUS_REG_1, bit 13 */
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#define XTENSA_IRQ_RTC_CORE 46 /* 47. *_INTR_STATUS_REG_1, bit 14 */
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#define XTENSA_IRQ_RMT 47 /* 48. *_INTR_STATUS_REG_1, bit 15 */
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#define XTENSA_IRQ_PCNT 48 /* 49. *_INTR_STATUS_REG_1, bit 16 */
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#define XTENSA_IRQ_I2C_EXT0 49 /* 50. *_INTR_STATUS_REG_1, bit 17 */
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#define XTENSA_IRQ_I2C_EXT1 50 /* 51. *_INTR_STATUS_REG_1, bit 18 */
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#define XTENSA_IRQ_RSA 51 /* 52. *_INTR_STATUS_REG_1, bit 19 */
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#define XTENSA_IRQ_PWM3 42 /* INTR_STATUS_REG_1, bit 10 */
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#define XTENSA_IRQ_LEDC 43 /* INTR_STATUS_REG_1, bit 11 */
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#define XTENSA_IRQ_EFUSE 44 /* INTR_STATUS_REG_1, bit 12 */
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#define XTENSA_IRQ_CAN 45 /* INTR_STATUS_REG_1, bit 13 */
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#define XTENSA_IRQ_RTC_CORE 46 /* INTR_STATUS_REG_1, bit 14 */
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#define XTENSA_IRQ_RMT 47 /* INTR_STATUS_REG_1, bit 15 */
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#define XTENSA_IRQ_PCNT 48 /* INTR_STATUS_REG_1, bit 16 */
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#define XTENSA_IRQ_I2C_EXT0 49 /* INTR_STATUS_REG_1, bit 17 */
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#define XTENSA_IRQ_I2C_EXT1 50 /* INTR_STATUS_REG_1, bit 18 */
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#define XTENSA_IRQ_RSA 51 /* INTR_STATUS_REG_1, bit 19 */
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#define XTENSA_IRQ_SPI1_DMA 52 /* 53. *_INTR_STATUS_REG_1, bit 20 */
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#define XTENSA_IRQ_SPI2_DMA 53 /* 54. *_INTR_STATUS_REG_1, bit 21 */
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#define XTENSA_IRQ_SPI3_DMA 54 /* 55. *_INTR_STATUS_REG_1, bit 22 */
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#define XTENSA_IRQ_WDG 55 /* 56. *_INTR_STATUS_REG_1, bit 23 */
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#define XTENSA_IRQ_TIMER1 56 /* 57. *_INTR_STATUS_REG_1, bit 24 */
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#define XTENSA_IRQ_TIMER2 57 /* 58. *_INTR_STATUS_REG_1, bit 25 */
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#define XTENSA_IRQ_TG_T0_EDGE 58 /* 59. *_INTR_STATUS_REG_1, bit 26 */
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#define XTENSA_IRQ_TG_T1_EDGE 59 /* 60. *_INTR_STATUS_REG_1, bit 27 */
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#define XTENSA_IRQ_TG_WDT_EDGE 60 /* 61. *_INTR_STATUS_REG_1, bit 28 */
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#define XTENSA_IRQ_TG_LACT_EDGE 61 /* 62. *_INTR_STATUS_REG_1, bit 29 */
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#define XTENSA_IRQ_SPI1_DMA 52 /* INTR_STATUS_REG_1, bit 20 */
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#define XTENSA_IRQ_SPI2_DMA 53 /* INTR_STATUS_REG_1, bit 21 */
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#define XTENSA_IRQ_SPI3_DMA 54 /* INTR_STATUS_REG_1, bit 22 */
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#define XTENSA_IRQ_WDG 55 /* INTR_STATUS_REG_1, bit 23 */
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#define XTENSA_IRQ_TIMER1 56 /* INTR_STATUS_REG_1, bit 24 */
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#define XTENSA_IRQ_TIMER2 57 /* INTR_STATUS_REG_1, bit 25 */
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#define XTENSA_IRQ_TG_T0_EDGE 58 /* INTR_STATUS_REG_1, bit 26 */
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#define XTENSA_IRQ_TG_T1_EDGE 59 /* INTR_STATUS_REG_1, bit 27 */
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#define XTENSA_IRQ_TG_WDT_EDGE 60 /* INTR_STATUS_REG_1, bit 28 */
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#define XTENSA_IRQ_TG_LACT_EDGE 61 /* INTR_STATUS_REG_1, bit 29 */
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#define XTENSA_IRQ_TG1_T0_EDGE 62 /* 63. *_INTR_STATUS_REG_1, bit 30 */
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#define XTENSA_IRQ_TG1_T1_EDGE 63 /* 64. *_INTR_STATUS_REG_1, bit 31 */
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#define XTENSA_IRQ_TG1_T0_EDGE 62 /* INTR_STATUS_REG_1, bit 30 */
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#define XTENSA_IRQ_TG1_T1_EDGE 63 /* INTR_STATUS_REG_1, bit 31 */
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/* PRO_INTR_STATUS_REG_2 / APP_INTR_STATUS_REG_2 */
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#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* 65. *_INTR_STATUS_REG_2, bit 0 */
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#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* 66. *_INTR_STATUS_REG_2, bit 1 */
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#define XTENSA_IRQ_MMU_IA 66 /* 67. *_INTR_STATUS_REG_2, bit 2 */
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#define XTENSA_IRQ_MPU_IA 67 /* 68. *_INTR_STATUS_REG_2, bit 3 */
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#define XTENSA_IRQ_CACHE_IA 68 /* 69. *_INTR_STATUS_REG_2, bit 4 */
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#define XTENSA_IRQ_SREG0 64
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#define XTENSA_IRQ_TG1_WDT_EDGE 64 /* INTR_STATUS_REG_2, bit 0 */
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#define XTENSA_IRQ_TG1_LACT_EDGE 65 /* INTR_STATUS_REG_2, bit 1 */
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#define XTENSA_IRQ_MMU_IA 66 /* INTR_STATUS_REG_2, bit 2 */
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#define XTENSA_IRQ_MPU_IA 67 /* INTR_STATUS_REG_2, bit 3 */
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#define XTENSA_IRQ_CACHE_IA 68 /* INTR_STATUS_REG_2, bit 4 */
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/* Total number of interrupts */
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