arch/srm/src/stm32f7: Remove confusing, redundant, and misleading STM32_BKP_BASE definitions.
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@ -112,7 +112,6 @@
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#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
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#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
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#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
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#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
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#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
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#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
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#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
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@ -113,7 +113,6 @@
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#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
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#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
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#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
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#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
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#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
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#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
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#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff: SPI2 / I2S2 */
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@ -113,7 +113,6 @@
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#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff: TIM14 */
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#define STM32_LPTIM1_BASE 0x40002400 /* 0x40002400-0x400027ff: LPTIM1 */
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#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
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#define STM32_BKP_BASE 0x40002800 /* 0x40002800-0x40002bff: RTC & BKP Registers */
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#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff: WWDG */
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#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff: IWDG */
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#define STM32_CAN3_BASE 0x40003400 /* 0x40003400-0x400037ff: CAN3 */
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