From 9ea290b8be059044c440597d049955fd5e3103c9 Mon Sep 17 00:00:00 2001
From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3>
Date: Sat, 26 Sep 2009 21:21:59 +0000
Subject: [PATCH] IRQ numbering fixes

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2100 42af7a65-404d-4744-a932-0658087f49c3
---
 arch/arm/include/stm32/irq.h   | 38 +++++++++++++++++-----------------
 arch/arm/src/stm32/stm32_irq.c | 11 +++++++---
 2 files changed, 27 insertions(+), 22 deletions(-)

diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h
index 6cfb6b6502..19815c5524 100644
--- a/arch/arm/include/stm32/irq.h
+++ b/arch/arm/include/stm32/irq.h
@@ -120,25 +120,25 @@
 #  define STM32_IRQ_RTCALR      (57) /* 41: RTC alarm through EXTI line interrupt */
 #  define STM32_IRQ_OTGFSWKUP   (58) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
                                      /* 43-49: Reserved */
-#  define STM32_IRQ_TIM5        (59) /* 50: TIM5 global interrupt */
-#  define STM32_IRQ_SPI3        (60) /* 51: SPI3 global interrupt */
-#  define STM32_IRQ_UART4       (71) /* 52: UART4 global interrupt */
-#  define STM32_IRQ_UART5       (72) /* 53: UART5 global interrupt */
-#  define STM32_IRQ_TIM6        (73) /* 54: TIM6 global interrupt */
-#  define STM32_IRQ_TIM7        (74) /* 55: TIM7 global interrupt */
-#  define STM32_IRQ_DMA2CH1     (75) /* 56: DMA2 Channel 1 global interrupt */
-#  define STM32_IRQ_DMA2CH2     (76) /* 57: DMA2 Channel 2 global interrupt */
-#  define STM32_IRQ_DMA2CH3     (77) /* 58: DMA2 Channel 3 global interrupt */
-#  define STM32_IRQ_DMA2CH4     (78) /* 59: DMA2 Channel 4 global interrupt */
-#  define STM32_IRQ_DMA2CH5     (79) /* 60: DMA2 Channel 5 global interrupt */
-#  define STM32_IRQ_ETH         (80) /* 61: Ethernet global interrupt */
-#  define STM32_IRQ_ETHWKUP     (81) /* 62: Ethernet Wakeup through EXTI line interrupt */
-#  define STM32_IRQ_CAN2TX      (82) /* 63: CAN2 TX interrupts */
-#  define STM32_IRQ_CAN2RX0     (83) /* 64: CAN2 RX0 interrupts */
-#  define STM32_IRQ_CAN2RX1     (84) /* 65: CAN2 RX1 interrupt */
-#  define STM32_IRQ_CAN2SCE     (85) /* 66: CAN2 SCE interrupt */
-#  define STM32_IRQ_OTGFS       (86) /* 67: USB On The Go FS global interrupt */
-#  define NR_IRQS               (87)
+#  define STM32_IRQ_TIM5        (66) /* 50: TIM5 global interrupt */
+#  define STM32_IRQ_SPI3        (67) /* 51: SPI3 global interrupt */
+#  define STM32_IRQ_UART4       (68) /* 52: UART4 global interrupt */
+#  define STM32_IRQ_UART5       (69) /* 53: UART5 global interrupt */
+#  define STM32_IRQ_TIM6        (70) /* 54: TIM6 global interrupt */
+#  define STM32_IRQ_TIM7        (71) /* 55: TIM7 global interrupt */
+#  define STM32_IRQ_DMA2CH1     (72) /* 56: DMA2 Channel 1 global interrupt */
+#  define STM32_IRQ_DMA2CH2     (73) /* 57: DMA2 Channel 2 global interrupt */
+#  define STM32_IRQ_DMA2CH3     (74) /* 58: DMA2 Channel 3 global interrupt */
+#  define STM32_IRQ_DMA2CH4     (75) /* 59: DMA2 Channel 4 global interrupt */
+#  define STM32_IRQ_DMA2CH5     (76) /* 60: DMA2 Channel 5 global interrupt */
+#  define STM32_IRQ_ETH         (77) /* 61: Ethernet global interrupt */
+#  define STM32_IRQ_ETHWKUP     (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
+#  define STM32_IRQ_CAN2TX      (79) /* 63: CAN2 TX interrupts */
+#  define STM32_IRQ_CAN2RX0     (70) /* 64: CAN2 RX0 interrupts */
+#  define STM32_IRQ_CAN2RX1     (81) /* 65: CAN2 RX1 interrupt */
+#  define STM32_IRQ_CAN2SCE     (82) /* 66: CAN2 SCE interrupt */
+#  define STM32_IRQ_OTGFS       (83) /* 67: USB On The Go FS global interrupt */
+#  define NR_IRQS               (84)
 #else
 #  define STM32_IRQ_WWDG        (16) /* 0:  Window Watchdog interrupt */
 #  define STM32_IRQ_PVD         (17) /* 1:  PVD through EXTI Line detection interrupt */
diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c
index 75e160a50a..a11fe3cc99 100644
--- a/arch/arm/src/stm32/stm32_irq.c
+++ b/arch/arm/src/stm32/stm32_irq.c
@@ -218,10 +218,15 @@ static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
            *regaddr = NVIC_IRQ0_31_ENABLE;
            *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS);
         }
+      if (irq < STM32_IRQ_INTERRUPTS + 64)
+        {
+           *regaddr = NVIC_IRQ0_31_ENABLE;
+           *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS);
+        }
       else if (irq < NR_IRQS)
         {
-           *regaddr = NVIC_IRQ32_63_ENABLE;
-           *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS - 32);
+           *regaddr = NVIC_IRQ64_95_ENABLE;
+           *bit     = 1 << (irq - STM32_IRQ_INTERRUPTS - 64);
         }
       else
         {
@@ -229,7 +234,7 @@ static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit)
         }
     }
 
-  /* Handler processor exceptions.  Only a few can be disabled */
+  /* Handle processor exceptions.  Only a few can be disabled */
 
   else
     {