STM32L152: Better LOOPSPERMSEC; Need to set higher performance VOS
This commit is contained in:
Gregory Nutt
parent
b475e965a6
commit
9ea58951b4
@ -108,9 +108,9 @@
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# define PWR_CR_ULP (1 << 9) /* Ultralow power mode */
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# define PWR_CR_FWU (1 << 10) /* Low power run mode */
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# define PWR_CR_VOS_MASK (3 << 11) /* Bits 11-12: Regulator voltage scaling output selection */
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# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) */
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# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) */
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# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) */
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# define PWR_CR_VOS_SCALE_1 (1 << 11) /* 1.8 V (range 1) PLL VCO Max = 96MHz */
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# define PWR_CR_VOS_SCALE_2 (2 << 11) /* 1.5 V (range 2) PLL VCO Max = 64MHz */
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# define PWR_CR_VOS_SCALE_3 (3 << 11) /* 1.2 V (range 3) PLL VCO Max = 24MHz */
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# define PWR_CR_LPRUN (1 << 14) /* Low power run mode */
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#endif
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@ -621,5 +621,3 @@ void stm32_lowsetup(void)
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#else
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# error "Unsupported STM32 chip"
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#endif
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@ -2,7 +2,9 @@
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* arch/arm/src/stm32/stm32_pwr.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Authors: Uros Platise <uros.platise@isotel.eu>
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* Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -58,17 +60,17 @@
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static inline uint16_t stm32_pwr_getreg(uint8_t offset)
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{
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return getreg32(STM32_PWR_BASE + offset);
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return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
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{
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putreg32(value, STM32_PWR_BASE + offset);
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putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits)
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{
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modifyreg32(STM32_PWR_BASE + offset, clearbits, setbits);
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modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits);
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}
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/************************************************************************************
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@ -95,4 +97,47 @@ void stm32_pwr_enablebkp(void)
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stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP);
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}
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/************************************************************************************
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* Name: stm32_pwr_setvos
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*
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* Description:
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* Set voltage scaling for EneryLite devices.
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*
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* Input Parameters:
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* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
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*
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* Returned Values:
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* None
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*
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* Assumptions:
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* At present, this function is called only from initialization logic. If used
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* for any other purpose that protection to assure that its operation is atomic
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* will be required.
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*
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************************************************************************************/
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#ifdef CONFIG_STM32_ENERGYLITE
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void stm32_pwr_setvos(uint16_t vos)
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{
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uint16_t regval;
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/* The following sequence is required to program the voltage regulator ranges:
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* 1. Check VDD to identify which ranges are allowed...
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* 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.
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* 3. Configure the voltage scaling range by setting the VOS bits in the PWR_CR
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* register.
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* 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
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*/
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while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
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regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
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regval &= ~PWR_CR_VOS_MASK;
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regval |= (vos & PWR_CR_VOS_MASK);
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stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
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while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
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}
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#endif
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#endif /* CONFIG_STM32_PWR */
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_pwr.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -78,7 +78,30 @@ extern "C" {
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*
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************************************************************************************/
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EXTERN void stm32_pwr_enablebkp(void);
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void stm32_pwr_enablebkp(void);
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/************************************************************************************
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* Name: stm32_pwr_setvos
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*
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* Description:
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* Set voltage scaling for EneryLite devices.
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*
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* Input Parameters:
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* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
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*
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* Returned Values:
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* None
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*
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* Assumptions:
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* At present, this function is called only from initialization logic. If used
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* for any other purpose that protection to assure that its operation is atomic
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* will be required.
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*
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************************************************************************************/
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#ifdef CONFIG_STM32_ENERGYLITE
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void stm32_pwr_setvos(uint16_t vos);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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@ -1214,6 +1214,7 @@ static void up_setspeed(struct uart_dev_s *dev)
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static int up_setup(struct uart_dev_s *dev)
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{
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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#ifndef CONFIG_SUPPRESS_UART_CONFIG
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uint32_t regval;
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@ -1,5 +1,7 @@
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/****************************************************************************
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* arch/arm/src/stm32/stm32l15xxx_rcc.c
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* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-
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* based 32-bit MCUs
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -134,7 +136,11 @@ static inline void rcc_reset(void)
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putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
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/* Rest the FLASH controller to 32-bit mode, no wait states.
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/* Go to the (default) voltage range 2 */
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stm32_pwr_setvos(PWR_CR_VOS_SCALE_2);
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/* Reset the FLASH controller to 32-bit mode, no wait states.
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*
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* First, program the new number of WS to the LATENCY bit in Flash access
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* control register (FLASH_ACR)
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@ -490,8 +496,21 @@ static void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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/* First, enable the source clock only the PLL (via HSE or HSI), HSE, and HSI
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* are supported in this implementation.
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/* Go to the high performance voltage range 1 if necessary. In this mode,
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* the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported.
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*
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* Range 1: PLLVCO up to 96MHz in range 1 (1.8V)
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* Range 2: PLLVCO up to 48MHz in range 2 (1.5V)
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* Range 3: PLLVCO up to 24MHz in range 3 (1.2V)
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*/
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#if STM32_PLL_FREQUENCY > 48000000
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stm32_pwr_setvos(PWR_CR_VOS_SCALE_1);
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#endif
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/* Enable the source clock for the PLL (via HSE or HSI), HSE, and HSI.
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* NOTE that only PLL, HSE, or HSI are supported for the system clock
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* in this implementation
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*/
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#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
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@ -75,21 +75,21 @@
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* Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
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*/
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#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
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#define STM32_BOARD_XTAL 8000000ul /* X3 on board (not fitted)*/
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#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */
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#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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#define STM32_HSI_FREQUENCY 16000000ul /* Approximately 16MHz */
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_MSI_FREQUENCY 2097000 /* Default is approximately 2.097Mhz */
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#define STM32_LSI_FREQUENCY 37000 /* Approximately 37KHz */
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#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
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/* PLL Configuration
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*
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* - PLL source is HSI -> 16MHz input (nominal)
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* - PLL multipler is 4 -> 64MHz PLL VCO clock output
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* - PLL output divider 2 -> 32MHz divided down PLL VCO clock output
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* - PLL multipler is 6 -> 96MHz PLL VCO clock output (for USB)
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* - PLL output divider 3 -> 32MHz divided down PLL VCO clock output
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*
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* Resulting SYSCLK frequency is 16MHz x 4 / 2 = 32MHz
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* Resulting SYSCLK frequency is 16MHz x 6 / 3 = 32MHz
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*
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* USB/SDIO:
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* If the USB or SDIO interface is used in the application, the PLL VCO
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@ -106,50 +106,60 @@
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* The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
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*/
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#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */
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#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */
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#define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */
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#define STM32_PLL_FREQUENCY (4*STM32_HSE_FREQUENCY) /* PLL VCO Frequency is 64MHz */
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#define STM32_CFGR_PLLSRC 0 /* Source is 16MHz HSI */
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#ifdef CONFIG_STM32_USB
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# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx6 /* PLLMUL = 6 */
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# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_3 /* PLLDIV = 3 */
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# define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */
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#else
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# define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx4 /* PLLMUL = 4 */
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# define STM32_CFGR_PLLDIV RCC_CFGR_PLLDIV_2 /* PLLDIV = 2 */
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# define STM32_PLL_FREQUENCY (4*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 64MHz */
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#endif
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/* Use the PLL and set the SYSCLK source to be the diveded down PLL VCO output
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/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
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* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
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*/
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */
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#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */
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#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
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#ifdef CONFIG_STM32_USB
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# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/3) /* SYSCLK frequence is 96MHz/PLLDIV = 32MHz */
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#else
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# define STM32_SYSCLK_FREQUENCY (STM32_PLL_FREQUENCY/2) /* SYSCLK frequence is 64MHz/PLLDIV = 32MHz */
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#endif
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/* AHB clock (HCLK) is SYSCLK (32MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
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/* APB2 clock (PCLK2) is HCLK (32MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
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#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
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#define STM32_APB2_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB2 timers 9, 10, and 11 will receive PCLK2. */
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#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
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/* APB1 clock (PCLK1) is HCLK (32MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
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/* APB1 timers 2-7 will receive PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
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/* LED definitions ******************************************************************/
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/* The STM32L-Discovery board has four LEDs. Two of these are controlled by
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@ -172,14 +182,14 @@
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/* LED index values for use with stm32_setled() */
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#define BOARD_LED1 0 /* User LD3 */
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#define BOARD_LED2 1 /* User LD4 */
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#define BOARD_NLEDS 2
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#define BOARD_LED1 0 /* User LD3 */
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#define BOARD_LED2 1 /* User LD4 */
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#define BOARD_NLEDS 2
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/* LED bits for use with stm32_setleds() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 8 LEDs on board the
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* STM32L-Discovery. The following definitions describe how NuttX controls the LEDs:
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@ -198,14 +208,14 @@
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* LED_IDLE STM32 is is sleep mode Not used
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*/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 3
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 0
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#define LED_IRQSENABLED 0
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#define LED_STACKCREATED 1
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#define LED_INIRQ 2
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#define LED_SIGNAL 2
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#define LED_ASSERTION 2
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#define LED_PANIC 3
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/* Button definitions ***************************************************************/
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/* The STM32L-Discovery supports two buttons; only one button is controllable by
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@ -215,13 +225,12 @@
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* B2 RESET: pushbutton connected to NRST is used to RESET the STM32L152RBT6.
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*/
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#define BUTTON_USER 0
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternat Pin Functions **********************************************************/
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/* Alternate Pin Functions **********************************************************/
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/* The STM32L-Discovery has no on-board RS-232 driver. Further, there are no USART
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* pins that do not conflict with the on board resources, in particular, the LCD:
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* Most USART pins are available if the LCD is enabled; USART2 may be used if either
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@ -244,25 +253,25 @@
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#if !defined(CONFIG_STM32_LCD)
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/* Select PA9 and PA10 if the LCD is not enabled */
|
||||
|
||||
# define GPIO_USART1_RX GPIO_USART1_RX_1
|
||||
# define GPIO_USART1_TX GPIO_USART1_TX_1
|
||||
# define GPIO_USART1_RX GPIO_USART1_RX_1
|
||||
# define GPIO_USART1_TX GPIO_USART1_TX_1
|
||||
|
||||
/* This there are no other options for USART1 on this part */
|
||||
|
||||
# define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
# define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
# define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
# define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* Arbirtrarily select PB10 and PB11 */
|
||||
|
||||
# define GPIO_USART3_RX GPIO_USART3_RX_1
|
||||
# define GPIO_USART3_TX GPIO_USART3_TX_1
|
||||
# define GPIO_USART3_RX GPIO_USART3_RX_1
|
||||
# define GPIO_USART3_TX GPIO_USART3_TX_1
|
||||
|
||||
#elif !defined(CONFIG_ARCH_LEDS)
|
||||
|
||||
/* Select PB6 and PB7 if the LEDs are not enabled */
|
||||
|
||||
# define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
# define GPIO_USART1_TX GPIO_USART1_TX_2
|
||||
# define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
# define GPIO_USART1_TX GPIO_USART1_TX_2
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@ -266,7 +266,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
|
||||
#
|
||||
# Board Settings
|
||||
#
|
||||
CONFIG_BOARD_LOOPSPERMSEC=2500
|
||||
CONFIG_BOARD_LOOPSPERMSEC=2796
|
||||
# CONFIG_ARCH_CALIBRATION is not set
|
||||
CONFIG_DRAM_START=0x20000000
|
||||
CONFIG_DRAM_SIZE=16384
|
||||
|
||||
Loading…
Reference in New Issue
Block a user