rv32im: fix typo.

Signed-off-by: zhongan <zhongan@xiaomi.com>
2020-11-17 14:10:24 +08:00 · 2020-11-17 14:10:24 +08:00 · 9eae6edfde
commit 9eae6edfde
parent d4c0786f52
1 changed files with 2 additions and 2 deletions
--- a/arch/risc-v/src/rv32im/riscv_schedulesigaction.c
+++ b/arch/risc-v/src/rv32im/riscv_schedulesigaction.c
@ -32,8 +32,8 @@
 #include <nuttx/arch.h>

 #include "sched/sched.h"
-#include "up_internal.h"
-#include "up_arch.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"

 #ifndef CONFIG_DISABLE_SIGNALS