Squashed commit of the following:
Author: Gregory Nutt <gnutt@nuttx.org>
arch/arm/src/kinetis: Cosmetic changes from review of coding standard.
Author: David Sidrane <david_s5@nscdg.com>
Merged in david_s5/nuttx/master_kinetis (pull request #710)
kinetis:Add DMA and use it as RX FIFOs on Serial
* Add initial implementation of the DMA
* Add across Kxx family support [WIP]
* Incorporate the DMA into the serial
Add polling to serial
do DMA initialisation at UART startup and fix DMA mux setting.
Fix circular DMA handling in the serial driver.
* Adapt defconfig to enable UART1,4 RXDMA
* [WIP] - refactor this with new CONFIG DMA settings
* kinetis/Kconfig:Bring inline with upstream stucture
1. Use the Serial console configuration from drivers/serial/Kconfig
and friends.
2. Prefix arch specific featurs as such
UARTx_RXDMA->KINETIS_UARTx_RXDMA
* Kinetis:Serial formatting and clean up
* kinetis:DMA Formating and Cleanup
* kinetis:serial Use cleaner DMA API
* kinetis:Make.defs fix duplicate/errant kinetis_dma.o
* kinetis:serial Fix warning/error on only one uart using DMA
The driver can support no DMA on any UART, DMA on some
UARTs or DMA on all UARTs.
In the case of no DMA we disable the DMA based variables
and logic. In the case of all DMA we disable the non
DMA variables and logic, and in the mixed case both
DMA and non DMA variable and logic are enabled.
* kinetis:dma config fix formatting
* kinetis:chip/dma fix formatting
* kinetis:DMA config assume Unknown
Assume KINETIS_DMA_VERSION_UKN for all SoC not versioned
This is as the code was in nuttx prior to this commit
* kinetis:DMAMUX contain versioning- use HAS pattern define Unknown
The pattern for chip versioning is to define 'HAS' constants.
Define KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG to contain the
version numbers to the include soc header and use that define
in the chip headers.
Define the KINETIS_DMAMUX_VERSION_UKN for the default as prior
this commit addressing was by default monotonic for CHCFG
* freedom-k66f:Disable Serial RXDMA
The application has to add calling of the kinetis
serial dma poll as it is application specific.
Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
David Sidrane
Gregory Nutt
parent
2e23ffe9d2
commit
9ef481ce4b
@ -42,6 +42,8 @@
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/kinetis/kinetis_dma.h>
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#include <arch/kinetis/kinetis_dmamux.h>
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#include <arch/kinetis/kinetis_mcg.h>
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#include <arch/kinetis/kinetis_sim.h>
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#include <arch/kinetis/kinetis_pmc.h>
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209
arch/arm/include/kinetis/kinetis_dma.h
Normal file
209
arch/arm/include/kinetis/kinetis_dma.h
Normal file
@ -0,0 +1,209 @@
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/************************************************************************************
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* arch/arm/include/kinetis/kinetis_dma.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Jan Okle <jan@leitwert.ch>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
|
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMA_H
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#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMA_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Note: It is envisioned that in the long term as a chip is added. The author of
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* the new chip definitions will either find the exact configuration in an existing
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* chip define and add the new chip to it Or add the DMA feature configuration
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* #defines to the chip ifdef list below. In either case the author should mark
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* it as "Verified to Document Number:" taken from the reference manual.
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*/
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/* DMA Register Configuration
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*
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* KINETIS_DMA_HAS_CR_ERGA - DMA has CR[ERGA]
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* KINETIS_DMA_HAS_CR_GRP0PRI - DMA has CR[GRP0PRI]
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* KINETIS_DMA_HAS_CR_GRP1PRI - DMA has CR[GRP1PRI]
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* KINETIS_DMA_HAS_ES_ERRCHN - DMA has ES[ERRCHN]
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* KINETIS_DMA_HAS_ES_ERRCHN_BITS - DMA has 4 bit ES[ERRCHN]
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* KINETIS_DMA_HAS_ES_GPE - DMA has ES[GPE]
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* KINETIS_DMA_HAS_CEEI_CEEI_BITS - DMA has 4 bit CEEi[CEEI]
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* KINETIS_DMA_HAS_SEEI_SEEI_BITS - DMA has 4 bit SEEi[SEEI]
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* KINETIS_DMA_HAS_CERQ_CERQ_BITS - DMA has 4 bit CERQ[CERQ]
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* KINETIS_DMA_HAS_SERQ_SERQ_BITS - DMA has 4 bit SERQ[SERQ]
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* KINETIS_DMA_HAS_CDNE_CDNE_BITS - DMA has 4 bit CDNE[CDNE]
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* KINETIS_DMA_HAS_SSRT_SSRT_BITS - DMA has 4 bit SSRT[SSRT]
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* KINETIS_DMA_HAS_CERR_CERR_BITS - DMA has 4 bit CERR[CERR]
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* KINETIS_DMA_HAS_CINT_CINT_BITS - DMA has 4 bit CINT[CINT]
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* KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS - DMA has 4 bit DCHPRI[DCHPRI]
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* KINETIS_DMA_HAS_DCHPRI_GRPPRI - DMA has DCHPRI[GRPPRI]
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* KINETIS_DMA_HAS_EARS - DMA has EARS Register
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* KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS - DMA has 4 bit TCD_CITER[LINKCH]
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* KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS - DMA has 4 bit TCD_CSR[MAJORLINKCH]
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* KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS - DMA has 4 bit TCD_BITER[LINKCH]
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*/
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/* Describe the version of the DMA
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*
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* These defines are not related to any NXP reference but are merely
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* a way to label the versions we are using
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*/
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#define KINETIS_DMA_VERSION_UKN -1 /* What was in nuttx prior to 8/9/2018 */
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#define KINETIS_DMA_VERSION_01 1 /* Verified Document Number:
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* K60P144M100SF2V2RM Rev. 2, Jun 2012
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* K64P144M120SF5RM Rev. 2, Jan 2014
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*/
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#define KINETIS_DMA_VERSION_02 2 /* Verified Document Number:
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* K60P144M150SF3RM Rev. 3, Nov 2014
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* K66P144M180SF5RMV2 Rev. 2, May 2015
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*/
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#if defined(CONFIG_ARCH_CHIP_MK60DN256VLQ10) || defined(CONFIG_ARCH_CHIP_MK60DX256VLQ10) || \
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defined(CONFIG_ARCH_CHIP_MK60DN512VLQ10) || defined(CONFIG_ARCH_CHIP_MK60DN256VMD10) || \
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defined(CONFIG_ARCH_CHIP_MK60DX256VMD10) || defined(CONFIG_ARCH_CHIP_MK60DN512VMD10)
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/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_01
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#elif defined(CONFIG_ARCH_CHIP_MK60FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) || \
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defined(CONFIG_ARCH_CHIP_MK60FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VMD12) || \
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defined(CONFIG_ARCH_CHIP_MK60FX512VLQ15) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ15) || \
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defined(CONFIG_ARCH_CHIP_MK60FX512VMD15) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VMD15)
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/* Verified Document Number: K60P144M150SF3RM Rev. 3, Nov 2014 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_02
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#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
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defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
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defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
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defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
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/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_01
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/* MK66F N/X 1M0/2M0 V MD/LQ 18
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*
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* --------------- ------- --- ------- ------- ------ ------ ------ -----
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* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
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* FREQ CNT FLASH FLASH
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* --------------- ------- --- ------- ------- ------ ------ ------ -----
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* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
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* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
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* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
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* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
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*/
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#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
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defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
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/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_02
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#else
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_UKN
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#endif
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/* Use the catch all configuration for the DMA based on the implementations in nuttx
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* prior 8/10/2018
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*/
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#if KINETIS_DMA_VERSION == KINETIS_DMA_VERSION_UKN
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/* DMA Register Configuration */
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#if defined(CONFIG_KINETIS_DMA)
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# warning "DMA Unsupported on this Kinetis device!"
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#endif
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#elif KINETIS_DMA_VERSION == KINETIS_DMA_VERSION_01
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/* DMA Register Configuration */
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# undef DMA_CHN_PER_GROUP /* Number of channels per group */
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# undef KINETIS_DMA_HAS_CR_ERGA /* DMA has CR[ERGA ] */
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# undef KINETIS_DMA_HAS_CR_GRP0PRI /* DMA has CR[GRP0PRI] */
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# undef KINETIS_DMA_HAS_CR_GRP1PRI /* DMA has CR[GRP1PRI] */
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# define KINETIS_DMA_HAS_ES_ERRCHN 1 /* DMA has ES[ERRCHN] */
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# define KINETIS_DMA_HAS_ES_ERRCHN_BITS 4 /* DMA has 4 bit ES[ERRCHN] */
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# undef KINETIS_DMA_HAS_ES_GPE /* DMA has ES[GPE ] */
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# define KINETIS_DMA_HAS_CEEI_CEEI_BITS 4 /* DMA has 4 bit CEEi[CEEI]*/
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# define KINETIS_DMA_HAS_SEEI_SEEI_BITS 4 /* DMA has 4 bit SEEi[SEEI]*/
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# define KINETIS_DMA_HAS_CERQ_CERQ_BITS 4 /* DMA has 4 bit CERQ[CERQ]*/
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# define KINETIS_DMA_HAS_SERQ_SERQ_BITS 4 /* DMA has 4 bit SERQ[SERQ]*/
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# define KINETIS_DMA_HAS_CDNE_CDNE_BITS 4 /* DMA has 4 bit CDNE[CDNE]*/
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# define KINETIS_DMA_HAS_SSRT_SSRT_BITS 4 /* DMA has 4 bit SSRT[SSRT]*/
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# define KINETIS_DMA_HAS_CERR_CERR_BITS 4 /* DMA has 4 bit CERR[CERR]*/
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# define KINETIS_DMA_HAS_CINT_CINT_BITS 4 /* DMA has 4 bit CINT[CINT]*/
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# define KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS 4 /* DMA has 4 bit DCHPRI[DCHPRI]*/
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# undef KINETIS_DMA_HAS_DCHPRI_GRPPRI /* DMA has DCHPRI[GRPPRI] */
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# undef KINETIS_DMA_HAS_EARS /* DMA has EARS Register */
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# define KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS 4 /* DMA has 4 bit TCD_CITER[LINKCH] */
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# define KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS 4 /* DMA has 4 bit TCD_CSR[MAJORLINKCH] */
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# define KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS 4 /* DMA has 4 bit TCD_BITER[LINKCH] */
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#elif KINETIS_DMA_VERSION == KINETIS_DMA_VERSION_02
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/* DMA Register Configuration */
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# define DMA_CHN_PER_GROUP 16 /* Number of channels per group */
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# define KINETIS_DMA_HAS_CR_ERGA 1 /* DMA has CR[ERGA ] */
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# define KINETIS_DMA_HAS_CR_GRP0PRI 1 /* DMA has CR[GRP0PRI] */
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# define KINETIS_DMA_HAS_CR_GRP1PRI 1 /* DMA has CR[GRP1PRI] */
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# define KINETIS_DMA_HAS_ES_ERRCHN_BITS 5 /* DMA has 5 bit ES[ERRCHN] */
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# define KINETIS_DMA_HAS_ES_GPE 1 /* DMA has ES[GPE ] */
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# define KINETIS_DMA_HAS_CEEI_CEEI_BITS 5 /* DMA has 5 bit CEEI[CEEI]*/
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# define KINETIS_DMA_HAS_SEEI_SEEI_BITS 5 /* DMA has 5 bit SEEI[SEEI]*/
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# define KINETIS_DMA_HAS_CERQ_CERQ_BITS 5 /* DMA has 5 bit CERQ[CERQ]*/
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# define KINETIS_DMA_HAS_SERQ_SERQ_BITS 5 /* DMA has 5 bit SERQ[SERQ]*/
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# define KINETIS_DMA_HAS_CDNE_CDNE_BITS 5 /* DMA has 5 bit CDNE[CDNE]*/
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# define KINETIS_DMA_HAS_SSRT_SSRT_BITS 5 /* DMA has 5 bit SSRT[SSRT]*/
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# define KINETIS_DMA_HAS_CERR_CERR_BITS 5 /* DMA has 5 bit CERR[CERR]*/
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# define KINETIS_DMA_HAS_CINT_CINT_BITS 5 /* DMA has 5 bit CINT[CINT]*/
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# define KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS 5 /* DMA has 5 bit DCHPRI[DCHPRI]*/
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# define KINETIS_DMA_HAS_DCHPRI_GRPPRI 1 /* DMA has DCHPRI[GRPPRI] */
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# define KINETIS_DMA_HAS_EARS 1 /* DMA has EARS Register */
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# define KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS 5 /* DMA has 5 bit TCD_CITER[LINKCH] */
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# define KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS 5 /* DMA has 5 bit TCD_CSR[MAJORLINKCH] */
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# define KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS 5 /* DMA has 5 bit TCD_BITER[LINKCH] */
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#endif
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#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMA_H */
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152
arch/arm/include/kinetis/kinetis_dmamux.h
Normal file
152
arch/arm/include/kinetis/kinetis_dmamux.h
Normal file
@ -0,0 +1,152 @@
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/************************************************************************************
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* arch/arm/include/kinetis/kinetis_dmamux.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
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* Authors: Jan Okle <jan@leitwert.ch>
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
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|
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#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMAMUX_H
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#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMAMUX_H
|
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|
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/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Note: It is envisioned that in the long term as a chip is added. The author of
|
||||
* the new chip definitions will either find the exact configuration in an existing
|
||||
* chip define and add the new chip to it Or add the DMAMUX feature configuration
|
||||
* #defines to the chip ifdef list below. In either case the author should mark
|
||||
* it as "Verified to Document Number:" taken from the reference manual.
|
||||
*/
|
||||
|
||||
/* DMAMUX Register Configuration
|
||||
*
|
||||
* KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG 0|1 - SoC has reg in 0,1,2..KINETIS_NDMACH
|
||||
*/
|
||||
|
||||
/* Describe the version of the DMA
|
||||
*
|
||||
* These defines are not related to any NXP reference but are merely
|
||||
* a way to label the versions we are using
|
||||
*/
|
||||
|
||||
#define KINETIS_DMAMUX_VERSION_UKN -1 /* What was in nuttx prior to 8/9/2018 */
|
||||
#define KINETIS_DMAMUX_VERSION_01 1 /* Verified Document Number:
|
||||
* K60P144M150SF3RM Rev. 3, Nov 2014
|
||||
*/
|
||||
#define KINETIS_DMAMUX_VERSION_02 2 /* Verified Document Number:
|
||||
* K60P144M100SF2V2RM Rev. 2, Jun 2012
|
||||
* K64P144M120SF5RM Rev. 2, Jan 2014
|
||||
* K66P144M180SF5RMV2 Rev. 2, May 2015
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_MK60DN256VLQ10) || defined(CONFIG_ARCH_CHIP_MK60DX256VLQ10) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK60DN512VLQ10) || defined(CONFIG_ARCH_CHIP_MK60DN256VMD10) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK60DX256VMD10) || defined(CONFIG_ARCH_CHIP_MK60DN512VMD10)
|
||||
|
||||
/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
|
||||
|
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# define KINETIS_DMAMUX_VERSION KINETIS_DMAMUX_VERSION_02
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#elif defined(CONFIG_ARCH_CHIP_MK60FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK60FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VMD12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK60FX512VLQ15) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ15) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK60FX512VMD15) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VMD15)
|
||||
|
||||
/* Verified Document Number: K60P144M150SF3RM Rev. 3, Nov 2014 */
|
||||
|
||||
# define KINETIS_DMAMUX_VERSION KINETIS_DMAMUX_VERSION_01
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
|
||||
|
||||
/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
|
||||
|
||||
# define KINETIS_DMAMUX_VERSION KINETIS_DMAMUX_VERSION_02
|
||||
|
||||
/* MK66F N/X 1M0/2M0 V MD/LQ 18
|
||||
*
|
||||
* --------------- ------- --- ------- ------- ------ ------ ------ -----
|
||||
* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
|
||||
* FREQ CNT FLASH FLASH
|
||||
* --------------- ------- --- ------- ------- ------ ------ ------ -----
|
||||
* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
|
||||
* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
|
||||
* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
|
||||
* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
|
||||
*/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
|
||||
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
|
||||
|
||||
/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
|
||||
|
||||
# define KINETIS_DMAMUX_VERSION KINETIS_DMAMUX_VERSION_02
|
||||
|
||||
#else
|
||||
# define KINETIS_DMAMUX_VERSION KINETIS_DMAMUX_VERSION_UKN
|
||||
#endif
|
||||
|
||||
/* Use the catch all configuration for the DMAMUX based on the implementations in
|
||||
* nuttx prior 8/10/2018
|
||||
*/
|
||||
|
||||
#if KINETIS_DMA_VERSION == KINETIS_DMAMUX_VERSION_01
|
||||
|
||||
/* DMAMUX Register Configuration */
|
||||
|
||||
# define KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG 0 /* SoC has reg in 3,2,1,0..KINETIS_NDMACH */
|
||||
|
||||
#elif KINETIS_DMA_VERSION == KINETIS_DMAMUX_VERSION_02
|
||||
|
||||
/* DMAMUX Register Configuration */
|
||||
|
||||
# define KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG 1 /* SoC has reg in 0,1,2,3..KINETIS_NDMACH */
|
||||
|
||||
#elif KINETIS_DMA_VERSION == KINETIS_DMAMUX_VERSION_UKN
|
||||
|
||||
/* DMAMUX Register Configuration */
|
||||
|
||||
# define KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG 1 /* SoC has reg in 0,1,2,3..KINETIS_NDMACH */
|
||||
# if defined(CONFIG_KINETIS_DMA)
|
||||
# warning "DMAMUX Assuming monotonic CHCFG addressing!"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMAMUX_H */
|
||||
@ -316,6 +316,7 @@ config ARCH_FAMILY_K66
|
||||
select KINETIS_HAVE_LPUART0
|
||||
select KINETIS_HAVE_TPM1
|
||||
select KINETIS_HAVE_TPM2
|
||||
select KINETIS_HAVE_DMA
|
||||
|
||||
menu "Kinetis Peripheral Support"
|
||||
|
||||
@ -323,6 +324,10 @@ config KINETIS_HAVE_FTM3
|
||||
bool
|
||||
default n
|
||||
|
||||
config KINETIS_HAVE_DMA
|
||||
bool
|
||||
default n
|
||||
|
||||
config KINETIS_HAVE_I2C1
|
||||
bool
|
||||
default n
|
||||
@ -659,11 +664,11 @@ config KINETIS_LPTMR0
|
||||
Support the low power timer 0
|
||||
|
||||
config KINETIS_LPTMR1
|
||||
bool "Low power timer 0 (LPTMR1)"
|
||||
default n
|
||||
bool "Low power timer 0 (LPTMR1)"
|
||||
default n
|
||||
depends on KINETIS_HAVE_LPTMR1
|
||||
---help---
|
||||
Support the low power timer 1
|
||||
---help---
|
||||
Support the low power timer 1
|
||||
|
||||
config KINETIS_RTC
|
||||
bool "RTC"
|
||||
@ -723,6 +728,8 @@ config KINETIS_FTFL
|
||||
config KINETIS_DMA
|
||||
bool "DMA"
|
||||
default n
|
||||
depends on KINETIS_HAVE_DMA
|
||||
select ARCH_DMA
|
||||
---help---
|
||||
Support DMA
|
||||
|
||||
@ -1079,6 +1086,60 @@ config KINETIS_UARTFIFOS
|
||||
default n
|
||||
depends on KINETIS_UART0
|
||||
|
||||
config KINETIS_UART0_RXDMA
|
||||
bool "UART0 Rx DMA"
|
||||
default n
|
||||
depends on KINETIS_UART0 && KINETIS_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
config KINETIS_UART1_RXDMA
|
||||
bool "UART1 Rx DMA"
|
||||
default n
|
||||
depends on KINETIS_UART1 && KINETIS_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
config KINETIS_UART2_RXDMA
|
||||
bool "UART2 Rx DMA"
|
||||
default n
|
||||
depends on KINETIS_UART2 && KINETIS_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
config KINETIS_UART3_RXDMA
|
||||
bool "UART3 Rx DMA"
|
||||
default n
|
||||
depends on KINETIS_UART3 && KINETIS_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
config KINETIS_UART4_RXDMA
|
||||
bool "UART4 Rx DMA"
|
||||
default n
|
||||
depends on KINETIS_UART4 && KINETIS_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
config KINETIS_UART5_RXDMA
|
||||
bool "UART5 Rx DMA"
|
||||
default n
|
||||
depends on KINETIS_UART5 && KINETIS_DMA
|
||||
---help---
|
||||
In high data rate usage, Rx DMA may eliminate Rx overrun errors
|
||||
|
||||
config KINETIS_SERIAL_RXDMA_BUFFER_SIZE
|
||||
int "Rx DMA buffer size"
|
||||
default 32
|
||||
depends on UART1_RXDMA || UART2_RXDMA || UART3_RXDMA || UART4_RXDMA || UART5_RXDMA
|
||||
---help---
|
||||
The DMA buffer size when using RX DMA to emulate a FIFO.
|
||||
|
||||
When streaming data, the generic serial layer will be called
|
||||
every time the FIFO receives half this number of bytes.
|
||||
|
||||
Value given here will be rounded up to next multiple of 32 bytes.
|
||||
|
||||
endmenu # Kinetis UART Configuration
|
||||
|
||||
config KINETIS_MERGE_TTY
|
||||
|
||||
@ -159,10 +159,6 @@ ifeq ($(CONFIG_PWM),y)
|
||||
CHIP_CSRCS += kinetis_pwm.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_PWM),y)
|
||||
CHIP_CSRCS += kinetis_dma.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_I2C),y)
|
||||
CHIP_CSRCS += kinetis_i2c.c
|
||||
endif
|
||||
|
||||
@ -83,20 +83,21 @@
|
||||
#define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */
|
||||
#define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */
|
||||
|
||||
#ifndef KINETIS_K64
|
||||
# define KINETIS_DMA_TCD_OFFSET(n) (0x0000+((n) << 5))
|
||||
# define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
|
||||
# define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
|
||||
# define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
|
||||
# define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */
|
||||
# define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
|
||||
# define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */
|
||||
# define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
|
||||
# define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
# define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
# define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */
|
||||
# define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
#endif
|
||||
|
||||
#define KINETIS_DMA_DCHPRI_OFFSET(n) 0x0100 + (n - (n % 4)) + (3 - (n % 4)) /* Channel n Priority Register */
|
||||
|
||||
#define KINETIS_DMA_TCD_OFFSET(n) (0x0000 + ((n) << 5))
|
||||
#define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
|
||||
#define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */
|
||||
#define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */
|
||||
#define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */
|
||||
#define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */
|
||||
#define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */
|
||||
#define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */
|
||||
#define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */
|
||||
#define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */
|
||||
#define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */
|
||||
|
||||
#define KINETIS_DMA_TCD0_SADDR_OFFSET 0x0000 /* TCD Source Address */
|
||||
#define KINETIS_DMA_TCD0_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */
|
||||
@ -292,246 +293,246 @@
|
||||
|
||||
/* Register Addresses *******************************************************************************/
|
||||
|
||||
#define KINETIS_DMA_CR (KINETIS_DMAC_BASE+KINETIS_DMA_CR_OFFSET)
|
||||
#define KINETIS_DMA_ES (KINETIS_DMAC_BASE+KINETIS_DMA_ES_OFFSET)
|
||||
#define KINETIS_DMA_ERQ (KINETIS_DMAC_BASE+KINETIS_DMA_ERQ_OFFSET)
|
||||
#define KINETIS_DMA_EEI (KINETIS_DMAC_BASE+KINETIS_DMA_EEI_OFFSET)
|
||||
#define KINETIS_DMA_CEEI (KINETIS_DMAC_BASE+KINETIS_DMA_CEEI_OFFSET)
|
||||
#define KINETIS_DMA_SEEI (KINETIS_DMAC_BASE+KINETIS_DMA_SEEI_OFFSET)
|
||||
#define KINETIS_DMA_CERQ (KINETIS_DMAC_BASE+KINETIS_DMA_CERQ_OFFSET)
|
||||
#define KINETIS_DMA_SERQ (KINETIS_DMAC_BASE+KINETIS_DMA_SERQ_OFFSET)
|
||||
#define KINETIS_DMA_CDNE (KINETIS_DMAC_BASE+KINETIS_DMA_CDNE_OFFSET)
|
||||
#define KINETIS_DMA_SSRT (KINETIS_DMAC_BASE+KINETIS_DMA_SSRT_OFFSET)
|
||||
#define KINETIS_DMA_CERR (KINETIS_DMAC_BASE+KINETIS_DMA_CERR_OFFSET)
|
||||
#define KINETIS_DMA_CINT (KINETIS_DMAC_BASE+KINETIS_DMA_CINT_OFFSET)
|
||||
#define KINETIS_DMA_INT (KINETIS_DMAC_BASE+KINETIS_DMA_INT_OFFSET)
|
||||
#define KINETIS_DMA_ERR (KINETIS_DMAC_BASE+KINETIS_DMA_ERR_OFFSET)
|
||||
#define KINETIS_DMA_HRS (KINETIS_DMAC_BASE+KINETIS_DMA_HRS_OFFSET)
|
||||
#define KINETIS_DMA_CR (KINETIS_DMAC_BASE + KINETIS_DMA_CR_OFFSET)
|
||||
#define KINETIS_DMA_ES (KINETIS_DMAC_BASE + KINETIS_DMA_ES_OFFSET)
|
||||
#define KINETIS_DMA_ERQ (KINETIS_DMAC_BASE + KINETIS_DMA_ERQ_OFFSET)
|
||||
#define KINETIS_DMA_EEI (KINETIS_DMAC_BASE + KINETIS_DMA_EEI_OFFSET)
|
||||
#define KINETIS_DMA_CEEI (KINETIS_DMAC_BASE + KINETIS_DMA_CEEI_OFFSET)
|
||||
#define KINETIS_DMA_SEEI (KINETIS_DMAC_BASE + KINETIS_DMA_SEEI_OFFSET)
|
||||
#define KINETIS_DMA_CERQ (KINETIS_DMAC_BASE + KINETIS_DMA_CERQ_OFFSET)
|
||||
#define KINETIS_DMA_SERQ (KINETIS_DMAC_BASE + KINETIS_DMA_SERQ_OFFSET)
|
||||
#define KINETIS_DMA_CDNE (KINETIS_DMAC_BASE + KINETIS_DMA_CDNE_OFFSET)
|
||||
#define KINETIS_DMA_SSRT (KINETIS_DMAC_BASE + KINETIS_DMA_SSRT_OFFSET)
|
||||
#define KINETIS_DMA_CERR (KINETIS_DMAC_BASE + KINETIS_DMA_CERR_OFFSET)
|
||||
#define KINETIS_DMA_CINT (KINETIS_DMAC_BASE + KINETIS_DMA_CINT_OFFSET)
|
||||
#define KINETIS_DMA_INT (KINETIS_DMAC_BASE + KINETIS_DMA_INT_OFFSET)
|
||||
#define KINETIS_DMA_ERR (KINETIS_DMAC_BASE + KINETIS_DMA_ERR_OFFSET)
|
||||
#define KINETIS_DMA_HRS (KINETIS_DMAC_BASE + KINETIS_DMA_HRS_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_DCHPRI3 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI3_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI2 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI2_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI1 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI1_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI0 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI0_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI7 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI7_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI6 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI6_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI5 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI5_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI4 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI4_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI11 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI11_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI10 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI10_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI9 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI9_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI8 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI8_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI15 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI15_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI14 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI14_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI13 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI13_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI12 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI12_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI(n) (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI_OFFSET(n))
|
||||
|
||||
#ifndef KINETIS_K64
|
||||
# define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD_OFFSET(n))
|
||||
#define KINETIS_DMA_DCHPRI3 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI3_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI2 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI2_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI1 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI1_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI0 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI0_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI7 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI7_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI6 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI6_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI5 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI5_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI4 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI4_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI11 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI11_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI10 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI10_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI9 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI9_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI8 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI8_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI15 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI15_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI14 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI14_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI13 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI13_OFFSET)
|
||||
#define KINETIS_DMA_DCHPRI12 (KINETIS_DMAC_BASE + KINETIS_DMA_DCHPRI12_OFFSET)
|
||||
|
||||
# define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET)
|
||||
# define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET)
|
||||
# define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET)
|
||||
# define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET)
|
||||
# define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET)
|
||||
# define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET)
|
||||
# define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET)
|
||||
# define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET)
|
||||
# define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET)
|
||||
# define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET)
|
||||
# define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET)
|
||||
#endif
|
||||
#define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD_OFFSET(n))
|
||||
|
||||
#define KINETIS_DMA_TCD0_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD1_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD1_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD0_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD0_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD2_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_CSR_ (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD2_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD1_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD1_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD3_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_DLASTSGA_OFFSET
|
||||
#define KINETIS_DMA_TCD3_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD3_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_CSR_ (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD2_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD2_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD4_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_ATTR_OFFSET0)
|
||||
#define KINETIS_DMA_TCD4_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD4_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_DLASTSGA_OFFSET
|
||||
#define KINETIS_DMA_TCD3_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD3_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD3_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD5_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD5_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_ATTR_OFFSET0)
|
||||
#define KINETIS_DMA_TCD4_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD4_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD4_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD6_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD6_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD5_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD5_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD7_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DLASTSGA_ (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD7_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD6_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD6_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD8_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD8_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_DLASTSGA_ (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD7_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD7_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD9_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD9_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD8_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD8_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD10_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD10_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD9_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD9_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD11_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD11_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD10_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD10_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD12_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD12_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD11_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD11_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD13_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD13_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD12_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD12_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD14_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD14_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD13_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD13_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD15_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_ATTR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_NBYTES (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_SLAST (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_CITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DLASTSGA (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_CSR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_BITER (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD15_BITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD14_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD14_BITER_OFFSET)
|
||||
|
||||
#define KINETIS_DMA_TCD15_SADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_SOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_ATTR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_ATTR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_NBYTES (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_NBYTES_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_SLAST (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_SLAST_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DADDR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DADDR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DOFF (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DOFF_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_CITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CITER_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_DLASTSGA (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_DLASTSGA_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_CSR (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_CSR_OFFSET)
|
||||
#define KINETIS_DMA_TCD15_BITER (KINETIS_DMADESC_BASE + KINETIS_DMA_TCD15_BITER_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *************************************************************************/
|
||||
|
||||
@ -539,15 +540,25 @@
|
||||
/* Bit 0: Reserved */
|
||||
#define DMA_CR_EDBG (1 << 1) /* Bit 1: Enable debug */
|
||||
#define DMA_CR_ERCA (1 << 2) /* Bit 2: Enable round robin channel arbitration */
|
||||
/* Bit 3: Reserved */
|
||||
#if defined KINETIS_DMA_HAS_CR_ERGA
|
||||
# define DMA_CR_ERGA (1 << 3) /* Bit 3: Enable round robin group arbitration */
|
||||
#endif
|
||||
#define DMA_CR_HOE (1 << 4) /* Bit 4: Halt on error */
|
||||
#define DMA_CR_HALT (1 << 5) /* Bit 5: Halt DMA operations */
|
||||
#define DMA_CR_CLM (1 << 6) /* Bit 6: Continuous link mode */
|
||||
#define DMA_CR_EMLM (1 << 7) /* Bit 7: Enable minor loop mapping */
|
||||
/* Bits 8-15: Reserved */
|
||||
#ifdef KINETIS_DMA_HAS_CR_GRP0PRI
|
||||
# define DMA_CR_GRP0PRI (1 << 8) /* Bit 8: Channel Group 0 Priority */
|
||||
#endif
|
||||
/* Bit 9: Reserved */
|
||||
#ifdef KINETIS_DMA_HAS_CR_GRP1PRI
|
||||
# define DMA_CR_GRP1PRI (1 << 10) /* Bit 10: Channel Group 1 Priority */
|
||||
#endif
|
||||
/* Bits 11-15: Reserved */
|
||||
#define DMA_CR_ECX (1 << 16) /* Bit 16: Error cancel transfer */
|
||||
#define DMA_CR_CX (1 << 17) /* Bit 17: Cancel transfer */
|
||||
/* Bits 18-31: Reserved */
|
||||
|
||||
/* Error Status Register */
|
||||
|
||||
#define DMA_ES_DBE (1 << 0) /* Bit 0: Destination bus error */
|
||||
@ -558,58 +569,44 @@
|
||||
#define DMA_ES_DAE (1 << 5) /* Bit 5: Destination address error */
|
||||
#define DMA_ES_SOE (1 << 6) /* Bit 6: Source offset error */
|
||||
#define DMA_ES_SAE (1 << 7) /* Bit 7: Source address error */
|
||||
#define DMA_ES_ERRCHN_SHIFT (8) /* Bits 8-11: Error channel number or cancelled channel number */
|
||||
#define DMA_ES_ERRCHN_MASK (15 << DMA_ES_ERRCHN_SHIFT)
|
||||
/* Bits 12-13: Reserved */
|
||||
#define DMA_ES_ERRCHN_SHIFT (8) /* Bits 8-11/12: Error channel number or cancelled channel number */
|
||||
#define DMA_ES_ERRCHN_MASK (((1 << KINETIS_DMA_HAS_ES_ERRCHN_BITS) - 1) << DMA_ES_ERRCHN_SHIFT)
|
||||
/* Bits 13: Reserved */
|
||||
#define DMA_ES_CPE (1 << 14) /* Bit 14: Channel priority error */
|
||||
/* Bit 15: Reserved */
|
||||
#ifdef KINETIS_DMA_HAS_ES_GPE
|
||||
# define DMA_ES_GPE (1 << 15) /* Bit 15: Group priority error */
|
||||
#endif
|
||||
#define DMA_ES_ECX (1 << 16) /* Bit 16: Transfer cancelled */
|
||||
/* Bits 17-30: Reserved */
|
||||
#define DMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status bits */
|
||||
|
||||
/* Enable Request Register, Enable Error Interrupt Register, Interrupt Request Register, Error
|
||||
* Register, Hardware Request Status Register common bit definitions (32-bit, except for Error
|
||||
* Register which is 16-bit)
|
||||
/* Enable Request Register (ERQ), Enable Error Interrupt Register (EEI), Interrupt Request Register (INT),
|
||||
* Error Register (ERR), Hardware Request Status Register (HRS) common bit definitions
|
||||
*/
|
||||
|
||||
#define DMA_REQ(n) (1 << (n)) /* Bit n: DMA Request n */
|
||||
#define DMA_REQ0 (1 << 0) /* Bit 0: DMA Request 0 */
|
||||
#define DMA_REQ1 (1 << 1) /* Bit 1: DMA Request 1 */
|
||||
#define DMA_REQ2 (1 << 2) /* Bit 2: DMA Request 2 */
|
||||
#define DMA_REQ3 (1 << 3) /* Bit 3: DMA Request 3 */
|
||||
#define DMA_REQ4 (1 << 4) /* Bit 4: DMA Request 4 */
|
||||
#define DMA_REQ5 (1 << 5) /* Bit 5: DMA Request 5 */
|
||||
#define DMA_REQ6 (1 << 6) /* Bit 6: DMA Request 6 */
|
||||
#define DMA_REQ7 (1 << 7) /* Bit 7: DMA Request 7 */
|
||||
#define DMA_REQ8 (1 << 8) /* Bit 8: DMA Request 8 */
|
||||
#define DMA_REQ9 (1 << 9) /* Bit 9: DMA Request 9 */
|
||||
#define DMA_REQ10 (1 << 10) /* Bit 10: DMA Request 10 */
|
||||
#define DMA_REQ11 (1 << 11) /* Bit 11: DMA Request 11 */
|
||||
#define DMA_REQ12 (1 << 12) /* Bit 12: DMA Request 12 */
|
||||
#define DMA_REQ13 (1 << 13) /* Bit 13: DMA Request 13 */
|
||||
#define DMA_REQ14 (1 << 14) /* Bit 14: DMA Request 14 */
|
||||
#define DMA_REQ15 (1 << 15) /* Bit 15: DMA Request 15 */
|
||||
/* Bits 16-31: Reserved */
|
||||
#define DMA_REQ(n) (1 << (n)) /* Bit n: DMA Request n, n=0..<KINETIS_NDMACH */
|
||||
/* Bits KINETIS_NDMACH-31: Reserved */
|
||||
|
||||
/* Clear Enable Error Interrupt Register (8-bit) */
|
||||
|
||||
#define DMA_CEEI_SHIFT (0) /* Bits 0-3: Clear enable error interrupt */
|
||||
#define DMA_CEEI_MASK (15 << DMA_CEEI_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CEEI_SHIFT (0) /* Bits 0-3/4: Clear enable error interrupt */
|
||||
#define DMA_CEEI_MASK (((1 << KINETIS_DMA_HAS_CEEI_CEEI_BITS) - 1) << DMA_CEEI_SHIFT)
|
||||
/* Bits 5: Reserved */
|
||||
#define DMA_CEEI_CAEE (1 << 6) /* Bit 6: Clear all enable error interrupts */
|
||||
#define DMA_CEEI_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Set Enable Error Interrupt Register (8-bit) */
|
||||
|
||||
#define DMA_SEEI_SHIFT (0) /* Bits 0-3: Set enable error interrupt */
|
||||
#define DMA_SEEI_MASK (15 << DMA_SEEI_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_SEEI_SHIFT (0) /* Bits 0-3/4: Set enable error interrupt */
|
||||
#define DMA_SEEI_MASK (((1 << KINETIS_DMA_HAS_SEEI_SEEI_BITS) - 1) << DMA_SEEI_SHIFT)
|
||||
/* Bits 5: Reserved */
|
||||
#define DMA_SEEI_SAEE (1 << 6) /* Bit 6: Set all enable error interrupts */
|
||||
#define DMA_SEEI_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Clear Enable Request Register (8-bit) */
|
||||
|
||||
#define DMA_CERQ_SHIFT (0) /* Bits 0-3: Clear enable request */
|
||||
#define DMA_CERQ_MASK (15 << DMA_CERQ_SHIFT)
|
||||
#define DMA_CERQ_MASK (((1 << KINETIS_DMA_HAS_CERQ_CERQ_BITS) - 1) << DMA_CERQ_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CERQ_CAER (1 << 6) /* Bit 6: Clear all enable requests */
|
||||
#define DMA_CERQ_NOP (1 << 7) /* Bit 7: No operation */
|
||||
@ -617,15 +614,14 @@
|
||||
/* Set Enable Request Register (8-bit) */
|
||||
|
||||
#define DMA_SERQ_SHIFT (0) /* Bits 0-3: Set enable request */
|
||||
#define DMA_SERQ_MASK (15 << DMA_SERQ_SHIFT)
|
||||
#define DMA_SERQ_MASK (((1 << KINETIS_DMA_HAS_SERQ_SERQ_BITS) - 1) << DMA_SERQ_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_SERQ_SAER (1 << 6) /* Bit 6: Set all enable requests */
|
||||
#define DMA_SERQ_NOP (1 << 7) /* Bit 7: No operation */
|
||||
|
||||
/* Clear DONE Status Bit Register (8-bit) */
|
||||
|
||||
#define DMA_CDNE_SHIFT (0) /* Bits 0-3: Clear DONE bit */
|
||||
#define DMA_CDNE_MASK (15 << DMA_CDNE_SHIFT)
|
||||
#define DMA_CDNE_MASK (((1 << KINETIS_DMA_HAS_CDNE_CDNE_BITS) - 1) << DMA_CDNE_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CDNE_CADN (1 << 6) /* Bit 6: Clears all DONE bits */
|
||||
#define DMA_CDNE_NOP (1 << 7) /* Bit 7: No operation */
|
||||
@ -633,7 +629,7 @@
|
||||
/* Set START Bit Register (8-bit) */
|
||||
|
||||
#define DMA_SSRT_SHIFT (0) /* Bits 0-3: Set START bit */
|
||||
#define DMA_SSRT_MASK (15 << DMA_SSRT_SHIFT)
|
||||
#define DMA_SSRT_MASK (((1 << KINETIS_DMA_HAS_SSRT_SSRT_BITS) - 1) << DMA_SSRT_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_SSRT_SAST (1 << 6) /* Bit 6: Set all START bits (activates all channels) */
|
||||
#define DMA_SSRT_NOP (1 << 7) /* Bit 7: No operation */
|
||||
@ -641,7 +637,7 @@
|
||||
/* Clear Error Register (8-bit) */
|
||||
|
||||
#define DMA_CERR_SHIFT (0) /* Bits 0-3: Clear error indicator */
|
||||
#define DMA_CERR_MASK (15 << DMA_CERR_SHIFT)
|
||||
#define DMA_CERR_MASK (((1 << KINETIS_DMA_HAS_CERR_CERR_BITS) - 1) << DMA_CERR_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CERR_CAEI (1 << 6) /* Bit 6: Clear all error indicators */
|
||||
#define DMA_CERR_NOP (1 << 7) /* Bit 7: No operation */
|
||||
@ -649,7 +645,7 @@
|
||||
/* Clear Interrupt Request Register (8-bit) */
|
||||
|
||||
#define DMA_CINT_SHIFT (0) /* Bits 0-3: Clear interrupt request */
|
||||
#define DMA_CINT_MASK (15 << DMA_CINT_SHIFT)
|
||||
#define DMA_CINT_MASK (((1 << KINETIS_DMA_HAS_CINT_CINT_BITS) - 1) << DMA_CINT_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_CINT_CAIR (1 << 6) /* Bit 6: Clear all interrupt requests */
|
||||
#define DMA_CINT_NOP (1 << 7) /* Bit 7: No operation */
|
||||
@ -657,11 +653,18 @@
|
||||
/* Channel n Priority Register (8-bit) */
|
||||
|
||||
#define DMA_DCHPR_SHIFT (0) /* Bits 0-3: Channel n arbitration priority */
|
||||
#define DMA_DCHPR_MASK (15 << DMA_DCHPR_SHIFT)
|
||||
/* Bits 4-5: Reserved */
|
||||
#define DMA_DCHPR_MASK (((1 << KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS) - 1) << DMA_DCHPR_SHIFT)
|
||||
#ifdef KINETIS_DMA_HAS_DCHPRI_GRPPRI
|
||||
# define DMA_DCHPR_GRPPRI (1 << 4) /* Bits 4-5: Channel n Current Group Priority */
|
||||
#endif
|
||||
#define DMA_DCHPR_DPA (1 << 6) /* Bit 6: Disable preempt ability */
|
||||
#define DMA_DCHPR_ECP (1 << 7) /* Bit 7: Enable channel preemption */
|
||||
|
||||
/* Enable Asynchronous Request in Stop Register (32-bit) */
|
||||
|
||||
#ifdef KINETIS_DMA_HAS_EARS
|
||||
# define DMA_EARS(n) (1 << (n)) /* Bit n: DMA EARS n, n=0..<KINETIS_NDMACH */
|
||||
#endif
|
||||
|
||||
/* TCD Source Address. 32-bit address value. */
|
||||
/* TCD Signed Source Address Offset. 32-bit offset value. */
|
||||
@ -714,9 +717,9 @@
|
||||
|
||||
#define DMA_TCD_CITER1_SHIFT (0) /* Bits 0-8: Current major iteration count */
|
||||
#define DMA_TCD_CITER1_MASK (0x1ff << DMA_TCD_CITER1_SHIFT)
|
||||
#define DMA_TCD_CITER1_LINKCH_SHIFT (9) /* Bits 9-12: Link channel number */
|
||||
#define DMA_TCD_CITER1_LINKCH_MASK (15 << DMA_TCD_CITER1_LINKCH_SHIFT)
|
||||
/* Bits 13-14: Reserved */
|
||||
#define DMA_TCD_CITER1_LINKCH_SHIFT (9) /* Bits 9-12/13: Link channel number */
|
||||
#define DMA_TCD_CITER1_LINKCH_MASK (((1 << KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS) - 1) << DMA_TCD_CITER1_LINKCH_SHIFT)
|
||||
/* Bits 14: Reserved */
|
||||
#define DMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking on minor-loop complete (Case 1&2) */
|
||||
|
||||
/* Case 2: Channel Linking Disabled: */
|
||||
@ -737,9 +740,9 @@
|
||||
#define DMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable channel-to-channel linking on major loop complete */
|
||||
#define DMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel active */
|
||||
#define DMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel done */
|
||||
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-11: Link channel number */
|
||||
#define DMA_TCD_CSR_MAJORLINKCH_MASK (15 << DMA_TCD_CSR_MAJORLINKCH_SHIFT)
|
||||
/* Bits 12-13: Reserved */
|
||||
#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-11/12: Link channel number */
|
||||
#define DMA_TCD_CSR_MAJORLINKCH_MASK (((1 << KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS) - 1) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)
|
||||
/* Bits 13: Reserved */
|
||||
#define DMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth control */
|
||||
#define DMA_TCD_CSR_BWC_MASK (3 << DMA_TCD_CSR_BWC_SHIFT)
|
||||
# define DMA_TCD_CSR_BWC_NOSTALLS (0 << DMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
|
||||
@ -754,7 +757,7 @@
|
||||
#define DMA_TCD_BITER1_SHIFT (0) /* Bits 0-8: Starting major iteration count */
|
||||
#define DMA_TCD_BITER1_MASK (0x1ff << DMA_TCD_BITER1_SHIFT)
|
||||
#define DMA_TCD_BITER1_LINKCH_SHIFT (9) /* Bits 9-12: Link channel number */
|
||||
#define DMA_TCD_BITER1_LINKCH_MASK (15 << DMA_TCD_BITER1_LINKCH_SHIFT)
|
||||
#define DMA_TCD_BITER1_LINKCH_MASK (((1 << KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS) - 1) << DMA_TCD_BITER1_LINKCH_SHIFT)
|
||||
/* Bits 13-14: Reserved */
|
||||
#define DMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking on minor-loop complete (Case 1&2) */
|
||||
|
||||
|
||||
@ -1,8 +1,9 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/kinetis/chip/kinetis_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Copyright (C) 2011, 2016, 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Jan Okle <jan@leitwert.ch>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -50,43 +51,21 @@
|
||||
|
||||
/* Register Offsets *************************************************************************/
|
||||
|
||||
#define KINETIS_DMAMUX_CHCFG_OFFSET(n) (n) /* Channel n Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG0_OFFSET 0x0000 /* Channel 0 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG1_OFFSET 0x0001 /* Channel 1 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG2_OFFSET 0x0002 /* Channel 2 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG3_OFFSET 0x0003 /* Channel 3 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG4_OFFSET 0x0004 /* Channel 4 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG5_OFFSET 0x0005 /* Channel 5 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG6_OFFSET 0x0006 /* Channel 6 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG7_OFFSET 0x0007 /* Channel 7 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG8_OFFSET 0x0008 /* Channel 8 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG9_OFFSET 0x0009 /* Channel 9 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG10_OFFSET 0x000a /* Channel 10 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG11_OFFSET 0x000b /* Channel 11 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG12_OFFSET 0x000c /* Channel 12 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG13_OFFSET 0x000d /* Channel 13 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG14_OFFSET 0x000e /* Channel 14 Configuration Register */
|
||||
#define KINETIS_DMAMUX_CHCFG15_OFFSET 0x000f /* Channel 15 Configuration Register */
|
||||
#if KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG == 0
|
||||
|
||||
/* Channel n Configuration Register, 3,2,1,0,7,6,5,4 ..KINETIS_NDMACH-1 */
|
||||
|
||||
# define KINETIS_DMAMUX_CHCFG_OFFSET(n) (n - (n % 4)) + (3 - (n % 4))
|
||||
#elif KINETIS_DMAMUX_HAS_MONOTONIC_CHCFG == 1
|
||||
|
||||
/* Channel n Configuration Register, n=0..KINETIS_NDMACH-1 */
|
||||
|
||||
# define KINETIS_DMAMUX_CHCFG_OFFSET(n) (n)
|
||||
#endif
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
|
||||
#define KINETIS_DMAMUX_CHCFG(n) (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG_OFFSET(n))
|
||||
#define KINETIS_DMAMUX_CHCFG0 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG0_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG1 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG1_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG2 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG2_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG3 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG3_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG4 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG4_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG5 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG5_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG6 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG6_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG7 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG7_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG8 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG8_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG9 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG9_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG10 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG10_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG11 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG11_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG12 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG12_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG13 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG13_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG14 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG14_OFFSET)
|
||||
#define KINETIS_DMAMUX_CHCFG15 (KINETIS_DMAMUX0_BASE+KINETIS_DMAMUX_CHCFG15_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *****************************************************************/
|
||||
/* Channel n Configuration Register */
|
||||
@ -96,6 +75,189 @@
|
||||
#define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable */
|
||||
#define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable */
|
||||
|
||||
/* DMA Request sources*****************************************************************************/
|
||||
|
||||
#ifdef KINETIS_K60
|
||||
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART0_RX 2
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART0_TX 3
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART1_RX 4
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART1_TX 5
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART2_RX 6
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART2_TX 7
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART3_RX 8
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART3_TX 9
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART4_RX 10
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART4_TX 11
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART5_RX 12
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART5_TX 13
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2S0_RX 14
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2S0_TX 15
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI0_RX 16
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI0_TX 17
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI1_RX 18
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI1_TX 19
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI2_RX 20
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI2_TX 21
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2C0 22
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2C1 23
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH0 24
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH1 25
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH2 26
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH3 27
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH4 28
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH5 29
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH6 30
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH7 31
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM1_CH0 32
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM1_CH1 33
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM2_CH0 34
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM2_CH1 35
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER0 36
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER1 37
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER2 38
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER3 39
|
||||
# define KINETIS_DMA_REQUEST_SRC_ADC0 40
|
||||
# define KINETIS_DMA_REQUEST_SRC_ADC1 41
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP0 42
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP1 43
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP2 44
|
||||
# define KINETIS_DMA_REQUEST_SRC_DAC0 45
|
||||
# define KINETIS_DMA_REQUEST_SRC_DAC1 46
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMT 47
|
||||
# define KINETIS_DMA_REQUEST_SRC_PDB 48
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_A 49
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_B 50
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_C 51
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_D 52
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_E 53
|
||||
|
||||
#endif /* KINETIS_K60 */
|
||||
|
||||
#ifdef KINETIS_K64
|
||||
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART0_RX 2
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART0_TX 3
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART1_RX 4
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART1_TX 5
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART2_RX 6
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART2_TX 7
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART3_RX 8
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART3_TX 9
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART4_RXTX 10
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART5_RXTX 11
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2S0_RX 12
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2S0_TX 13
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI0_RX 14
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI0_TX 15
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI1_RXTX 16
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI2_RXTX 17
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2C0 18
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2C1__I2C2 19
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH0 20
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH1 21
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH2 22
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH3 23
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH4 24
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH5 25
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH6 26
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH7 27
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM1_CH0 28
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM1_CH1 29
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM2_CH0 30
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM2_CH1 31
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH0 32
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH1 33
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH2 34
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH3 35
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH4 36
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH5 37
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH6 38
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH7 39
|
||||
# define KINETIS_DMA_REQUEST_SRC_ADC0 40
|
||||
# define KINETIS_DMA_REQUEST_SRC_ADC1 41
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP0 42
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP1 43
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP2 44
|
||||
# define KINETIS_DMA_REQUEST_SRC_DAC0 45
|
||||
# define KINETIS_DMA_REQUEST_SRC_DAC1 46
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMT 47
|
||||
# define KINETIS_DMA_REQUEST_SRC_PDB 48
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_A 49
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_B 50
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_C 51
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_D 52
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_E 53
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER0 54
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER1 55
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER2 56
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER3 57
|
||||
|
||||
#endif /* KINETIS K64 */
|
||||
|
||||
#ifdef KINETIS_K66
|
||||
|
||||
# define KINETIS_DMA_REQUEST_SRC_TSI0 1
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART0_RX 2
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART0_TX 3
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART1_RX 4
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART1_TX 5
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART2_RX 6
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART2_TX 7
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART3_RX 8
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART3_TX 9
|
||||
# define KINETIS_DMA_REQUEST_SRC_UART4_RXTX 10
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2S0_RX 12
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2S0_TX 13
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI0_RX 14
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI0_TX 15
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI1_RX 16
|
||||
# define KINETIS_DMA_REQUEST_SRC_SPI1_TX 17
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2C0__I2C3 18
|
||||
# define KINETIS_DMA_REQUEST_SRC_I2C1__I2C2 19
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH0 20
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH1 21
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH2 22
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH3 23
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH4 24
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH5 25
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH6 26
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM0_CH7 27
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM1_TPM1_CH0 28
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM1_TPM1_CH1 29
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM2_TPM2_CH0 30
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM2_TPM2_CH1 31
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH0 32
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH1 33
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH2 34
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH3 35
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH4 36
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH5 37
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH6__SPI2_RX 38
|
||||
# define KINETIS_DMA_REQUEST_SRC_FTM3_CH7__SPI2_TX 39
|
||||
# define KINETIS_DMA_REQUEST_SRC_ADC0 40
|
||||
# define KINETIS_DMA_REQUEST_SRC_ADC1 41
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP0 42
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP1 43
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMP2__CMP3 44
|
||||
# define KINETIS_DMA_REQUEST_SRC_DAC0 45
|
||||
# define KINETIS_DMA_REQUEST_SRC_DAC1 46
|
||||
# define KINETIS_DMA_REQUEST_SRC_CMT 47
|
||||
# define KINETIS_DMA_REQUEST_SRC_PDB 48
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_A 49
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_B 50
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_C 51
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_D 52
|
||||
# define KINETIS_DMA_REQUEST_SRC_PCM_E 53
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER0 54
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER1 55
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER2 56
|
||||
# define KINETIS_DMA_REQUEST_SRC_TIMER3 57
|
||||
# define KINETIS_DMA_REQUEST_SRC_LPUART0_RX 58
|
||||
# define KINETIS_DMA_REQUEST_SRC_LPUART0_TX 59
|
||||
|
||||
#endif /* KINETIS_K66 */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Jan Okle <jan@leitwert.ch>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -44,6 +45,10 @@
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
@ -53,23 +58,100 @@
|
||||
#include "kinetis_config.h"
|
||||
#include "chip.h"
|
||||
#include "kinetis_dma.h"
|
||||
#include "chip/kinetis_dmamux.h"
|
||||
#include "chip/kinetis_sim.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef DMA_CHN_PER_GROUP
|
||||
# define DMA_CHN_PER_GROUP KINETIS_NDMACH /* Number of channels per group */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DMA_PRI
|
||||
# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
struct kinetis_dma_ch
|
||||
{
|
||||
bool used;
|
||||
uint8_t ind;
|
||||
uint8_t irq;
|
||||
kinetis_dma_direction_t dir;
|
||||
kinetis_dma_data_sz_t data_sz;
|
||||
dma_callback_t callback;
|
||||
void *arg;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct kinetis_dma_ch g_channels[KINETIS_NDMACH];
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static int kinetis_dmainterrupt_int(int irq, void *context,
|
||||
struct kinetis_dma_ch *ch)
|
||||
{
|
||||
/* Clear bit in the interrupt */
|
||||
|
||||
putreg8(ch->ind, KINETIS_DMA_CINT);
|
||||
|
||||
/* Invoke the callback */
|
||||
|
||||
if (ch->callback)
|
||||
{
|
||||
ch->callback((DMA_HANDLE)&ch, ch->arg, 0);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
static int kinetis_dmainterrupt(int irq, void *context, void *arg)
|
||||
{
|
||||
uint8_t irq_int = *(uint8_t *)arg;
|
||||
uint32_t regval;
|
||||
regval = getreg32(KINETIS_DMA_INT);
|
||||
|
||||
/* Channel irq_int and irq_int + DMA_CHN_PER_GROUP use the same arg. Check
|
||||
* which one requested an interrupt
|
||||
*/
|
||||
|
||||
if ((regval & (1 << irq_int)) != 0)
|
||||
{
|
||||
kinetis_dmainterrupt_int(irq, context, &g_channels[irq_int]);
|
||||
}
|
||||
|
||||
if ((regval & (1 << (irq_int + DMA_CHN_PER_GROUP))) != 0)
|
||||
{
|
||||
kinetis_dmainterrupt_int(irq, context,
|
||||
&g_channels[irq_int + DMA_CHN_PER_GROUP]);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
size_t kinetis_dmaresidual(DMA_HANDLE handle)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
|
||||
/* Channel Linking Disabled */
|
||||
|
||||
return ((getreg16(KINETIS_DMA_TCD_CITER(ch->ind)) >> DMA_TCD_CITER2_SHIFT) &
|
||||
DMA_TCD_CITER2_MASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmainitialize
|
||||
@ -82,9 +164,64 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmainitilaize(void)
|
||||
void weak_function up_dmainitialize(void)
|
||||
{
|
||||
int i;
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
|
||||
for (i = KINETIS_NDMACH - 1; i >= 0; i--)
|
||||
{
|
||||
g_channels[i].ind = i;
|
||||
g_channels[i].used = false;
|
||||
g_channels[i].irq = KINETIS_IRQ_FIRST + (i % DMA_CHN_PER_GROUP);
|
||||
|
||||
if (i < DMA_CHN_PER_GROUP)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* Set up the interrupt priority */
|
||||
|
||||
up_prioritize_irq(g_channels[i].irq, CONFIG_DMA_PRI);
|
||||
#endif
|
||||
|
||||
/* Attach DMA interrupt */
|
||||
|
||||
ret = irq_attach(g_channels[i].irq, kinetis_dmainterrupt,
|
||||
(void *)&g_channels[i].ind);
|
||||
|
||||
if (ret == OK)
|
||||
{
|
||||
/* Enable the IRQ at the NVIC (still disabled at the DMA
|
||||
* controller)
|
||||
*/
|
||||
|
||||
up_enable_irq(g_channels[i].irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
g_channels[i].used = true;
|
||||
g_channels[i + DMA_CHN_PER_GROUP].used = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable clocking for DMA */
|
||||
|
||||
regval = getreg32(KINETIS_SIM_SCGC7);
|
||||
regval |= SIM_SCGC7_DMA;
|
||||
putreg32(regval, KINETIS_SIM_SCGC7);
|
||||
|
||||
/* Configure DMA for round robin arbitration */
|
||||
|
||||
regval = 0;
|
||||
regval |= DMA_CR_ERCA | DMA_CR_ERGA;
|
||||
putreg32(regval, KINETIS_DMA_CR);
|
||||
|
||||
/* Enable clocking for the DMA mux*/
|
||||
|
||||
regval = getreg32(KINETIS_SIM_SCGC6);
|
||||
regval |= SIM_SCGC6_DMAMUX0;
|
||||
putreg32(regval, KINETIS_SIM_SCGC6);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -101,9 +238,85 @@ void kinetis_dmainitilaize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE kinetis_dmachannel(void)
|
||||
DMA_HANDLE kinetis_dmachannel(uint8_t src, uint32_t per_addr,
|
||||
kinetis_dma_data_sz_t per_data_sz,
|
||||
kinetis_dma_direction_t dir)
|
||||
{
|
||||
return NULL;
|
||||
int i;
|
||||
int ch_ind;
|
||||
uint8_t regval8;
|
||||
uint16_t regval16;
|
||||
irqstate_t flags;
|
||||
struct kinetis_dma_ch *ch;
|
||||
|
||||
/* Find available channel */
|
||||
|
||||
ch_ind = -1;
|
||||
flags = enter_critical_section();
|
||||
for (i = 0; i < KINETIS_NDMACH; i++)
|
||||
{
|
||||
if (!g_channels[i].used)
|
||||
{
|
||||
ch_ind = i;
|
||||
g_channels[ch_ind].used = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
if (ch_ind == -1)
|
||||
{
|
||||
/* No available channel */
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
ch = &g_channels[ch_ind];
|
||||
|
||||
/* Copy arguments */
|
||||
|
||||
ch->dir = dir;
|
||||
ch->data_sz = per_data_sz;
|
||||
|
||||
/* DMAMUX Set DMA channel source and enable it */
|
||||
|
||||
regval8 = ((((uint8_t)src) << DMAMUX_CHCFG_SOURCE_SHIFT) &
|
||||
DMAMUX_CHCFG_SOURCE_MASK) | DMAMUX_CHCFG_ENBL;
|
||||
putreg8(regval8, KINETIS_DMAMUX_CHCFG(ch_ind));
|
||||
|
||||
/* DMA Set peripheral address in TCD */
|
||||
|
||||
if (ch->dir == KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY)
|
||||
{
|
||||
putreg32(per_addr, KINETIS_DMA_TCD_SADDR(ch->ind));
|
||||
putreg16(0, KINETIS_DMA_TCD_SOFF(ch->ind));
|
||||
putreg32(0, KINETIS_DMA_TCD_SLAST(ch->ind));
|
||||
}
|
||||
else if (ch->dir == KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL)
|
||||
{
|
||||
putreg32(per_addr, KINETIS_DMA_TCD_DADDR(ch->ind));
|
||||
putreg16(0, KINETIS_DMA_TCD_DOFF(ch->ind));
|
||||
putreg32(0, KINETIS_DMA_TCD_DLASTSGA(ch->ind));
|
||||
}
|
||||
else
|
||||
{
|
||||
ch->used = false;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Set data sizes */
|
||||
|
||||
regval16 = (DMA_TCD_ATTR_SSIZE_MASK & ((uint16_t)per_data_sz) <<
|
||||
DMA_TCD_ATTR_SSIZE_SHIFT);
|
||||
regval16 |= (DMA_TCD_ATTR_DSIZE_MASK & ((uint16_t)per_data_sz) <<
|
||||
DMA_TCD_ATTR_DSIZE_SHIFT);
|
||||
putreg16(regval16, KINETIS_DMA_TCD_ATTR(ch->ind));
|
||||
|
||||
/* Set minor loop count */
|
||||
|
||||
putreg32(1 << (uint8_t)per_data_sz, KINETIS_DMA_TCD_NBYTES(ch->ind));
|
||||
return (DMA_HANDLE)ch;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -121,7 +334,18 @@ DMA_HANDLE kinetis_dmachannel(void)
|
||||
|
||||
void kinetis_dmafree(DMA_HANDLE handle)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
irqstate_t flags;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
/* Disable DMA channel in the dmamux */
|
||||
|
||||
putreg8(0, KINETIS_DMAMUX_CHCFG(ch->ind));
|
||||
|
||||
flags = enter_critical_section();
|
||||
ch->used = false;
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -132,10 +356,54 @@ void kinetis_dmafree(DMA_HANDLE handle)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
|
||||
uint32_t srcaddr, uint32_t destaddr, size_t nbytes)
|
||||
int kinetis_dmasetup(DMA_HANDLE handle, uint32_t mem_addr, size_t ntransfers,
|
||||
uint16_t control)
|
||||
{
|
||||
return -1;
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
uint16_t regval = 0;
|
||||
uint32_t nbytes;
|
||||
|
||||
if (ntransfers > (DMA_TCD_CITER2_MASK >> DMA_TCD_CITER2_SHIFT))
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
nbytes = (uint32_t)ntransfers * (uint32_t)(1 << (uint8_t)ch->data_sz);
|
||||
|
||||
if (ch->dir == KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY)
|
||||
{
|
||||
putreg32(mem_addr, KINETIS_DMA_TCD_DADDR(ch->ind));
|
||||
putreg16(1 << (uint8_t)ch->data_sz, KINETIS_DMA_TCD_DOFF(ch->ind));
|
||||
putreg32(-nbytes, KINETIS_DMA_TCD_DLASTSGA(ch->ind));
|
||||
}
|
||||
else if (ch->dir == KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL)
|
||||
{
|
||||
putreg32(mem_addr, KINETIS_DMA_TCD_SADDR(ch->ind));
|
||||
putreg16(1 << (uint8_t)ch->data_sz, KINETIS_DMA_TCD_SOFF(ch->ind));
|
||||
putreg32(-nbytes, KINETIS_DMA_TCD_SLAST(ch->ind));
|
||||
}
|
||||
else
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Set up channel with control word */
|
||||
|
||||
regval = (control & DMA_TCD_CSR_MAJORELINK) ? ch->ind : 0;
|
||||
regval <<= DMA_TCD_CSR_MAJORLINKCH_SHIFT;
|
||||
regval &= DMA_TCD_CSR_MAJORLINKCH_MASK;
|
||||
regval |= (DMA_TCD_CSR_INTMAJOR |
|
||||
(control & (DMA_TCD_CSR_INTHALF | DMA_TCD_CSR_MAJORELINK)));
|
||||
putreg16(regval, KINETIS_DMA_TCD_CSR(ch->ind));
|
||||
|
||||
/* Set major loop count */
|
||||
|
||||
putreg16(ntransfers, KINETIS_DMA_TCD_BITER(ch->ind));
|
||||
putreg16(ntransfers, KINETIS_DMA_TCD_CITER(ch->ind));
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -148,22 +416,37 @@ int kinetis_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
|
||||
|
||||
int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
ch->callback = callback;
|
||||
ch->arg = arg;
|
||||
|
||||
/* Enable request register for this channel */
|
||||
|
||||
putreg8(ch->ind, KINETIS_DMA_SERQ);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is
|
||||
* reset and kinetis_dmasetup() must be called before kinetis_dmastart() can be
|
||||
* called again
|
||||
* reset and kinetis_dmasetup() must be called before kinetis_dmastart()
|
||||
* can be called again
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmastop(DMA_HANDLE handle)
|
||||
{
|
||||
struct kinetis_dma_ch *ch = (struct kinetis_dma_ch *)handle;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
putreg8(ch->ind, KINETIS_DMA_CERQ);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -177,7 +460,7 @@ void kinetis_dmastop(DMA_HANDLE handle)
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs)
|
||||
{
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -193,7 +476,6 @@ void kinetis_dmasample(DMA_HANDLE handle, struct kinetis_dmaregs_s *regs)
|
||||
void kinetis_dmadump(DMA_HANDLE handle, const struct kinetis_dmaregs_s *regs,
|
||||
const char *msg)
|
||||
{
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -1,9 +1,10 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_dma.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016-2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Jan Okle <jan@leitwert.ch>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -57,7 +58,9 @@
|
||||
typedef FAR void *DMA_HANDLE;
|
||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
|
||||
|
||||
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is selected */
|
||||
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA is
|
||||
* selected.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
struct kinetis_dmaglobalregs_s
|
||||
@ -84,6 +87,21 @@ struct kinetis_dmaregs_s
|
||||
};
|
||||
#endif
|
||||
|
||||
typedef enum _kinetis_dma_direction_e
|
||||
{
|
||||
KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY,
|
||||
KINETIS_DMA_DIRECTION_MEMORY_TO_PERIPHERAL
|
||||
} kinetis_dma_direction_t;
|
||||
|
||||
/* Kinetis data transfer size */
|
||||
|
||||
typedef enum _kinetis_dma_data_sz_e
|
||||
{
|
||||
KINETIS_DMA_DATA_SZ_8BIT = 0,
|
||||
KINETIS_DMA_DATA_SZ_16BIT = 1,
|
||||
KINETIS_DMA_DATA_SZ_32BIT = 2,
|
||||
} kinetis_dma_data_sz_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
@ -99,10 +117,9 @@ extern "C"
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmainitialize
|
||||
@ -115,7 +132,7 @@ extern "C"
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmainitilaize(void);
|
||||
void kinetis_dmainitialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmachannel
|
||||
@ -124,22 +141,33 @@ void kinetis_dmainitilaize(void);
|
||||
* Allocate a DMA channel. This function sets aside a DMA channel and
|
||||
* gives the caller exclusive access to the DMA channel.
|
||||
*
|
||||
* Input Parameters:
|
||||
* src - DMA request source
|
||||
* per_addr - Address of the peripheral data
|
||||
* per_data_sz - Peripheral data size (register size). Note that if this
|
||||
* does not agree with the peripheral register size, DMA
|
||||
* transfers will silently fail during operation.
|
||||
* dir - transfer direction
|
||||
*
|
||||
* Returned Value:
|
||||
* One success, this function returns a non-NULL, void* DMA channel
|
||||
* One success, this function returns a non-NULL, void * DMA channel
|
||||
* handle. NULL is returned on any failure. This function can fail only
|
||||
* if no DMA channel is available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE kinetis_dmachannel(void);
|
||||
DMA_HANDLE kinetis_dmachannel(uint8_t src,
|
||||
uint32_t per_addr,
|
||||
kinetis_dma_data_sz_t per_data_sz,
|
||||
kinetis_dma_direction_t dir);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. NOTE: The 'handle' used in this argument must
|
||||
* NEVER be used again until kinetis_dmachannel() is called again to re-gain
|
||||
* a valid handle.
|
||||
* NEVER be used again until kinetis_dmachannel() is called again to re-
|
||||
* gain a valid handle.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
@ -154,10 +182,18 @@ void kinetis_dmafree(DMA_HANDLE handle);
|
||||
* Description:
|
||||
* Configure DMA for one transfer.
|
||||
*
|
||||
* Input Parameters:
|
||||
* mem_addr - Memory address
|
||||
* ntransfers - Number of transfers. Must be 0<= ntransfers <= 0x7FFF
|
||||
* control - Channel control configuration
|
||||
*
|
||||
* Returned Value:
|
||||
* result: 0 if ok, negative else
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int kinetis_dmasetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
|
||||
uint32_t srcaddr, uint32_t destaddr, size_t nbytes);
|
||||
int kinetis_dmasetup(DMA_HANDLE handle, uint32_t mem_addr,
|
||||
size_t ntransfers, uint16_t control);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmastart
|
||||
@ -174,13 +210,25 @@ int kinetis_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After kinetis_dmastop() is called, the DMA channel is
|
||||
* reset and kinetis_dmasetup() must be called before kinetis_dmastart() can be
|
||||
* called again
|
||||
* reset and kinetis_dmasetup() must be called before kinetis_dmastart()
|
||||
* can be called again
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void kinetis_dmastop(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Returns the number of transfers left
|
||||
*
|
||||
* Returned Value:
|
||||
* Residual transfers
|
||||
****************************************************************************/
|
||||
|
||||
size_t kinetis_dmaresidual(DMA_HANDLE handle);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_dmasample
|
||||
*
|
||||
|
||||
@ -1,9 +1,10 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_serial.c
|
||||
*
|
||||
* Copyright (C) 2011-2012, 2017 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2011-2012, 2017-2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* Jan Okle <jan@leitwert.ch>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -60,18 +61,23 @@
|
||||
#include <arch/serial.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "cache.h"
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "kinetis_config.h"
|
||||
#include "chip.h"
|
||||
#include "chip/kinetis_dmamux.h"
|
||||
#include "chip/kinetis_uart.h"
|
||||
#include "chip/kinetis_pinmux.h"
|
||||
#include "kinetis.h"
|
||||
#include "kinetis_dma.h"
|
||||
#include "kinetis_uart.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Some sanity checks *******************************************************/
|
||||
/* Is there at least one UART enabled and configured as a RS-232 device? */
|
||||
|
||||
@ -85,6 +91,10 @@
|
||||
|
||||
#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER)
|
||||
|
||||
/* Assume DMA is not used on the console UART */
|
||||
|
||||
#undef SERIAL_HAVE_CONSOLE_DMA
|
||||
|
||||
/* Which UART with be tty0/console and which tty1-4? The console will always
|
||||
* be ttyS0. If there is no console then will use the lowest numbered UART.
|
||||
*/
|
||||
@ -95,26 +105,44 @@
|
||||
# define CONSOLE_DEV g_uart0port /* UART0 is console */
|
||||
# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
|
||||
# define UART0_ASSIGNED 1
|
||||
# if defined(CONFIG_KINETIS_UART0_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
# endif
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define CONSOLE_DEV g_uart1port /* UART1 is console */
|
||||
# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */
|
||||
# define UART1_ASSIGNED 1
|
||||
# if defined(CONFIG_KINETIS_UART1_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
# endif
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define CONSOLE_DEV g_uart2port /* UART2 is console */
|
||||
# define TTYS0_DEV g_uart2port /* UART2 is ttyS0 */
|
||||
# define UART2_ASSIGNED 1
|
||||
# if defined(CONFIG_KINETIS_UART2_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
# endif
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
|
||||
# define CONSOLE_DEV g_uart3port /* UART3 is console */
|
||||
# define TTYS0_DEV g_uart3port /* UART3 is ttyS0 */
|
||||
# define UART3_ASSIGNED 1
|
||||
# if defined(CONFIG_KINETIS_UART3_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
# endif
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define CONSOLE_DEV g_uart4port /* UART4 is console */
|
||||
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
|
||||
# define UART4_ASSIGNED 1
|
||||
# if defined(CONFIG_KINETIS_UART4_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
# endif
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
|
||||
# define CONSOLE_DEV g_uart5port /* UART5 is console */
|
||||
# define TTYS5_DEV g_uart5port /* UART5 is ttyS0 */
|
||||
# define UART5_ASSIGNED 1
|
||||
# if defined(CONFIG_KINETIS_UART5_RXDMA)
|
||||
# define SERIAL_HAVE_CONSOLE_DMA 1
|
||||
# endif
|
||||
#else
|
||||
# undef CONSOLE_DEV /* No console */
|
||||
# if defined(CONFIG_KINETIS_UART0)
|
||||
@ -230,6 +258,40 @@
|
||||
# define UART5_ASSIGNED 1
|
||||
#endif
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
|
||||
/* The DMA buffer size when using RX DMA to emulate a FIFO.
|
||||
*
|
||||
* When streaming data, the generic serial layer will be called every time
|
||||
* the FIFO receives half this number of bytes.
|
||||
*
|
||||
* This buffer size should be an even multiple of the Cortex-M7 D-Cache line
|
||||
* size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated.
|
||||
*
|
||||
* Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
|
||||
* would be zero!
|
||||
*/
|
||||
|
||||
# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
|
||||
# undef ARMV7M_DCACHE_LINESIZE
|
||||
# define ARMV7M_DCACHE_LINESIZE 32
|
||||
# endif
|
||||
|
||||
# if !defined(CONFIG_KINETIS_SERIAL_RXDMA_BUFFER_SIZE) || \
|
||||
(CONFIG_KINETIS_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE)
|
||||
# undef CONFIG_KINETIS_SERIAL_RXDMA_BUFFER_SIZE
|
||||
# define CONFIG_KINETIS_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE
|
||||
# endif
|
||||
|
||||
# define RXDMA_BUFFER_MASK ((uint32_t)(ARMV7M_DCACHE_LINESIZE - 1))
|
||||
# define RXDMA_BUFFER_SIZE ((CONFIG_KINETIS_SERIAL_RXDMA_BUFFER_SIZE \
|
||||
+ RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
|
||||
|
||||
# define SERIAL_DMA_CONTROL_WORD \
|
||||
(DMA_TCD_CSR_MAJORELINK | \
|
||||
DMA_TCD_CSR_INTHALF)
|
||||
#endif /* SERIAL_HAVE_DMA */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
@ -260,6 +322,12 @@ struct up_dev_s
|
||||
#ifdef CONFIG_SERIAL_OFLOWCONTROL
|
||||
uint32_t cts_gpio; /* UART CTS GPIO pin configuration */
|
||||
#endif
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
const uint8_t rxdma_reqsrc;
|
||||
DMA_HANDLE rxdma; /* currently-open receive DMA stream */
|
||||
uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */
|
||||
char *const rxfifo; /* Receive DMA buffer */
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -275,9 +343,11 @@ static int up_interrupt(int irq, void *context, FAR void *arg);
|
||||
#endif
|
||||
static int up_interrupts(int irq, void *context, FAR void *arg);
|
||||
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
|
||||
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
|
||||
static void up_rxint(struct uart_dev_s *dev, bool enable);
|
||||
#if !defined(SERIAL_HAVE_ALL_DMA)
|
||||
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
|
||||
static bool up_rxavailable(struct uart_dev_s *dev);
|
||||
#endif
|
||||
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
||||
static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
|
||||
bool upper);
|
||||
@ -288,11 +358,21 @@ static bool up_txready(struct uart_dev_s *dev);
|
||||
#ifdef CONFIG_KINETIS_UARTFIFOS
|
||||
static bool up_txempty(struct uart_dev_s *dev);
|
||||
#endif
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static int up_dma_nextrx(struct up_dev_s *priv);
|
||||
static int up_dma_setup(struct uart_dev_s *dev);
|
||||
static void up_dma_shutdown(struct uart_dev_s *dev);
|
||||
static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status);
|
||||
static bool up_dma_rxavailable(struct uart_dev_s *dev);
|
||||
static uint8_t get_and_clear_uart_status(struct up_dev_s *priv);
|
||||
static void up_dma_rxcallback(DMA_HANDLE handle, void *arg, int result);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(SERIAL_HAVE_ALL_DMA)
|
||||
static const struct uart_ops_s g_uart_ops =
|
||||
{
|
||||
.setup = up_setup,
|
||||
@ -315,32 +395,87 @@ static const struct uart_ops_s g_uart_ops =
|
||||
.txempty = up_txready,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static const struct uart_ops_s g_uart_dma_ops =
|
||||
{
|
||||
.setup = up_dma_setup,
|
||||
.shutdown = up_dma_shutdown,
|
||||
.attach = up_attach,
|
||||
.detach = up_detach,
|
||||
.ioctl = up_ioctl,
|
||||
.receive = up_dma_receive,
|
||||
.rxint = up_rxint,
|
||||
.rxavailable = up_dma_rxavailable,
|
||||
#ifdef CONFIG_SERIAL_IFLOWCONTROL
|
||||
.rxflowcontrol = up_rxflowcontrol,
|
||||
#endif
|
||||
.send = up_send,
|
||||
.txint = up_txint,
|
||||
.txready = up_txready,
|
||||
#ifdef CONFIG_KINETIS_UARTFIFOS
|
||||
.txempty = up_txempty,
|
||||
#else
|
||||
.txempty = up_txready,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
||||
/* I/O buffers */
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART0
|
||||
static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
|
||||
static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
|
||||
# ifdef CONFIG_KINETIS_UART0_RXDMA
|
||||
static char g_uart0rxfifo[RXDMA_BUFFER_SIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART1
|
||||
static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
|
||||
static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
|
||||
# ifdef CONFIG_KINETIS_UART1_RXDMA
|
||||
static char g_uart1rxfifo[RXDMA_BUFFER_SIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART2
|
||||
static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
|
||||
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
|
||||
# ifdef CONFIG_KINETIS_UART2_RXDMA
|
||||
static char g_uart2rxfifo[RXDMA_BUFFER_SIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART3
|
||||
static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE];
|
||||
static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
|
||||
# ifdef CONFIG_KINETIS_UART3_RXDMA
|
||||
static char g_uart3rxfifo[RXDMA_BUFFER_SIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART4
|
||||
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
|
||||
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
|
||||
# ifdef CONFIG_KINETIS_UART4_RXDMA
|
||||
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART5
|
||||
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
|
||||
static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE];
|
||||
# ifdef CONFIG_KINETIS_UART5_RXDMA
|
||||
static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]
|
||||
__attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* This describes the state of the Kinetis UART0 port. */
|
||||
@ -360,13 +495,18 @@ static struct up_dev_s g_uart0priv =
|
||||
.bits = CONFIG_UART0_BITS,
|
||||
.stop2 = CONFIG_UART0_2STOP,
|
||||
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART0_OFLOWCONTROL)
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART0_CTS,
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART0_CTS,
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL)
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART0_RTS,
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART0_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_UART0_RXDMA
|
||||
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART0_RX,
|
||||
.rxfifo = g_uart0rxfifo,
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
static uart_dev_t g_uart0port =
|
||||
@ -381,7 +521,11 @@ static uart_dev_t g_uart0port =
|
||||
.size = CONFIG_UART0_TXBUFSIZE,
|
||||
.buffer = g_uart0txbuffer,
|
||||
},
|
||||
#ifdef CONFIG_KINETIS_UART0_RXDMA
|
||||
.ops = &g_uart_dma_ops,
|
||||
#else
|
||||
.ops = &g_uart_ops,
|
||||
#endif
|
||||
.priv = &g_uart0priv,
|
||||
};
|
||||
#endif
|
||||
@ -403,12 +547,16 @@ static struct up_dev_s g_uart1priv =
|
||||
.bits = CONFIG_UART1_BITS,
|
||||
.stop2 = CONFIG_UART1_2STOP,
|
||||
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART1_OFLOWCONTROL)
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART1_CTS,
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART1_CTS,
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL)
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART1_RTS,
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART1_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_UART1_RXDMA
|
||||
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART1_RX,
|
||||
.rxfifo = g_uart1rxfifo,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -424,7 +572,11 @@ static uart_dev_t g_uart1port =
|
||||
.size = CONFIG_UART1_TXBUFSIZE,
|
||||
.buffer = g_uart1txbuffer,
|
||||
},
|
||||
#ifdef CONFIG_KINETIS_UART1_RXDMA
|
||||
.ops = &g_uart_dma_ops,
|
||||
#else
|
||||
.ops = &g_uart_ops,
|
||||
#endif
|
||||
.priv = &g_uart1priv,
|
||||
};
|
||||
#endif
|
||||
@ -446,12 +598,16 @@ static struct up_dev_s g_uart2priv =
|
||||
.bits = CONFIG_UART2_BITS,
|
||||
.stop2 = CONFIG_UART2_2STOP,
|
||||
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART2_OFLOWCONTROL)
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART2_CTS,
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART2_CTS,
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL)
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART2_RTS,
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART2_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_UART2_RXDMA
|
||||
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART2_RX,
|
||||
.rxfifo = g_uart2rxfifo,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -467,7 +623,11 @@ static uart_dev_t g_uart2port =
|
||||
.size = CONFIG_UART2_TXBUFSIZE,
|
||||
.buffer = g_uart2txbuffer,
|
||||
},
|
||||
#ifdef CONFIG_KINETIS_UART2_RXDMA
|
||||
.ops = &g_uart_dma_ops,
|
||||
#else
|
||||
.ops = &g_uart_ops,
|
||||
#endif
|
||||
.priv = &g_uart2priv,
|
||||
};
|
||||
#endif
|
||||
@ -489,12 +649,16 @@ static struct up_dev_s g_uart3priv =
|
||||
.bits = CONFIG_UART3_BITS,
|
||||
.stop2 = CONFIG_UART3_2STOP,
|
||||
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART3_OFLOWCONTROL)
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART3_CTS,
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART3_CTS,
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL)
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART3_RTS,
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART3_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_UART3_RXDMA
|
||||
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART3_RX,
|
||||
.rxfifo = g_uart3rxfifo,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -510,7 +674,11 @@ static uart_dev_t g_uart3port =
|
||||
.size = CONFIG_UART3_TXBUFSIZE,
|
||||
.buffer = g_uart3txbuffer,
|
||||
},
|
||||
#ifdef CONFIG_KINETIS_UART3_RXDMA
|
||||
.ops = &g_uart_dma_ops,
|
||||
#else
|
||||
.ops = &g_uart_ops,
|
||||
#endif
|
||||
.priv = &g_uart3priv,
|
||||
};
|
||||
#endif
|
||||
@ -532,12 +700,16 @@ static struct up_dev_s g_uart4priv =
|
||||
.bits = CONFIG_UART4_BITS,
|
||||
.stop2 = CONFIG_UART4_2STOP,
|
||||
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART4_OFLOWCONTROL)
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART4_CTS,
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART4_CTS,
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL)
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART4_RTS,
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART4_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_UART4_RXDMA
|
||||
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART4_RXTX,
|
||||
.rxfifo = g_uart4rxfifo,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -553,7 +725,11 @@ static uart_dev_t g_uart4port =
|
||||
.size = CONFIG_UART4_TXBUFSIZE,
|
||||
.buffer = g_uart4txbuffer,
|
||||
},
|
||||
#ifdef CONFIG_KINETIS_UART4_RXDMA
|
||||
.ops = &g_uart_dma_ops,
|
||||
#else
|
||||
.ops = &g_uart_ops,
|
||||
#endif
|
||||
.priv = &g_uart4priv,
|
||||
};
|
||||
#endif
|
||||
@ -575,12 +751,16 @@ static struct up_dev_s g_uart5priv =
|
||||
.bits = CONFIG_UART5_BITS,
|
||||
.stop2 = CONFIG_UART5_2STOP,
|
||||
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_UART5_OFLOWCONTROL)
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART5_CTS,
|
||||
.oflow = true,
|
||||
.cts_gpio = PIN_UART5_CTS,
|
||||
#endif
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL)
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART5_RTS,
|
||||
.iflow = true,
|
||||
.rts_gpio = PIN_UART5_RTS,
|
||||
#endif
|
||||
#ifdef CONFIG_KINETIS_UART5_RXDMA
|
||||
.rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART5_RX,
|
||||
.rxfifo = g_uart5rxfifo,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -596,7 +776,11 @@ static uart_dev_t g_uart5port =
|
||||
.size = CONFIG_UART5_TXBUFSIZE,
|
||||
.buffer = g_uart5txbuffer,
|
||||
},
|
||||
#ifdef CONFIG_KINETIS_UART5_RXDMA
|
||||
.ops = &g_uart_dma_ops,
|
||||
#else
|
||||
.ops = &g_uart_ops,
|
||||
#endif
|
||||
.priv = &g_uart5priv,
|
||||
};
|
||||
#endif
|
||||
@ -678,6 +862,40 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: get_and_clear_uart_status
|
||||
*
|
||||
* Description:
|
||||
* Clears the error flags of the uart if an error occurred in s1 and
|
||||
* returns the status
|
||||
*
|
||||
* Input Parameters:
|
||||
* u_dev_s
|
||||
*
|
||||
* Returns Value:
|
||||
* Uart status s1
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static uint8_t get_and_clear_uart_status(struct up_dev_s *priv)
|
||||
{
|
||||
uint8_t regval;
|
||||
|
||||
regval = up_serialin(priv, KINETIS_UART_S1_OFFSET);
|
||||
if ((regval & (UART_S1_PF | UART_S1_FE | UART_S1_NF | UART_S1_OR)) != 0)
|
||||
{
|
||||
/* if an error occurred, clear the status flag by reading and
|
||||
* discarding the data.
|
||||
*/
|
||||
|
||||
(void)up_serialin(priv, KINETIS_UART_D_OFFSET);
|
||||
}
|
||||
|
||||
return regval;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_setup
|
||||
*
|
||||
@ -702,7 +920,6 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
bool oflow = false;
|
||||
#endif
|
||||
|
||||
|
||||
/* Configure the UART as an RS-232 UART */
|
||||
|
||||
kinetis_uartconfigure(priv->uartbase, priv->baud, priv->clock,
|
||||
@ -726,6 +943,71 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_setup
|
||||
*
|
||||
* Description:
|
||||
* Configure the UART baud, bits, parity, etc. This method is called the
|
||||
* first time that the serial port is opened.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static int up_dma_setup(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
int result;
|
||||
uint8_t regval;
|
||||
DMA_HANDLE rxdma = NULL;
|
||||
|
||||
/* Do the basic UART setup first, unless we are the console */
|
||||
|
||||
if (!dev->isconsole)
|
||||
{
|
||||
result = up_setup(dev);
|
||||
if (result != OK)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
}
|
||||
|
||||
/* Acquire the DMA channel.*/
|
||||
|
||||
rxdma = kinetis_dmachannel(priv->rxdma_reqsrc,
|
||||
priv->uartbase + KINETIS_UART_D_OFFSET,
|
||||
KINETIS_DMA_DATA_SZ_8BIT,
|
||||
KINETIS_DMA_DIRECTION_PERIPHERAL_TO_MEMORY);
|
||||
if (rxdma == NULL)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
/* Configure for circular DMA reception into the RX FIFO */
|
||||
|
||||
kinetis_dmasetup(rxdma, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE,
|
||||
SERIAL_DMA_CONTROL_WORD);
|
||||
|
||||
/* Reset our DMA shadow pointer to match the address just programmed above. */
|
||||
|
||||
priv->rxdmanext = 0;
|
||||
|
||||
/* Enable receive DMA for the UART */
|
||||
|
||||
regval = up_serialin(priv, KINETIS_UART_C5_OFFSET);
|
||||
regval |= UART_C5_RDMAS;
|
||||
up_serialout(priv, KINETIS_UART_C5_OFFSET, regval);
|
||||
|
||||
/* Start the DMA channel, and arrange for callbacks at the half and
|
||||
* full points in the FIFO. This ensures that we have half a FIFO
|
||||
* worth of time to claim bytes before they are overwritten.
|
||||
*/
|
||||
|
||||
kinetis_dmastart(rxdma, up_dma_rxcallback, (void *)dev);
|
||||
priv->rxdma = rxdma;
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_shutdown
|
||||
*
|
||||
@ -748,6 +1030,36 @@ static void up_shutdown(struct uart_dev_s *dev)
|
||||
kinetis_uartreset(priv->uartbase);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_shutdown
|
||||
*
|
||||
* Description:
|
||||
* Disable the UART. This method is called when the serial
|
||||
* port is closed
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static void up_dma_shutdown(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
DMA_HANDLE rxdma = priv->rxdma;
|
||||
priv->rxdma = NULL;
|
||||
|
||||
/* Perform the normal UART shutdown */
|
||||
|
||||
up_shutdown(dev);
|
||||
|
||||
/* Stop the DMA channel */
|
||||
|
||||
kinetis_dmastop(rxdma);
|
||||
|
||||
/* Release the DMA channel */
|
||||
|
||||
kinetis_dmafree(rxdma);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_attach
|
||||
*
|
||||
@ -1225,6 +1537,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(SERIAL_HAVE_ALL_DMA)
|
||||
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
@ -1255,6 +1568,66 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
|
||||
|
||||
return (int)up_serialin(priv, KINETIS_UART_D_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_receive
|
||||
*
|
||||
* Description:
|
||||
* Called (usually) from the interrupt level to receive one
|
||||
* character from the UART. Error bits associated with the
|
||||
* receipt are provided in the return 'status'.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
int c = 0;
|
||||
uint8_t s1;
|
||||
|
||||
/* Clear uart errors and return status information */
|
||||
|
||||
s1 = get_and_clear_uart_status(priv);
|
||||
if (status)
|
||||
{
|
||||
*status = (uint32_t)s1;
|
||||
}
|
||||
|
||||
if (up_dma_nextrx(priv) != priv->rxdmanext)
|
||||
{
|
||||
/* Invalidate the DMA buffer */
|
||||
|
||||
arch_invalidate_dcache((uintptr_t)priv->rxfifo,
|
||||
(uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE);
|
||||
|
||||
/* Now read from the DMA buffer */
|
||||
|
||||
c = priv->rxfifo[priv->rxdmanext];
|
||||
priv->rxdmanext++;
|
||||
if (priv->rxdmanext == RXDMA_BUFFER_SIZE)
|
||||
{
|
||||
/* HACK: Skip the first byte since it is duplicate of last one. */
|
||||
|
||||
if (up_dma_nextrx(priv) != 0)
|
||||
{
|
||||
priv->rxdmanext = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Try to catch race conditions that will spin on the whole
|
||||
* buffer again.
|
||||
*/
|
||||
|
||||
priv->rxdmanext = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_rxint
|
||||
@ -1303,6 +1676,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if !defined(SERIAL_HAVE_ALL_DMA)
|
||||
static bool up_rxavailable(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
@ -1324,6 +1698,28 @@ static bool up_rxavailable(struct uart_dev_s *dev)
|
||||
return (up_serialin(priv, KINETIS_UART_S1_OFFSET) & UART_S1_RDRF) != 0;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_rxavailable
|
||||
*
|
||||
* Description:
|
||||
* Return true if the receive register is not empty
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static bool up_dma_rxavailable(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
|
||||
|
||||
/* Compare our receive pointer to the current DMA pointer, if they
|
||||
* do not match, then there are bytes to be received.
|
||||
*/
|
||||
|
||||
return (up_dma_nextrx(priv) != priv->rxdmanext);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_rxflowcontrol
|
||||
@ -1398,6 +1794,26 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_nextrx
|
||||
*
|
||||
* Description:
|
||||
* Returns the index into the RX FIFO where the DMA will place the next
|
||||
* byte that it receives.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static int up_dma_nextrx(struct up_dev_s *priv)
|
||||
{
|
||||
size_t dmaresidual;
|
||||
|
||||
dmaresidual = kinetis_dmaresidual(priv->rxdma);
|
||||
|
||||
return (RXDMA_BUFFER_SIZE - (int)dmaresidual) % RXDMA_BUFFER_SIZE;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_send
|
||||
*
|
||||
@ -1487,7 +1903,7 @@ static bool up_txready(struct uart_dev_s *dev)
|
||||
* Name: up_txempty
|
||||
*
|
||||
* Description:
|
||||
* Return true if the tranmsit data register is empty
|
||||
* Return true if the transmit data register is empty
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@ -1502,6 +1918,27 @@ static bool up_txempty(struct uart_dev_s *dev)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_dma_rxcallback
|
||||
*
|
||||
* Description:
|
||||
* This function checks the current DMA state and calls the generic
|
||||
* serial stack when bytes appear to be available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
static void up_dma_rxcallback(DMA_HANDLE handle, void *arg, int result)
|
||||
{
|
||||
struct uart_dev_s *dev = (struct uart_dev_s *)arg;
|
||||
|
||||
if (up_dma_rxavailable(dev))
|
||||
{
|
||||
uart_recvchars(dev);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -1513,8 +1950,8 @@ static bool up_txempty(struct uart_dev_s *dev)
|
||||
* Performs the low level UART initialization early in debug so that the
|
||||
* serial console will be available during bootup. This must be called
|
||||
* before up_serialinit. NOTE: This function depends on GPIO pin
|
||||
* configuration performed in up_consoleinit() and main clock iniialization
|
||||
* performed in up_clkinitialize().
|
||||
* configuration performed in up_consoleinit() and main clock
|
||||
* initialization performed in up_clkinitialize().
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@ -1574,6 +2011,12 @@ unsigned int kinetis_uart_serialinit(unsigned int first)
|
||||
|
||||
#ifdef HAVE_UART_CONSOLE
|
||||
(void)uart_register("/dev/console", &CONSOLE_DEV);
|
||||
|
||||
# ifdef SERIAL_HAVE_CONSOLE_DMA
|
||||
/* If we need to re-initialise the console to enable DMA do that here. */
|
||||
|
||||
up_dma_setup(&CONSOLE_DEV);
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Register all UARTs */
|
||||
@ -1603,6 +2046,70 @@ unsigned int kinetis_uart_serialinit(unsigned int first)
|
||||
return first;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_serial_dma_poll
|
||||
*
|
||||
* Description:
|
||||
* Checks receive DMA buffers for received bytes that have not accumulated
|
||||
* to the point where the DMA half/full interrupt has triggered.
|
||||
*
|
||||
* This function should be called from a timer or other periodic context.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
void kinetis_serial_dma_poll(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART0_RXDMA
|
||||
if (g_uart0priv.rxdma != NULL)
|
||||
{
|
||||
up_dma_rxcallback(g_uart0priv.rxdma, (void *)&g_uart0port, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART1_RXDMA
|
||||
if (g_uart1priv.rxdma != NULL)
|
||||
{
|
||||
up_dma_rxcallback(g_uart1priv.rxdma, (void *)&g_uart1port, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART2_RXDMA
|
||||
if (g_uart2priv.rxdma != NULL)
|
||||
{
|
||||
up_dma_rxcallback(g_uart2priv.rxdma, (void *)&g_uart2port, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART3_RXDMA
|
||||
if (g_uart3priv.rxdma != NULL)
|
||||
{
|
||||
up_dma_rxcallback(g_uart3priv.rxdma, (void *)&g_uart3port, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART4_RXDMA
|
||||
if (g_uart4priv.rxdma != NULL)
|
||||
{
|
||||
up_dma_rxcallback(g_uart4priv.rxdma, (void *)&g_uart4port, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KINETIS_UART5_RXDMA
|
||||
if (g_uart5priv.rxdma != NULL)
|
||||
{
|
||||
up_dma_rxcallback(g_uart5priv.rxdma, (void *)&g_uart5port, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_putc
|
||||
*
|
||||
@ -1666,4 +2173,3 @@ int up_putc(int ch)
|
||||
#endif
|
||||
|
||||
#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER) */
|
||||
|
||||
|
||||
118
arch/arm/src/kinetis/kinetis_uart.h
Normal file
118
arch/arm/src/kinetis/kinetis_uart.h
Normal file
@ -0,0 +1,118 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_uart.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: David Sidrane <david_s5@nscdg.com>
|
||||
* Jan Okle <jan@leitwert.ch>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H
|
||||
#define __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H
|
||||
|
||||
#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER)
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
/* Is DMA available on any (enabled) UART? */
|
||||
|
||||
#undef SERIAL_HAVE_DMA
|
||||
#if defined(CONFIG_KINETIS_UART0_RXDMA) || defined(CONFIG_KINETIS_UART1_RXDMA) || \
|
||||
defined(CONFIG_KINETIS_UART2_RXDMA) || defined(CONFIG_KINETIS_UART3_RXDMA) || \
|
||||
defined(CONFIG_KINETIS_UART4_RXDMA) || defined(CONFIG_KINETIS_UART5_RXDMA)
|
||||
# define SERIAL_HAVE_DMA 1
|
||||
|
||||
/* Is DMA available on All (enabled) UART? */
|
||||
|
||||
#define SERIAL_HAVE_ALL_DMA 1
|
||||
# if (defined(CONFIG_KINETIS_UART0) && !defined(CONFIG_KINETIS_UART0_RXDMA)) || \
|
||||
(defined(CONFIG_KINETIS_UART1) && !defined(CONFIG_KINETIS_UART1_RXDMA)) || \
|
||||
(defined(CONFIG_KINETIS_UART2) && !defined(CONFIG_KINETIS_UART2_RXDMA)) || \
|
||||
(defined(CONFIG_KINETIS_UART3) && !defined(CONFIG_KINETIS_UART3_RXDMA)) || \
|
||||
(defined(CONFIG_KINETIS_UART4) && !defined(CONFIG_KINETIS_UART4_RXDMA)) || \
|
||||
(defined(CONFIG_KINETIS_UART5) && !defined(CONFIG_KINETIS_UART5_RXDMA))
|
||||
# undef SERIAL_HAVE_ALL_DMA
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: kinetis_serial_dma_poll
|
||||
*
|
||||
* Description:
|
||||
* Must be called periodically if any Kinetis UART is configured for DMA. The DMA
|
||||
* callback is triggered for each fifo size/2 bytes, but this can result in some
|
||||
* bytes being transferred but not collected if the incoming data is not a whole
|
||||
* multiple of half the FIFO size.
|
||||
*
|
||||
* May be safely called from either interrupt or thread context.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef SERIAL_HAVE_DMA
|
||||
void kinetis_serial_dma_poll(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER) */
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H */
|
||||
@ -36,6 +36,7 @@ CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_I2C_RESET=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_KINETIS_DMA=y
|
||||
CONFIG_KINETIS_FTM0=y
|
||||
CONFIG_KINETIS_FTM0_CHANNEL=2
|
||||
CONFIG_KINETIS_FTM0_PWM=y
|
||||
@ -86,8 +87,8 @@ CONFIG_RTC_DRIVER=y
|
||||
CONFIG_RTC_HIRES=y
|
||||
CONFIG_SCHED_CHILD_STATUS=y
|
||||
CONFIG_SCHED_HAVE_PARENT=y
|
||||
CONFIG_SCHED_HPWORK=y
|
||||
CONFIG_SCHED_HPWORKPERIOD=50000
|
||||
CONFIG_SCHED_HPWORK=y
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_SDCLONE_DISABLE=y
|
||||
CONFIG_SERIAL_TERMIOS=y
|
||||
|
||||
Loading…
Reference in New Issue
Block a user