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Add ARMv7-M DWT and TPI register definitions

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This commit is contained in:
Gregory Nutt 2014-10-21 16:46:26 -06:00
parent 485e71bf7e
commit 9ef8abc5ec
3 changed files with 354 additions and 12 deletions
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173
arch/arm/src/armv7-m/dwt.h Normal file
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/***********************************************************************************************
* arch/arm/src/armv7-m/dwt.h
*
* Copyright (c) 2009 - 2013 ARM LIMITED
*
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Author: Pierre-noel Bouteville <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***********************************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_M_DWT_H
#define __ARCH_ARM_SRC_ARMV7_M_DWT_H
/***********************************************************************************************
* Pre-processor Definitions
***********************************************************************************************/
/* Data Watchpoint and Trace Register (DWT) Definitions ****************************************/
/* DWT Register Base Address *******************************************************************/
#define DWT_BASE (0xe0001000ul)
/* DWT Register Addresses **********************************************************************/
#define DWT_CTRL (DWT_BASE+0x0000) /* Control Register */
#define DWT_CYCCNT (DWT_BASE+0x0004) /* Cycle Count Register */
#define DWT_CPICNT (DWT_BASE+0x0008) /* CPI Count Register */
#define DWT_EXCCNT (DWT_BASE+0x000c) /* Exception Overhead Count Register */
#define DWT_SLEEPCNT (DWT_BASE+0x0010) /* Sleep Count Register */
#define DWT_LSUCNT (DWT_BASE+0x0014) /* LSU Count Register */
#define DWT_FOLDCNT (DWT_BASE+0x0018) /* Folded-instruction Count Register */
#define DWT_PCSR (DWT_BASE+0x001c) /* Program Counter Sample Register */
#define DWT_COMP0 (DWT_BASE+0x0020) /* Comparator Register 0 */
#define DWT_MASK0 (DWT_BASE+0x0024) /* Mask Register 0 */
#define DWT_FUNCTION0 (DWT_BASE+0x0028) /* Function Register 0 */
#define DWT_COMP1 (DWT_BASE+0x0030) /* Comparator Register 1 */
#define DWT_MASK1 (DWT_BASE+0x0034) /* Mask Register 1 */
#define DWT_FUNCTION1 (DWT_BASE+0x0038) /* Function Register 1 */
#define DWT_COMP2 (DWT_BASE+0x0040) /* Comparator Register 2 */
#define DWT_MASK2 (DWT_BASE+0x0044) /* Mask Register 2 */
#define DWT_FUNCTION2 (DWT_BASE+0x0048) /* Function Register 2 */
#define DWT_COMP3 (DWT_BASE+0x0050) /* Comparator Register 3 */
#define DWT_MASK3 (DWT_BASE+0x0054) /* Mask Register 3 */
#define DWT_FUNCTION3 (DWT_BASE+0x0058) /* Function Register 3 */
/* DWT Register Bit Field Definitions **********************************************************/
#define DWT_CTRL_NUMCOMP_Pos 28 /* DWT CTRL: NUMCOMP Position */
#define DWT_CTRL_NUMCOMP_Msk (0xFul << DWT_CTRL_NUMCOMP_Pos) /* DWT CTRL: NUMCOMP Mask */
#define DWT_CTRL_NOTRCPKT_Pos 27 /* DWT CTRL: NOTRCPKT Position */
#define DWT_CTRL_NOTRCPKT_Msk (0x1ul << DWT_CTRL_NOTRCPKT_Pos) /* DWT CTRL: NOTRCPKT Mask */
#define DWT_CTRL_NOEXTTRIG_Pos 26 /* DWT CTRL: NOEXTTRIG Position */
#define DWT_CTRL_NOEXTTRIG_Msk (0x1ul << DWT_CTRL_NOEXTTRIG_Pos) /* DWT CTRL: NOEXTTRIG Mask */
#define DWT_CTRL_NOCYCCNT_Pos 25 /* DWT CTRL: NOCYCCNT Position */
#define DWT_CTRL_NOCYCCNT_Msk (0x1ul << DWT_CTRL_NOCYCCNT_Pos) /* DWT CTRL: NOCYCCNT Mask */
#define DWT_CTRL_NOPRFCNT_Pos 24 /* DWT CTRL: NOPRFCNT Position */
#define DWT_CTRL_NOPRFCNT_Msk (0x1ul << DWT_CTRL_NOPRFCNT_Pos) /* DWT CTRL: NOPRFCNT Mask */
#define DWT_CTRL_CYCEVTENA_Pos 22 /* DWT CTRL: CYCEVTENA Position */
#define DWT_CTRL_CYCEVTENA_Msk (0x1ul << DWT_CTRL_CYCEVTENA_Pos) /* DWT CTRL: CYCEVTENA Mask */
#define DWT_CTRL_FOLDEVTENA_Pos 21 /* DWT CTRL: FOLDEVTENA Position */
#define DWT_CTRL_FOLDEVTENA_Msk (0x1ul << DWT_CTRL_FOLDEVTENA_Pos) /* DWT CTRL: FOLDEVTENA Mask */
#define DWT_CTRL_LSUEVTENA_Pos 20 /* DWT CTRL: LSUEVTENA Position */
#define DWT_CTRL_LSUEVTENA_Msk (0x1ul << DWT_CTRL_LSUEVTENA_Pos) /* DWT CTRL: LSUEVTENA Mask */
#define DWT_CTRL_SLEEPEVTENA_Pos 19 /* DWT CTRL: SLEEPEVTENA Position */
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1ul << DWT_CTRL_SLEEPEVTENA_Pos) /* DWT CTRL: SLEEPEVTENA Mask */
#define DWT_CTRL_EXCEVTENA_Pos 18 /* DWT CTRL: EXCEVTENA Position */
#define DWT_CTRL_EXCEVTENA_Msk (0x1ul << DWT_CTRL_EXCEVTENA_Pos) /* DWT CTRL: EXCEVTENA Mask */
#define DWT_CTRL_CPIEVTENA_Pos 17 /* DWT CTRL: CPIEVTENA Position */
#define DWT_CTRL_CPIEVTENA_Msk (0x1ul << DWT_CTRL_CPIEVTENA_Pos) /* DWT CTRL: CPIEVTENA Mask */
#define DWT_CTRL_EXCTRCENA_Pos 16 /* DWT CTRL: EXCTRCENA Position */
#define DWT_CTRL_EXCTRCENA_Msk (0x1ul << DWT_CTRL_EXCTRCENA_Pos) /* DWT CTRL: EXCTRCENA Mask */
#define DWT_CTRL_PCSAMPLENA_Pos 12 /* DWT CTRL: PCSAMPLENA Position */
#define DWT_CTRL_PCSAMPLENA_Msk (0x1ul << DWT_CTRL_PCSAMPLENA_Pos) /* DWT CTRL: PCSAMPLENA Mask */
#define DWT_CTRL_SYNCTAP_Pos 10 /* DWT CTRL: SYNCTAP Position */
#define DWT_CTRL_SYNCTAP_Msk (0x3ul << DWT_CTRL_SYNCTAP_Pos) /* DWT CTRL: SYNCTAP Mask */
#define DWT_CTRL_CYCTAP_Pos 9 /* DWT CTRL: CYCTAP Position */
#define DWT_CTRL_CYCTAP_Msk (0x1ul << DWT_CTRL_CYCTAP_Pos) /* DWT CTRL: CYCTAP Mask */
#define DWT_CTRL_POSTINIT_Pos 5 /* DWT CTRL: POSTINIT Position */
#define DWT_CTRL_POSTINIT_Msk (0xful << DWT_CTRL_POSTINIT_Pos) /* DWT CTRL: POSTINIT Mask */
#define DWT_CTRL_POSTPRESET_Pos 1 /* DWT CTRL: POSTPRESET Position */
#define DWT_CTRL_POSTPRESET_Msk (0xful << DWT_CTRL_POSTPRESET_Pos) /* DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0 /* DWT CTRL: CYCCNTENA Position */
#define DWT_CTRL_CYCCNTENA_Msk (0x1ul << DWT_CTRL_CYCCNTENA_Pos) /* DWT CTRL: CYCCNTENA Mask */
#define DWT_CPICNT_CPICNT_Pos 0 /* DWT CPICNT: CPICNT Position */
#define DWT_CPICNT_CPICNT_Msk (0xfful << DWT_CPICNT_CPICNT_Pos) /* DWT CPICNT: CPICNT Mask */
#define DWT_EXCCNT_EXCCNT_Pos 0 /* DWT EXCCNT: EXCCNT Position */
#define DWT_EXCCNT_EXCCNT_Msk (0xfful << DWT_EXCCNT_EXCCNT_Pos) /* DWT EXCCNT: EXCCNT Mask */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /* DWT SLEEPCNT: SLEEPCNT Position */
#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xfful << DWT_SLEEPCNT_SLEEPCNT_Pos) /* DWT SLEEPCNT: SLEEPCNT Mask */
#define DWT_LSUCNT_LSUCNT_Pos 0 /* DWT LSUCNT: LSUCNT Position */
#define DWT_LSUCNT_LSUCNT_Msk (0xfful << DWT_LSUCNT_LSUCNT_Pos) /* DWT LSUCNT: LSUCNT Mask */
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /* DWT FOLDCNT: FOLDCNT Position */
#define DWT_FOLDCNT_FOLDCNT_Msk (0xfful << DWT_FOLDCNT_FOLDCNT_Pos) /* DWT FOLDCNT: FOLDCNT Mask */
#define DWT_MASK_MASK_Pos 0 /* DWT MASK: MASK Position */
#define DWT_MASK_MASK_Msk (0x1ful << DWT_MASK_MASK_Pos) /* DWT MASK: MASK Mask */
#define DWT_FUNCTION_MATCHED_Pos 24 /* DWT FUNCTION: MATCHED Position */
#define DWT_FUNCTION_MATCHED_Msk (0x1ul << DWT_FUNCTION_MATCHED_Pos) /* DWT FUNCTION: MATCHED Mask */
#define DWT_FUNCTION_DATAVADDR1_Pos 16 /* DWT FUNCTION: DATAVADDR1 Position */
#define DWT_FUNCTION_DATAVADDR1_Msk (0xful << DWT_FUNCTION_DATAVADDR1_Pos) /* DWT FUNCTION: DATAVADDR1 Mask */
#define DWT_FUNCTION_DATAVADDR0_Pos 12 /* DWT FUNCTION: DATAVADDR0 Position */
#define DWT_FUNCTION_DATAVADDR0_Msk (0xful << DWT_FUNCTION_DATAVADDR0_Pos) /* DWT FUNCTION: DATAVADDR0 Mask */
#define DWT_FUNCTION_DATAVSIZE_Pos 10 /* DWT FUNCTION: DATAVSIZE Position */
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3ul << DWT_FUNCTION_DATAVSIZE_Pos) /* DWT FUNCTION: DATAVSIZE Mask */
#define DWT_FUNCTION_LNK1ENA_Pos 9 /* DWT FUNCTION: LNK1ENA Position */
#define DWT_FUNCTION_LNK1ENA_Msk (0x1ul << DWT_FUNCTION_LNK1ENA_Pos) /* DWT FUNCTION: LNK1ENA Mask */
#define DWT_FUNCTION_DATAVMATCH_Pos 8 /* DWT FUNCTION: DATAVMATCH Position */
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1ul << DWT_FUNCTION_DATAVMATCH_Pos) /* DWT FUNCTION: DATAVMATCH Mask */
#define DWT_FUNCTION_CYCMATCH_Pos 7 /* DWT FUNCTION: CYCMATCH Position */
#define DWT_FUNCTION_CYCMATCH_Msk 0x1ul << DWT_FUNCTION_CYCMATCH_Pos) /* DWT FUNCTION: CYCMATCH Mask */
#define DWT_FUNCTION_EMITRANGE_Pos 5 /* DWT FUNCTION: EMITRANGE Position */
#define DWT_FUNCTION_EMITRANGE_Msk (0x1ul << DWT_FUNCTION_EMITRANGE_Pos) /* DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0 /* DWT FUNCTION: FUNCTION Position */
#define DWT_FUNCTION_FUNCTION_Msk (0xful << DWT_FUNCTION_FUNCTION_Pos) /* DWT FUNCTION: FUNCTION Mask */
#endif /* __ARCH_ARM_SRC_ARMV7_M_DWT_H */

17
arch/arm/src/armv7-m/itm.h
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@ -72,11 +72,12 @@
* Pre-processor Definitions
***********************************************************************************************/
/* Instrumentation Trace Macrocell Register (ITM) ase address. */
/* Instrumentation Trace Macrocell Register (ITM) Definitions **********************************/
/* ITM Register Base Address *******************************************************************/
#define ITM_BASE (0xe0000000ul)
/* ITM port used : 0-31 */
/* ITM Register Addresses **********************************************************************/
#define ITM_PORT(i) (ITM_BASE+(i*4)) /* Stimulus Port 32-bit */
#define ITM_TER (ITM_BASE+0x0e00) /* Trace Enable Register */
@ -100,33 +101,27 @@
#define ITM_CID2 (ITM_BASE+0x0ff8) /* Component Identification Register #2 */
#define ITM_CID3 (ITM_BASE+0x0ffc) /* Component Identification Register #3 */
/* ITM Register Bit Field Definitions **********************************************************/
#define ITM_TPR_PRIVMASK_Pos 0 /* ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xful << ITM_TPR_PRIVMASK_Pos) /* ITM TPR: PRIVMASK Mask */
#define ITM_TCR_BUSY_Pos 23 /* ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /* ITM TCR: BUSY Mask */
#define ITM_TCR_TraceBusID_Pos 16 /* ITM TCR: ATBID Position */
#define ITM_TCR_TraceBusID_Msk (0x7ful << ITM_TCR_TraceBusID_Pos) /* ITM TCR: ATBID Mask */
#define ITM_TCR_GTSFREQ_Pos 10 /* ITM TCR: Global timestamp frequency Position */
#define ITM_TCR_GTSFREQ_Msk (3ul << ITM_TCR_GTSFREQ_Pos) /* ITM TCR: Global timestamp frequency Mask */
#define ITM_TCR_TSPrescale_Pos 8 /* ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /* ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4 /* ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /* ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3 /* ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /* ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2 /* ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /* ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1 /* ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /* ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /* ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /* ITM TCR: ITM Enable bit Mask */
@ -141,10 +136,8 @@
#define ITM_LSR_ByteAcc_Pos 2 /* ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /* ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1 /* ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /* ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /* ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /* ITM LSR: Present Mask */

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arch/arm/src/armv7-m/tpi.h Normal file
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@ -0,0 +1,176 @@
/***********************************************************************************************
* arch/arm/src/armv7-m/tpi.h
*
* Copyright (c) 2009 - 2013 ARM LIMITED
*
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
* *
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
* Author: Pierre-noel Bouteville <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
***********************************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_M_TPI_H
#define __ARCH_ARM_SRC_ARMV7_M_TPI_H
/***********************************************************************************************
* Pre-processor Definitions
***********************************************************************************************/
/* Trace Port Interface Register (TPI) Definitions *********************************************/
/* TPI Register Base Address *******************************************************************/
#define TPI_BASE (0xe0040000ul)
/* TPI Register Addresses **********************************************************************/
#define TPI_SSPSR (TPI_BASE+0x0000) /* Supported Parallel Port Size Register */
#define TPI_CSPSR (TPI_BASE+0x0004) /* Current Parallel Port Size Register */
#define TPI_ACPR (TPI_BASE+0x0010) /* Asynchronous Clock Prescaler Register */
#define TPI_SPPR (TPI_BASE+0x00f0) /* Selected Pin Protocol Register */
#define TPI_FFSR (TPI_BASE+0x0300) /* Formatter and Flush Status Register */
#define TPI_FFCR (TPI_BASE+0x0304) /* Formatter and Flush Control Register */
#define TPI_FSCR (TPI_BASE+0x0308) /* Formatter Synchronization Counter Register */
#define TPI_TRIGGER (TPI_BASE+0x0ee8) /* TRIGGER */
#define TPI_FIFO0 (TPI_BASE+0x0eec) /* Integration ETM Data */
#define TPI_ITATBCTR2 (TPI_BASE+0x0ef0) /* ITATBCTR2 */
#define TPI_ITATBCTR0 (TPI_BASE+0x0ef8) /* ITATBCTR0 */
#define TPI_FIFO1 (TPI_BASE+0x0efc) /* Integration ITM Data */
#define TPI_ITCTRL (TPI_BASE+0x0f00) /* Integration Mode Control */
#define TPI_CLAIMSET (TPI_BASE+0x0fa0) /* Claim tag set */
#define TPI_CLAIMCLR (TPI_BASE+0x0fa4) /* Claim tag clear */
#define TPI_DEVID (TPI_BASE+0x0fc8) /* TPIU_DEVID */
#define TPI_DEVTYPE (TPI_BASE+0x0fcc) /* TPIU_DEVTYPE */
/* TPI Register Bit Field Definitions **********************************************************/
#define TPI_ACPR_PRESCALER_Pos 0 /* TPI ACPR: PRESCALER Position */
#define TPI_ACPR_PRESCALER_Msk (0x1ffful << TPI_ACPR_PRESCALER_Pos) /* TPI ACPR: PRESCALER Mask */
#define TPI_SPPR_TXMODE_Pos 0 /* TPI SPPR: TXMODE Position */
#define TPI_SPPR_TXMODE_Msk (0x3ul << TPI_SPPR_TXMODE_Pos) /* TPI SPPR: TXMODE Mask */
#define TPI_FFSR_FtNonStop_Pos 3 /* TPI FFSR: FtNonStop Position */
#define TPI_FFSR_FtNonStop_Msk (0x1ul << TPI_FFSR_FtNonStop_Pos) /* TPI FFSR: FtNonStop Mask */
#define TPI_FFSR_TCPresent_Pos 2 /* TPI FFSR: TCPresent Position */
#define TPI_FFSR_TCPresent_Msk (0x1ul << TPI_FFSR_TCPresent_Pos) /* TPI FFSR: TCPresent Mask */
#define TPI_FFSR_FtStopped_Pos 1 /* TPI FFSR: FtStopped Position */
#define TPI_FFSR_FtStopped_Msk (0x1ul << TPI_FFSR_FtStopped_Pos) /* TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0 /* TPI FFSR: FlInProg Position */
#define TPI_FFSR_FlInProg_Msk (0x1ul << TPI_FFSR_FlInProg_Pos) /* TPI FFSR: FlInProg Mask */
#define TPI_FFCR_TrigIn_Pos 8 /* TPI FFCR: TrigIn Position */
#define TPI_FFCR_TrigIn_Msk (0x1ul << TPI_FFCR_TrigIn_Pos) /* TPI FFCR: TrigIn Mask */
#define TPI_FFCR_EnFCont_Pos 1 /* TPI FFCR: EnFCont Position */
#define TPI_FFCR_EnFCont_Msk (0x1ul << TPI_FFCR_EnFCont_Pos) /* TPI FFCR: EnFCont Mask */
#define TPI_TRIGGER_TRIGGER_Pos 0 /* TPI TRIGGER: TRIGGER Position */
#define TPI_TRIGGER_TRIGGER_Msk (0x1ul << TPI_TRIGGER_TRIGGER_Pos) /* TPI TRIGGER: TRIGGER Mask */
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /* TPI FIFO0: ITM_ATVALID Position */
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3ul << TPI_FIFO0_ITM_ATVALID_Pos) /* TPI FIFO0: ITM_ATVALID Mask */
#define TPI_FIFO0_ITM_bytecount_Pos 27 /* TPI FIFO0: ITM_bytecount Position */
#define TPI_FIFO0_ITM_bytecount_Msk (0x3ul << TPI_FIFO0_ITM_bytecount_Pos) /* TPI FIFO0: ITM_bytecount Mask */
#define TPI_FIFO0_ETM_ATVALID_Pos 26 /* TPI FIFO0: ETM_ATVALID Position */
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3ul << TPI_FIFO0_ETM_ATVALID_Pos) /* TPI FIFO0: ETM_ATVALID Mask */
#define TPI_FIFO0_ETM_bytecount_Pos 24 /* TPI FIFO0: ETM_bytecount Position */
#define TPI_FIFO0_ETM_bytecount_Msk (0x3ul << TPI_FIFO0_ETM_bytecount_Pos) /* TPI FIFO0: ETM_bytecount Mask */
#define TPI_FIFO0_ETM2_Pos 16 /* TPI FIFO0: ETM2 Position */
#define TPI_FIFO0_ETM2_Msk (0xfful << TPI_FIFO0_ETM2_Pos) /* TPI FIFO0: ETM2 Mask */
#define TPI_FIFO0_ETM1_Pos 8 /* TPI FIFO0: ETM1 Position */
#define TPI_FIFO0_ETM1_Msk (0xfful << TPI_FIFO0_ETM1_Pos) /* TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0 /* TPI FIFO0: ETM0 Position */
#define TPI_FIFO0_ETM0_Msk (0xfful << TPI_FIFO0_ETM0_Pos) /* TPI FIFO0: ETM0 Mask */
#define TPI_ITATBCTR2_ATREADY_Pos 0 /* TPI ITATBCTR2: ATREADY Position */
#define TPI_ITATBCTR2_ATREADY_Msk (0x1ul << TPI_ITATBCTR2_ATREADY_Pos) /* TPI ITATBCTR2: ATREADY Mask */
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /* TPI FIFO1: ITM_ATVALID Position */
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3ul << TPI_FIFO1_ITM_ATVALID_Pos) /* TPI FIFO1: ITM_ATVALID Mask */
#define TPI_FIFO1_ITM_bytecount_Pos 27 /* TPI FIFO1: ITM_bytecount Position */
#define TPI_FIFO1_ITM_bytecount_Msk (0x3ul << TPI_FIFO1_ITM_bytecount_Pos) /* TPI FIFO1: ITM_bytecount Mask */
#define TPI_FIFO1_ETM_ATVALID_Pos 26 /* TPI FIFO1: ETM_ATVALID Position */
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3ul << TPI_FIFO1_ETM_ATVALID_Pos) /* TPI FIFO1: ETM_ATVALID Mask */
#define TPI_FIFO1_ETM_bytecount_Pos 24 /* TPI FIFO1: ETM_bytecount Position */
#define TPI_FIFO1_ETM_bytecount_Msk (0x3ul << TPI_FIFO1_ETM_bytecount_Pos) /* TPI FIFO1: ETM_bytecount Mask */
#define TPI_FIFO1_ITM2_Pos 16 /* TPI FIFO1: ITM2 Position */
#define TPI_FIFO1_ITM2_Msk (0xfful << TPI_FIFO1_ITM2_Pos) /* TPI FIFO1: ITM2 Mask */
#define TPI_FIFO1_ITM1_Pos 8 /* TPI FIFO1: ITM1 Position */
#define TPI_FIFO1_ITM1_Msk (0xfful << TPI_FIFO1_ITM1_Pos) /* TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0 /* TPI FIFO1: ITM0 Position */
#define TPI_FIFO1_ITM0_Msk (0xfful << TPI_FIFO1_ITM0_Pos) /* TPI FIFO1: ITM0 Mask */
#define TPI_ITATBCTR0_ATREADY_Pos 0 /* TPI ITATBCTR0: ATREADY Position */
#define TPI_ITATBCTR0_ATREADY_Msk (0x1ul << TPI_ITATBCTR0_ATREADY_Pos) /* TPI ITATBCTR0: ATREADY Mask */
#define TPI_ITCTRL_Mode_Pos 0 /* TPI ITCTRL: Mode Position */
#define TPI_ITCTRL_Mode_Msk (0x1ul << TPI_ITCTRL_Mode_Pos) /* TPI ITCTRL: Mode Mask */
#define TPI_DEVID_NRZVALID_Pos 11 /* TPI DEVID: NRZVALID Position */
#define TPI_DEVID_NRZVALID_Msk (0x1ul << TPI_DEVID_NRZVALID_Pos) /* TPI DEVID: NRZVALID Mask */
#define TPI_DEVID_MANCVALID_Pos 10 /* TPI DEVID: MANCVALID Position */
#define TPI_DEVID_MANCVALID_Msk (0x1ul << TPI_DEVID_MANCVALID_Pos) /* TPI DEVID: MANCVALID Mask */
#define TPI_DEVID_PTINVALID_Pos 9 /* TPI DEVID: PTINVALID Position */
#define TPI_DEVID_PTINVALID_Msk (0x1ul << TPI_DEVID_PTINVALID_Pos) /* TPI DEVID: PTINVALID Mask */
#define TPI_DEVID_MinBufSz_Pos 6 /* TPI DEVID: MinBufSz Position */
#define TPI_DEVID_MinBufSz_Msk (0x7ul << TPI_DEVID_MinBufSz_Pos) /* TPI DEVID: MinBufSz Mask */
#define TPI_DEVID_AsynClkIn_Pos 5 /* TPI DEVID: AsynClkIn Position */
#define TPI_DEVID_AsynClkIn_Msk (0x1ul << TPI_DEVID_AsynClkIn_Pos) /* TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0 /* TPI DEVID: NrTraceInput Position */
#define TPI_DEVID_NrTraceInput_Msk (0x1ful << TPI_DEVID_NrTraceInput_Pos) /* TPI DEVID: NrTraceInput Mask */
#define TPI_DEVTYPE_SubType_Pos 0 /* TPI DEVTYPE: SubType Position */
#define TPI_DEVTYPE_SubType_Msk (0xful << TPI_DEVTYPE_SubType_Pos) /* TPI DEVTYPE: SubType Mask */
#define TPI_DEVTYPE_MajorType_Pos 4 /* TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xful << TPI_DEVTYPE_MajorType_Pos) /* TPI DEVTYPE: MajorType Mask */
#endif /* __ARCH_ARM_SRC_ARMV7_M_TPI_H */