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configs/metro-m4: Verify the CMCC and enable it by default in the NSH configuration.

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This commit is contained in:
Gregory Nutt 2018-09-01 17:03:31 -06:00
parent f66869b793
commit 9f6383e5fd
5 changed files with 20 additions and 30 deletions
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4
arch/arm/src/samd5e5/Make.defs
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@ -87,8 +87,8 @@ endif
# Required SAMD5x/E5x files
CHIP_ASRCS =
CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c
CHIP_CSRCS = sam_clockconfig.c sam_gclk.c sam_irq.c sam_lowputc.c
CHIP_CSRCS += sam_port.c sam_serial.c sam_start.c sam_usart.c
# Configuration-dependent SAMD5x/E5x files

11
arch/arm/src/samd5e5/sam_start.c
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@ -345,18 +345,13 @@ void __start(void)
showprogress('C');
#endif
/* Initialize onboard resources */
/* Initialize on-board resources */
sam_board_initialize();
showprogress('D');
#ifdef CONFIG_SAM34_CMCC
/* Enable the Cortex-M Cache
*
* REVISIT: This logic is complete but I have not yet tried to enable it.
* I have some questions about how the cache will effect memory mapped
* register accesses.
*/
#ifdef CONFIG_SAMD5E5_CMCC
/* Enable the Cortex-M Cache Controller (CMCC) */
sam_cmcc_enable();
#endif

16
arch/arm/src/samd5e5/sam_timerisr.c
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@ -117,23 +117,11 @@ void arm_timer_initialize(void)
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SysTick clock source is set correctly */
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#ifdef CONFIG_SAM34_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
#endif
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
@ -143,7 +131,7 @@ void arm_timer_initialize(void)
(void)irq_attach(SAM_IRQ_SYSTICK, (xcpt_t)sam_timerisr, NULL);
/* Enable SysTick interrupts */
/* Enable SysTick interrupts using the processor clock source. */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);

16
configs/metro-m4/README.txt
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@ -124,11 +124,11 @@ STATUS
There are additional drivers ported from SAML21 which has, in most cases,
identical peripherals. None of these drivers have been verified on the
SAMD51, However. These include: CMCC, DMAC, I2C, SPI, and USB.
SAMD51, However. These include: DMAC, I2C, SPI, and USB.
The delay loop has not yet been calibrated. no sense in doing that
because the CMCC should improve performance dramatically when it is
integrated.
The timer interrupt appears to be running too fast. From the NSH console,
I see that sleep 5 seems to take about 1 second, sleep 10 seems to take
about 2 seconds.
Unlocking FLASH
===============
@ -342,4 +342,10 @@ Configuration sub-directories
-----------------------------
nsh:
This configuration directory will built the NuttShell. See NOTES above.
This configuration directory will built the NuttShell. See NOTES ;for
common configuration above and the following:
NOTES:
1. The CMCC (Cortex M Cache Controller) is enabled.

3
configs/metro-m4/nsh/defconfig
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@ -6,7 +6,7 @@ CONFIG_ARCH_BOARD_METRO_M4=y
CONFIG_ARCH_CHIP_SAMD51J19=y
CONFIG_ARCH_CHIP_SAMD5X=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_BOARD_LOOPSPERMSEC=4316
CONFIG_BOARD_LOOPSPERMSEC=7225
CONFIG_BUILTIN=y
CONFIG_DISABLE_ENVIRON=y
CONFIG_DISABLE_POLL=y
@ -28,6 +28,7 @@ CONFIG_RAM_SIZE=196608
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SAMD5E5_CMCC=y
CONFIG_SAMD5E5_EIC=y
CONFIG_SAMD5E5_SERCOM3=y
CONFIG_SCHED_WAITPID=y