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PIC32MZ Ethernet: Enable PBCLK5 and MII divider for PHY. From Kistopher Tate

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This commit is contained in:
Gregory Nutt 2015-03-29 07:14:09 -06:00
parent d85f3dd530
commit 9f70633dac
1 changed files with 14 additions and 1 deletions
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15
configs/pic32mz-starterkit/include/board.h
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@ -136,7 +136,10 @@
* FRC clock is used for programming
*/
#undef BOARD_PBCLK5_ENABLE
#define BOARD_PBCLK5_ENABLE 1 /* Enable PBCLK5 */
#define BOARD_PB5DIV 2 /* Divider = 2 */
#define BOARD_PBCLK5 100000000 /* PBCLK5 frequency = 200MHz/2 = 100MHz */
/* PBCLK6
* Peripherals:
@ -160,6 +163,16 @@
#define BOARD_WD_PRESCALER 1048576 /* Watchdog pre-scaler */
/* Ethernet MII clocking.
*
* The clock divider used to create the MII Management Clock (MDC). The MIIM
* module uses the PBCLK5 as an input clock. According to the IEEE 802.3
* Specification this should be no faster than 2.5 MHz. However, some PHYs
* support clock rates up to 12.5 MHz.
*/
#define BOARD_EMAC_MIIM_DIV 40 /* Ideal: 100MHz/40 = 2.5MHz */
/* LED definitions **********************************************************/
/* LED Configuration ********************************************************/
/* The PIC32MZ Ethernet Starter kit has 3 user LEDs labelled LED1-3 on the