SAMD21: Update PM definitions for SAMD21 support
This commit is contained in:
Gregory Nutt
parent
62973af6eb
commit
9fc91cfa5a
@ -48,7 +48,7 @@
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
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/********************************************************************************************
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* Pre-processor Definitions
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@ -98,9 +98,9 @@
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#define PM_SLEEP_IDLE_SHIFT (0) /* Bits 0-1: Idle Mode Configuration */
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#define PM_SLEEP_IDLE_MASK (3 << PM_SLEEP_IDLE_SHIFT)
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#define PM_SLEEP_IDLE_CPU (0 << PM_SLEEP_IDLE_SHIFT) /* CPU clock domain stopped */
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#define PM_SLEEP_IDLE_CPUAHB (1 << PM_SLEEP_IDLE_SHIFT) /* CPU and AHB clock domains stopped */
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#define PM_SLEEP_IDLE_CPUAHBAPB (2 << PM_SLEEP_IDLE_SHIFT) /* CPU, AHB and APB clock domains stopped */
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# define PM_SLEEP_IDLE_CPU (0 << PM_SLEEP_IDLE_SHIFT) /* CPU clock domain stopped */
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# define PM_SLEEP_IDLE_CPUAHB (1 << PM_SLEEP_IDLE_SHIFT) /* CPU and AHB clock domains stopped */
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# define PM_SLEEP_IDLE_CPUAHBAPB (2 << PM_SLEEP_IDLE_SHIFT) /* CPU, AHB, and APB clock domains stopped */
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/* CPU clock select register */
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@ -162,6 +162,11 @@
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#define PM_AHBMASK_DSU (1 << 3) /* Bit 3: DSU */
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#define PM_AHBMASK_NVMCTRL (1 << 4) /* Bit 4: NVMCTRL */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define PM_AHBMASK_DMAC (1 << 5) /* Bit 4: DMA controller */
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# define PM_AHBMASK_USB (1 << 6) /* Bit 4: USB */
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#endif
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/* APBA mask register */
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#define PM_APBAMASK_PAC0 (1 << 0) /* Bit 0: PAC0 */
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@ -179,6 +184,11 @@
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#define PM_APBBMASK_NVMCTRL (1 << 2) /* Bit 2: NVMCTRL */
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#define PM_APBBMASK_PORT (1 << 3) /* Bit 3: PORT */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define PM_APBBMASK_DMAC (1 << 4) /* Bit 4: DMA controller */
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# define PM_APBBMASK_USB (1 << 5) /* Bit 5: USB */
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#endif
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/* APBC mask register */
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#define PM_APBCMASK_PAC2 (1 << 0) /* Bit 0: PAC2 */
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@ -189,10 +199,20 @@
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# define PM_APBCMASK_SERCOM2 (1 << 4) /* Bit 4: SERCOM2 */
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# define PM_APBCMASK_SERCOM3 (1 << 5) /* Bit 5: SERCOM3 */
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# define PM_APBCMASK_SERCOM4 (1 << 6) /* Bit 6: SERCOM4 */
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#define PM_APBCMASK_SERCOM5 (1 << 7) /* Bit 7: SERCOM5 */
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#define PM_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 */
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#define PM_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 */
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#define PM_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 */
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# define PM_APBCMASK_SERCOM5 (1 << 7) /* Bit 7: SERCOM5 */
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define PM_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 */
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# define PM_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 */
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# define PM_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 */
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define PM_APBCMASK_TCC0 (1 << 8) /* Bit 8: TCC0 */
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# define PM_APBCMASK_TCC1 (1 << 9) /* Bit 9: TCC1 */
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# define PM_APBCMASK_TCC2 (1 << 10) /* Bit 10: TCC2 */
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#endif
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#define PM_APBCMASK_TC3 (1 << 11) /* Bit 11: TC3 */
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#define PM_APBCMASK_TC4 (1 << 12) /* Bit 12: TC4 */
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#define PM_APBCMASK_TC5 (1 << 13) /* Bit 13: TC5 */
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@ -203,10 +223,17 @@
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#define PM_APBCMASK_DAC (1 << 18) /* Bit 18: DAC */
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#define PM_APBCMASK_PTC (1 << 19) /* Bit 19: PTC */
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define PM_APBBMASK_I2S (1 << 10) /* Bit 20: Inter IC Sound */
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#endif
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/* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */
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#define PM_INT_CKRDY (1 << 0) /* Bit 0: Clock Ready Interrupt */
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#define PM_INT_CFD (1 << 1) /* Bit 1: Clock Failure Detector Interrupt */
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define PM_INT_CFD (1 << 1) /* Bit 1: Clock Failure Detector Interrupt */
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#endif
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/* Reset cause register */
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@ -229,5 +256,5 @@
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_PM_H */
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@ -44,7 +44,7 @@
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#include "chip/samd_pm.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
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/****************************************************************************
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* Pre-processor Definitions
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@ -67,6 +67,11 @@
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#define sam_nvmctrl_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_NVMCTRL)
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#define sam_port_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_PORT)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_dmac_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_DMAC)
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# define sam_usb_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_USB)
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#endif
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#define sam_apbc_enableperiph(s) modifyreg32(SAM_PM_APBCMASK,0,s)
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#define sam_pac2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PAC2)
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@ -78,9 +83,19 @@
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#define sam_sercom3_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM3)
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#define sam_sercom4_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM4)
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#define sam_sercom5_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM5)
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#define sam_tc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC0)
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#define sam_tc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC1)
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#define sam_tc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC2)
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define sam_tc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC0)
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# define sam_tc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC1)
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# define sam_tc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC2)
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_tcc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TCC0)
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# define sam_tcc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TCC1)
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# define sam_tcc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TCC2)
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#endif
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#define sam_tc3_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC3)
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#define sam_tc4_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC4)
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#define sam_tc5_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC5)
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@ -91,6 +106,10 @@
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#define sam_dac_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_DAC)
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#define sam_ptc_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PTC)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_i2s_enableperiph() sam_apbc_enableperiph(PM_APBBMASK_I2S)
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#endif
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#define sam_apba_disableperiph(s) modifyreg32(SAM_PM_APBAMASK,s,0)
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#define sam_pac0_disableperiph() sam_apba_disableperiph(PM_APBAMASK_PAC0)
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@ -108,6 +127,11 @@
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#define sam_nvmctrl_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_NVMCTRL)
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#define sam_port_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_PORT)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_dmac_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_DMAC)
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# define sam_usb_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_USB)
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#endif
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#define sam_apbc_disableperiph(s) modifyreg32(SAM_PM_APBCMASK,s,0)
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#define sam_pac2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PAC2)
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@ -119,9 +143,19 @@
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#define sam_sercom3_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM3)
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#define sam_sercom4_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM4)
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#define sam_sercom5_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM5)
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#define sam_tc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC0)
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#define sam_tc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC1)
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#define sam_tc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC2)
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define sam_tc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC0)
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# define sam_tc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC1)
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# define sam_tc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC2)
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_tcc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TCC0)
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# define sam_tcc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TCC1)
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# define sam_tcc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TCC2)
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#endif
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#define sam_tc3_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC3)
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#define sam_tc4_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC4)
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#define sam_tc5_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC5)
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@ -132,6 +166,10 @@
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#define sam_dac_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_DAC)
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#define sam_ptc_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PTC)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_i2s_disableperiph() sam_apbc_disableperiph(PM_APBBMASK_I2S)
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#endif
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#define sam_apba_isenabled(s) (getreg32(SAM_PM_APBAMASK) & (s)) != 0)
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#define sam_pac0_isenabled() sam_apba_isenabled(PM_APBAMASK_PAC0)
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@ -149,6 +187,11 @@
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#define sam_nvmctrl_isenabled() sam_apbb_isenabled(PM_APBBMASK_NVMCTRL)
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#define sam_port_isenabled() sam_apbb_isenabled(PM_APBBMASK_PORT)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_dmac_isenabled() sam_apbb_isenabled(PM_APBBMASK_DMAC)
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# define sam_usb_isenabled() sam_apbb_isenabled(PM_APBBMASK_USB)
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#endif
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#define sam_apbc_isenabled(s) (getreg32(SAM_PM_APBCMASK) & (s)) != 0)
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#define sam_pac2_isenabled() sam_apbc_isenabled(PM_APBCMASK_PAC2)
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@ -160,9 +203,19 @@
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#define sam_sercom3_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM3)
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#define sam_sercom4_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM4)
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#define sam_sercom5_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM5)
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#define sam_tc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC0)
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#define sam_tc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC1)
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#define sam_tc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC2)
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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# define sam_tc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC0)
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# define sam_tc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC1)
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# define sam_tc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC2)
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_tcc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TCC0)
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# define sam_tcc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TCC1)
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# define sam_tcc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TCC2)
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#endif
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#define sam_tc3_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC3)
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#define sam_tc4_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC4)
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#define sam_tc5_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC5)
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@ -173,6 +226,10 @@
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#define sam_dac_isenabled() sam_apbc_isenabled(PM_APBCMASK_DAC)
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#define sam_ptc_isenabled() sam_apbc_isenabled(PM_APBCMASK_PTC)
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define sam_i2s_isenabled() sam_apbc_isenabled(PM_APBBMASK_I2S)
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#endif
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -205,5 +262,5 @@ extern "C"
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_SAMD_PERIPHCLKS_H */
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