From 9fc91cfa5ae462968af09d9c59c5b4c666511c96 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 20 Jun 2015 15:32:57 -0600 Subject: [PATCH] SAMD21: Update PM definitions for SAMD21 support --- arch/arm/src/samdl/chip/samd_pm.h | 47 +++++++++++++---- arch/arm/src/samdl/samd_periphclks.h | 79 ++++++++++++++++++++++++---- 2 files changed, 105 insertions(+), 21 deletions(-) diff --git a/arch/arm/src/samdl/chip/samd_pm.h b/arch/arm/src/samdl/chip/samd_pm.h index 36c82fe0c1..066eef5279 100644 --- a/arch/arm/src/samdl/chip/samd_pm.h +++ b/arch/arm/src/samdl/chip/samd_pm.h @@ -48,7 +48,7 @@ #include "chip.h" -#ifdef CONFIG_ARCH_FAMILY_SAMD20 +#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) /******************************************************************************************** * Pre-processor Definitions @@ -98,9 +98,9 @@ #define PM_SLEEP_IDLE_SHIFT (0) /* Bits 0-1: Idle Mode Configuration */ #define PM_SLEEP_IDLE_MASK (3 << PM_SLEEP_IDLE_SHIFT) -#define PM_SLEEP_IDLE_CPU (0 << PM_SLEEP_IDLE_SHIFT) /* CPU clock domain stopped */ -#define PM_SLEEP_IDLE_CPUAHB (1 << PM_SLEEP_IDLE_SHIFT) /* CPU and AHB clock domains stopped */ -#define PM_SLEEP_IDLE_CPUAHBAPB (2 << PM_SLEEP_IDLE_SHIFT) /* CPU, AHB and APB clock domains stopped */ +# define PM_SLEEP_IDLE_CPU (0 << PM_SLEEP_IDLE_SHIFT) /* CPU clock domain stopped */ +# define PM_SLEEP_IDLE_CPUAHB (1 << PM_SLEEP_IDLE_SHIFT) /* CPU and AHB clock domains stopped */ +# define PM_SLEEP_IDLE_CPUAHBAPB (2 << PM_SLEEP_IDLE_SHIFT) /* CPU, AHB, and APB clock domains stopped */ /* CPU clock select register */ @@ -162,6 +162,11 @@ #define PM_AHBMASK_DSU (1 << 3) /* Bit 3: DSU */ #define PM_AHBMASK_NVMCTRL (1 << 4) /* Bit 4: NVMCTRL */ +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define PM_AHBMASK_DMAC (1 << 5) /* Bit 4: DMA controller */ +# define PM_AHBMASK_USB (1 << 6) /* Bit 4: USB */ +#endif + /* APBA mask register */ #define PM_APBAMASK_PAC0 (1 << 0) /* Bit 0: PAC0 */ @@ -179,6 +184,11 @@ #define PM_APBBMASK_NVMCTRL (1 << 2) /* Bit 2: NVMCTRL */ #define PM_APBBMASK_PORT (1 << 3) /* Bit 3: PORT */ +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define PM_APBBMASK_DMAC (1 << 4) /* Bit 4: DMA controller */ +# define PM_APBBMASK_USB (1 << 5) /* Bit 5: USB */ +#endif + /* APBC mask register */ #define PM_APBCMASK_PAC2 (1 << 0) /* Bit 0: PAC2 */ @@ -189,10 +199,20 @@ # define PM_APBCMASK_SERCOM2 (1 << 4) /* Bit 4: SERCOM2 */ # define PM_APBCMASK_SERCOM3 (1 << 5) /* Bit 5: SERCOM3 */ # define PM_APBCMASK_SERCOM4 (1 << 6) /* Bit 6: SERCOM4 */ -#define PM_APBCMASK_SERCOM5 (1 << 7) /* Bit 7: SERCOM5 */ -#define PM_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 */ -#define PM_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 */ -#define PM_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 */ +# define PM_APBCMASK_SERCOM5 (1 << 7) /* Bit 7: SERCOM5 */ + +#ifdef CONFIG_ARCH_FAMILY_SAMD20 +# define PM_APBCMASK_TC0 (1 << 8) /* Bit 8: TC0 */ +# define PM_APBCMASK_TC1 (1 << 9) /* Bit 9: TC1 */ +# define PM_APBCMASK_TC2 (1 << 10) /* Bit 10: TC2 */ +#endif + +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define PM_APBCMASK_TCC0 (1 << 8) /* Bit 8: TCC0 */ +# define PM_APBCMASK_TCC1 (1 << 9) /* Bit 9: TCC1 */ +# define PM_APBCMASK_TCC2 (1 << 10) /* Bit 10: TCC2 */ +#endif + #define PM_APBCMASK_TC3 (1 << 11) /* Bit 11: TC3 */ #define PM_APBCMASK_TC4 (1 << 12) /* Bit 12: TC4 */ #define PM_APBCMASK_TC5 (1 << 13) /* Bit 13: TC5 */ @@ -203,10 +223,17 @@ #define PM_APBCMASK_DAC (1 << 18) /* Bit 18: DAC */ #define PM_APBCMASK_PTC (1 << 19) /* Bit 19: PTC */ +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define PM_APBBMASK_I2S (1 << 10) /* Bit 20: Inter IC Sound */ +#endif + /* Interrupt enable clear, Interrupt enable set, and Interrupt flag status and clear registers */ #define PM_INT_CKRDY (1 << 0) /* Bit 0: Clock Ready Interrupt */ -#define PM_INT_CFD (1 << 1) /* Bit 1: Clock Failure Detector Interrupt */ + +#ifdef CONFIG_ARCH_FAMILY_SAMD20 +# define PM_INT_CFD (1 << 1) /* Bit 1: Clock Failure Detector Interrupt */ +#endif /* Reset cause register */ @@ -229,5 +256,5 @@ * Public Functions ********************************************************************************************/ -#endif /* CONFIG_ARCH_FAMILY_SAMD20 */ +#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_PM_H */ diff --git a/arch/arm/src/samdl/samd_periphclks.h b/arch/arm/src/samdl/samd_periphclks.h index b4b4da412b..0ba3df0f87 100644 --- a/arch/arm/src/samdl/samd_periphclks.h +++ b/arch/arm/src/samdl/samd_periphclks.h @@ -44,7 +44,7 @@ #include "chip/samd_pm.h" -#ifdef CONFIG_ARCH_FAMILY_SAMD20 +#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21) /**************************************************************************** * Pre-processor Definitions @@ -67,6 +67,11 @@ #define sam_nvmctrl_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_NVMCTRL) #define sam_port_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_PORT) +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_dmac_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_DMAC) +# define sam_usb_enableperiph() sam_apbb_enableperiph(PM_APBBMASK_USB) +#endif + #define sam_apbc_enableperiph(s) modifyreg32(SAM_PM_APBCMASK,0,s) #define sam_pac2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PAC2) @@ -78,9 +83,19 @@ #define sam_sercom3_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM3) #define sam_sercom4_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM4) #define sam_sercom5_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_SERCOM5) -#define sam_tc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC0) -#define sam_tc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC1) -#define sam_tc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC2) + +#ifdef CONFIG_ARCH_FAMILY_SAMD20 +# define sam_tc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC0) +# define sam_tc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC1) +# define sam_tc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC2) +#endif + +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_tcc0_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TCC0) +# define sam_tcc1_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TCC1) +# define sam_tcc2_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TCC2) +#endif + #define sam_tc3_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC3) #define sam_tc4_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC4) #define sam_tc5_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_TC5) @@ -91,6 +106,10 @@ #define sam_dac_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_DAC) #define sam_ptc_enableperiph() sam_apbc_enableperiph(PM_APBCMASK_PTC) +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_i2s_enableperiph() sam_apbc_enableperiph(PM_APBBMASK_I2S) +#endif + #define sam_apba_disableperiph(s) modifyreg32(SAM_PM_APBAMASK,s,0) #define sam_pac0_disableperiph() sam_apba_disableperiph(PM_APBAMASK_PAC0) @@ -108,6 +127,11 @@ #define sam_nvmctrl_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_NVMCTRL) #define sam_port_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_PORT) +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_dmac_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_DMAC) +# define sam_usb_disableperiph() sam_apbb_disableperiph(PM_APBBMASK_USB) +#endif + #define sam_apbc_disableperiph(s) modifyreg32(SAM_PM_APBCMASK,s,0) #define sam_pac2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PAC2) @@ -119,9 +143,19 @@ #define sam_sercom3_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM3) #define sam_sercom4_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM4) #define sam_sercom5_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_SERCOM5) -#define sam_tc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC0) -#define sam_tc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC1) -#define sam_tc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC2) + +#ifdef CONFIG_ARCH_FAMILY_SAMD20 +# define sam_tc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC0) +# define sam_tc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC1) +# define sam_tc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC2) +#endif + +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_tcc0_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TCC0) +# define sam_tcc1_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TCC1) +# define sam_tcc2_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TCC2) +#endif + #define sam_tc3_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC3) #define sam_tc4_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC4) #define sam_tc5_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_TC5) @@ -132,6 +166,10 @@ #define sam_dac_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_DAC) #define sam_ptc_disableperiph() sam_apbc_disableperiph(PM_APBCMASK_PTC) +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_i2s_disableperiph() sam_apbc_disableperiph(PM_APBBMASK_I2S) +#endif + #define sam_apba_isenabled(s) (getreg32(SAM_PM_APBAMASK) & (s)) != 0) #define sam_pac0_isenabled() sam_apba_isenabled(PM_APBAMASK_PAC0) @@ -149,6 +187,11 @@ #define sam_nvmctrl_isenabled() sam_apbb_isenabled(PM_APBBMASK_NVMCTRL) #define sam_port_isenabled() sam_apbb_isenabled(PM_APBBMASK_PORT) +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_dmac_isenabled() sam_apbb_isenabled(PM_APBBMASK_DMAC) +# define sam_usb_isenabled() sam_apbb_isenabled(PM_APBBMASK_USB) +#endif + #define sam_apbc_isenabled(s) (getreg32(SAM_PM_APBCMASK) & (s)) != 0) #define sam_pac2_isenabled() sam_apbc_isenabled(PM_APBCMASK_PAC2) @@ -160,9 +203,19 @@ #define sam_sercom3_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM3) #define sam_sercom4_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM4) #define sam_sercom5_isenabled() sam_apbc_isenabled(PM_APBCMASK_SERCOM5) -#define sam_tc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC0) -#define sam_tc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC1) -#define sam_tc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC2) + +#ifdef CONFIG_ARCH_FAMILY_SAMD20 +# define sam_tc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC0) +# define sam_tc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC1) +# define sam_tc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC2) +#endif + +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_tcc0_isenabled() sam_apbc_isenabled(PM_APBCMASK_TCC0) +# define sam_tcc1_isenabled() sam_apbc_isenabled(PM_APBCMASK_TCC1) +# define sam_tcc2_isenabled() sam_apbc_isenabled(PM_APBCMASK_TCC2) +#endif + #define sam_tc3_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC3) #define sam_tc4_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC4) #define sam_tc5_isenabled() sam_apbc_isenabled(PM_APBCMASK_TC5) @@ -173,6 +226,10 @@ #define sam_dac_isenabled() sam_apbc_isenabled(PM_APBCMASK_DAC) #define sam_ptc_isenabled() sam_apbc_isenabled(PM_APBCMASK_PTC) +#ifdef CONFIG_ARCH_FAMILY_SAMD21 +# define sam_i2s_isenabled() sam_apbc_isenabled(PM_APBBMASK_I2S) +#endif + /**************************************************************************** * Public Types ****************************************************************************/ @@ -205,5 +262,5 @@ extern "C" } #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_ARCH_FAMILY_SAMD20 */ +#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */ #endif /* __ARCH_ARM_SRC_SAMDL_SAMD_PERIPHCLKS_H */