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arch: spi: fix typos and run nxstyle

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Signed-off-by: Juha Niskanen <juha.niskanen@haltian.com>
This commit is contained in:
Juha Niskanen 2020-10-31 17:47:57 +02:00 committed by Xiang Xiao
parent 77bbb07749
commit a01a01ab45
18 changed files with 108 additions and 64 deletions
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8
arch/arm/src/efm32/efm32_spi.c
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@ -1044,8 +1044,8 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
regval |= setting; regval |= setting;
spi_putreg(config, EFM32_USART_FRAME_OFFSET, regval); spi_putreg(config, EFM32_USART_FRAME_OFFSET, regval);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster * faster.
*/ */
priv->nbits = nbits; priv->nbits = nbits;
@ -1105,8 +1105,8 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev,
spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval); spi_putreg(config, EFM32_USART_CTRL_OFFSET, regval);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster * faster.
*/ */
priv->lsbfirst = lsbfirst; priv->lsbfirst = lsbfirst;

2
arch/arm/src/kinetis/kinetis_spi.c
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@ -813,7 +813,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CTARM_FMSZ(nbits - 1); regval |= SPI_CTARM_FMSZ(nbits - 1);
spi_putreg(priv, priv->ctarsel, regval); spi_putreg(priv, priv->ctarsel, regval);
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be faster. */
priv->nbits = nbits; priv->nbits = nbits;
} }

6
arch/arm/src/kl/kl_spi.c
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@ -284,7 +284,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
unsigned int spr; unsigned int spr;
unsigned int sppr; unsigned int sppr;
/* Check if the requested frequence is the same as the frequency selection */ /* Check if the requested frequence is the same as the frequency
* selection.
*/
if (priv->frequency == frequency) if (priv->frequency == frequency)
{ {
@ -410,7 +412,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
spi_putreg(priv, KL_SPI_C1_OFFSET, regval); spi_putreg(priv, KL_SPI_C1_OFFSET, regval);
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }

14
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
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@ -228,10 +228,12 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t divisor; uint32_t divisor;
uint32_t actual; uint32_t actual;
/* Check if the requested frequence is the same as the frequency selection */
DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2); DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
/* Check if the requested frequence is the same as the frequency
* selection.
*/
if (priv->frequency == frequency) if (priv->frequency == frequency)
{ {
/* We are already at this frequency. Return the actual. */ /* We are already at this frequency. Return the actual. */
@ -328,7 +330,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
putreg32(regval, LPC17_40_SPI_CR); putreg32(regval, LPC17_40_SPI_CR);
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }
@ -342,7 +344,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -368,7 +370,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CR_BITENABLE; regval |= SPI_CR_BITENABLE;
regval = getreg32(LPC17_40_SPI_CR); regval = getreg32(LPC17_40_SPI_CR);
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be
* faster.
*/
priv->nbits = nbits; priv->nbits = nbits;
} }

20
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
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@ -385,10 +385,12 @@ static uint32_t ssp_setfrequency(FAR struct spi_dev_s *dev,
uint32_t regval; uint32_t regval;
uint32_t actual; uint32_t actual;
/* Check if the requested frequency is the same as the frequency selection */
DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2); DEBUGASSERT(priv && frequency <= SSP_CLOCK / 2);
/* Check if the requested frequency is the same as the frequency
* selection.
*/
if (priv->frequency == frequency) if (priv->frequency == frequency)
{ {
/* We are already at this frequency. Return the actual. */ /* We are already at this frequency. Return the actual. */
@ -533,7 +535,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -558,7 +560,9 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT); regval |= ((nbits - 1) << SSP_CR0_DSS_SHIFT);
ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, regval); ssp_putreg(priv, LPC17_40_SSP_CR0_OFFSET, regval);
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be
* faster.
*/
priv->nbits = nbits; priv->nbits = nbits;
} }
@ -731,7 +735,9 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
uint32_t data; uint32_t data;
uint32_t rxpending = 0; uint32_t rxpending = 0;
/* While there is remaining to be sent (and no synchronization error has occurred) */ /* While there is remaining to be sent (and no synchronization error
* has occurred)
*/
spiinfo("nwords: %d\n", nwords); spiinfo("nwords: %d\n", nwords);
u.pv = buffer; u.pv = buffer;
@ -752,7 +758,9 @@ static void ssp_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer,
rxpending++; rxpending++;
} }
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */ /* Now, read the RX data from the RX FIFO while the RX FIFO is
* not empty.
*/
spiinfo("RX: rxpending: %d\n", rxpending); spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE) while (ssp_getreg(priv, LPC17_40_SSP_SR_OFFSET) & SSP_SR_RNE)

16
arch/arm/src/lpc2378/lpc23xx_spi.c
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@ -234,7 +234,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
DEBUGASSERT(frequency <= SPI_CLOCK / 2); DEBUGASSERT(frequency <= SPI_CLOCK / 2);
/* Check if the requested frequency is the same as the frequency selection */ /* Check if the requested frequency is the same as the frequency
* selection.
*/
DEBUGASSERT(priv != NULL); DEBUGASSERT(priv != NULL);
if (priv->frequency == frequency) if (priv->frequency == frequency)
@ -248,7 +250,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
divisor = SPI_CLOCK / frequency; divisor = SPI_CLOCK / frequency;
/* The SPI CCR register must contain an even number greater than or equal to 8. */ /* The SPI CCR register must contain an even number greater than or equal
* to 8.
*/
if (divisor < 8) if (divisor < 8)
{ {
@ -332,7 +336,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
putreg32(regval, SPI_CR); putreg32(regval, SPI_CR);
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }
@ -346,7 +350,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -373,7 +377,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CR_BITENABLE; regval |= SPI_CR_BITENABLE;
putreg32(regval, SPI_CR); putreg32(regval, SPI_CR);
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be
* faster.
*/
priv->nbits = nbits; priv->nbits = nbits;
} }

16
arch/arm/src/lpc43xx/lpc43_spi.c
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@ -219,7 +219,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
uint32_t divisor; uint32_t divisor;
uint32_t actual; uint32_t actual;
/* Check if the requested frequence is the same as the frequency selection */ /* Check if the requested frequence is the same as the frequency
* selection.
*/
DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2); DEBUGASSERT(priv && frequency <= SPI_CLOCK / 2);
@ -234,7 +236,9 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
divisor = SPI_CLOCK / frequency; divisor = SPI_CLOCK / frequency;
/* The SPI CCR register must contain an even number greater than or equal to 8. */ /* The SPI CCR register must contain an even number greater than or equal
* to 8.
*/
if (divisor < 8) if (divisor < 8)
{ {
@ -317,7 +321,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
putreg32(regval, LPC43_SPI_CR); putreg32(regval, LPC43_SPI_CR);
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }
@ -331,7 +335,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -357,7 +361,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= SPI_CR_BITENABLE; regval |= SPI_CR_BITENABLE;
regval = getreg32(LPC43_SPI_CR); regval = getreg32(LPC43_SPI_CR);
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be
* faster.
*/
priv->nbits = nbits; priv->nbits = nbits;
} }

18
arch/arm/src/lpc43xx/lpc43_ssp.c
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@ -432,7 +432,7 @@ static void ssp_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -461,7 +461,9 @@ static void ssp_setbits(FAR struct spi_dev_s *dev, int nbits)
spiinfo("SSP Control Register 0 (CR0) after setting" spiinfo("SSP Control Register 0 (CR0) after setting"
"DSS: 0x%08X.\n", regval); "DSS: 0x%08X.\n", regval);
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be
* faster.
*/
priv->nbits = nbits; priv->nbits = nbits;
} }
@ -550,7 +552,9 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
uint32_t datadummy = (priv->nbits > 8) ? 0xffff : 0xff; uint32_t datadummy = (priv->nbits > 8) ? 0xffff : 0xff;
uint32_t rxpending = 0; uint32_t rxpending = 0;
/* While there is remaining to be sent (and no synchronization error has occurred) */ /* While there is remaining to be sent (and no synchronization error
* has occurred)
*/
spiinfo("nwords: %d\n", nwords); spiinfo("nwords: %d\n", nwords);
@ -585,7 +589,9 @@ static void ssp_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
rxpending++; rxpending++;
} }
/* Now, read the RX data from the RX FIFO while the RX FIFO is not empty */ /* Now, read the RX data from the RX FIFO while the RX FIFO is not
* empty.
*/
spiinfo("RX: rxpending: %d\n", rxpending); spiinfo("RX: rxpending: %d\n", rxpending);
while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE) while (ssp_getreg(priv, LPC43_SSP_SR_OFFSET) & SSP_SR_RNE)
@ -759,7 +765,9 @@ static inline FAR struct lpc43_sspdev_s *lpc43_ssp1initialize(void)
/* Pins configuration */ /* Pins configuration */
#ifdef PINCONF_SSP1_SCK #ifdef PINCONF_SSP1_SCK
/* It is possible this is not configured if CLK0 is being used for clocking SPI */ /* It is possible this is not configured if CLK0 is being used for
* clocking SPI.
*/
lpc43_pin_config(PINCONF_SSP1_SCK); lpc43_pin_config(PINCONF_SSP1_SCK);
#endif #endif

14
arch/arm/src/max326xx/max32660/max32660_spim.c
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@ -708,7 +708,9 @@ static int spi_poll(struct max326_spidev_s *priv)
inten |= SPI_INT_RXLEVEL; inten |= SPI_INT_RXLEVEL;
} }
/* Break out if we've received all the bytes and we're not transmitting */ /* Break out if we've received all the bytes and we're not
* transmitting.
*/
if (priv->txbuffer == NULL && priv->rxbytes == length) if (priv->txbuffer == NULL && priv->rxbytes == length)
{ {
@ -716,7 +718,7 @@ static int spi_poll(struct max326_spidev_s *priv)
} }
} }
/* Break out once we've transmitted and received all of the data */ /* Break out once we've transmitted and received all of the data. */
if (priv->rxbytes == length && priv->txbytes == length) if (priv->rxbytes == length && priv->txbytes == length)
{ {
@ -1080,7 +1082,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode)
spi_modify_ctrl2(priv, setbits, clrbits); spi_modify_ctrl2(priv, setbits, clrbits);
/* Save the mode so that subsequent re-configurations will be faster */ /* Save the mode so that subsequent re-configurations will be
* faster.
*/
priv->mode = mode; priv->mode = mode;
} }
@ -1121,8 +1125,8 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
priv->data16 = (nbits > 8); priv->data16 = (nbits > 8);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster * faster.
*/ */
priv->nbits = nbits; priv->nbits = nbits;

6
arch/arm/src/samv7/sam_qspi.c
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@ -1281,7 +1281,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -1310,8 +1310,8 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits)
spiinfo("MR=%08x\n", regval); spiinfo("MR=%08x\n", regval);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster * faster.
*/ */
priv->nbits = nbits; priv->nbits = nbits;

6
arch/arm/src/samv7/sam_spi_slave.c
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@ -703,7 +703,7 @@ static void spi_setmode(struct sam_spidev_s *priv, enum spi_smode_e mode)
* *
* Input Parameters: * Input Parameters:
* priv - SPI device data structure * priv - SPI device data structure
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -730,8 +730,8 @@ static void spi_setbits(struct sam_spidev_s *priv, int nbits)
spiinfo("csr0=%08x\n", regval); spiinfo("csr0=%08x\n", regval);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster * faster.
*/ */
priv->nbits = nbits; priv->nbits = nbits;

6
arch/arm/src/stm32/stm32_spi.c
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@ -1520,7 +1520,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_modifycr1(priv, setbits, clrbits); spi_modifycr1(priv, setbits, clrbits);
spi_modifycr1(priv, SPI_CR1_SPE, 0); spi_modifycr1(priv, SPI_CR1_SPE, 0);
#endif #endif
/* Save the selection so the subsequence re-configurations will be faster */ /* Save the selection so that subsequent re-configurations will be faster. */
priv->nbits = nbits; priv->nbits = nbits;
} }
@ -1818,10 +1818,10 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
/* If this bus uses a in driver buffers we will incur 2 copies, /* If this bus uses a in driver buffers we will incur 2 copies,
* The copy cost is << less the non DMA transfer time and having * The copy cost is << less the non DMA transfer time and having
* the buffer in the driver ensures DMA can be used. This is bacause * the buffer in the driver ensures DMA can be used. This is because
* the API does not support passing the buffer extent so the only * the API does not support passing the buffer extent so the only
* extent is buffer + the transfer size. These can sizes be less than * extent is buffer + the transfer size. These can sizes be less than
* the cache line size, and not aligned and tyicaly greater then 4 * the cache line size, and not aligned and typically greater then 4
* bytes, which is about the break even point for the DMA IO overhead. * bytes, which is about the break even point for the DMA IO overhead.
*/ */

16
arch/arm/src/stm32f0l0g0/stm32_spi.c
View File

@ -1068,7 +1068,9 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits);
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
/* Save the mode so that subsequent re-configurations will be faster */ /* Save the mode so that subsequent re-configurations will be
* faster.
*/
priv->mode = mode; priv->mode = mode;
} }
@ -1156,7 +1158,9 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0);
#endif #endif
/* Save the selection so that subsequent re-configurations will be faster. */ /* Save the selection so that subsequent re-configurations will be
* faster.
*/
priv->nbits = nbits; priv->nbits = nbits;
} }
@ -1256,7 +1260,9 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
spi_writeword(priv, (uint16_t)(wd & 0xffff)); spi_writeword(priv, (uint16_t)(wd & 0xffff));
ret = (uint32_t)spi_readword(priv); ret = (uint32_t)spi_readword(priv);
/* Check and clear any error flags (Reading from the SR clears the error flags) */ /* Check and clear any error flags (Reading from the SR clears the error
* flags)
*/
regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); regval = spi_getreg(priv, STM32_SPI_SR_OFFSET);
@ -1618,7 +1624,9 @@ static int spi_pm_prepare(FAR struct pm_callback_s *cb, int domain,
if (sval <= 0) if (sval <= 0)
{ {
/* Exclusive lock is held, do not allow entry to deeper PM states. */ /* Exclusive lock is held, do not allow entry to deeper PM
* states.
*/
return -EBUSY; return -EBUSY;
} }

2
arch/arm/src/tiva/common/tiva_ssi.c
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@ -1277,7 +1277,7 @@ static void ssi_setmodeinternal(struct tiva_ssidev_s *priv,
ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval); ssi_putreg(priv, TIVA_SSI_CR0_OFFSET, regval);
spiinfo("CR0: %08x\n", regval); spiinfo("CR0: %08x\n", regval);
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }

4
arch/avr/src/avr/up_spi.c
View File

@ -308,7 +308,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
SPSR = regval; SPSR = regval;
/* Save the mode so that subsequent re-configuratins will be faster */ /* Save the mode so that subsequent re-configurations will be faster */
priv->mode = mode; priv->mode = mode;
} }
@ -322,7 +322,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests (only nbits == 8 is supported) * nbits - The number of bits requested (only nbits == 8 is supported)
* *
* Returned Value: * Returned Value:
* none * none

6
arch/mips/src/pic32mz/pic32mz_spi.c
View File

@ -1368,7 +1368,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -1411,8 +1411,8 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
regval |= setting; regval |= setting;
spi_putreg(priv, PIC32MZ_SPI_CON_OFFSET, regval); spi_putreg(priv, PIC32MZ_SPI_CON_OFFSET, regval);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster * faster.
*/ */
priv->nbits = nbits; priv->nbits = nbits;

8
arch/xtensa/src/esp32/esp32_spi.c
View File

@ -791,16 +791,14 @@ static void esp32_spi_setbits(FAR struct spi_dev_s *dev, int nbits)
if (nbits != priv->nbits) if (nbits != priv->nbits)
{ {
/** /* Save the selection so that subsequent re-configurations
* Save the selection so the subsequence re-configurations
* will be faster. * will be faster.
*/ */
priv->nbits = nbits; priv->nbits = nbits;
/** /* Each DMA transmission will set these value according to
* Each DMA transmission will set these value according to * calculated buffer length.
* calculate buffer length.
*/ */
if (!priv->dma_chan) if (!priv->dma_chan)

4
arch/z16/src/z16f/z16f_espi.c
View File

@ -514,7 +514,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
* *
* Input Parameters: * Input Parameters:
* dev - Device-specific state data * dev - Device-specific state data
* nbits - The number of bits requests * nbits - The number of bits requested
* *
* Returned Value: * Returned Value:
* none * none
@ -548,7 +548,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
spi_putreg8(priv, regval, Z16F_ESPI_MODE); spi_putreg8(priv, regval, Z16F_ESPI_MODE);
spiinfo("ESPI MODE: %02x\n", regval); spiinfo("ESPI MODE: %02x\n", regval);
/* Save the selection so the subsequence re-configurations will be /* Save the selection so that subsequent re-configurations will be
* faster. * faster.
*/ */