Merged in david_s5/nuttx/master_imxrt (pull request #748)
Adding imxrt 106x * imxrt:Fix comment in imxrt105x_memorymap * imxrt:Add imxrt1060 memory map * imxrt:Add imcrt106x to imxrt_memorymap * imxrt:Add i.MX RT 106x to Kconfig * imxrt:Moved IMXRT_GPIO_NPORTS to chip.h & fixed comments * imxrt:105x IRQ fix comment * imxrt:gpioirq GPIO4,5 using wrong boundry * imxrt:Add RT106x irq headers & Kconfig * imxrt:Add rt106x GPIO chip headers * imxrt:Extend Number of GPIO ports * imxrt:Add 106x DMAMUX header * imxrt:iomuxc add 106x * imxrt:106x iomuxc extend Indexes * imxrt:pinmux Add 106x * imxrt:clockconfig use imxrt_memorymap.h * imxrt:allocateheap use OCRAM2 as BASE when avaialbe Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
David Sidrane
GregoryN
parent
813f4d424c
commit
a0745bbef6
@ -2,7 +2,8 @@
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* arch/arm/include/imxrt/chip.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -48,18 +49,31 @@
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/* Get customizations for each supported chip */
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/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1051CVL5A - Consumer, Reduced Features, 600MHz
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* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1052CVL5A - Consumer, Full Feature, 600MHz
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*/
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#if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A)
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/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1052DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 5 /* Five total ports */
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#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \
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defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A)
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/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz
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* MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz
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* MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz
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* MIMXRT1062DVL6A - Consumer, Full Feature, 600MHz
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*/
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# define IMXRT_OCRAM_SIZE (1024 * 1024) /* 1024Kb OCRAM */
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# define IMXRT_GPIO_NPORTS 9 /* Nine total ports */
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#else
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# error "Unknown i.MX RT chip type"
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#endif
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@ -81,7 +81,7 @@
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#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */
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#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */
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#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */
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#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C- Interrupt */
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#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C4 Interrupt */
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#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */
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#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */
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#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */
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725
arch/arm/include/imxrt/imxrt106x_irq.h
Normal file
725
arch/arm/include/imxrt/imxrt106x_irq.h
Normal file
@ -0,0 +1,725 @@
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/****************************************************************************************
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* arch/arm/include/imxrt/imxrt106x_irq.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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/* This file should never be included directed but, rather, only indirectly through
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* nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT106X_IRQ_H
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#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT106X_IRQ_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* External interrupts (priority levels >= 256) *****************************************/
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#define IMXRT_IRQ_EDMA0_16 (IMXRT_IRQ_EXTINT + 0) /* eDMA Channel 0/16 Transfer Complete */
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#define IMXRT_IRQ_EDMA1_17 (IMXRT_IRQ_EXTINT + 1) /* eDMA Channel 1/17 Transfer Complete */
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#define IMXRT_IRQ_EDMA2_18 (IMXRT_IRQ_EXTINT + 2) /* eDMA Channel 2/18 Transfer Complete */
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#define IMXRT_IRQ_EDMA3_19 (IMXRT_IRQ_EXTINT + 3) /* eDMA Channel 3/19 Transfer Complete */
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#define IMXRT_IRQ_EDMA4_20 (IMXRT_IRQ_EXTINT + 4) /* eDMA Channel 4/20 Transfer Complete */
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#define IMXRT_IRQ_EDMA5_21 (IMXRT_IRQ_EXTINT + 5) /* eDMA Channel 5/21 Transfer Complete */
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#define IMXRT_IRQ_EDMA6_22 (IMXRT_IRQ_EXTINT + 6) /* eDMA Channel 6/22 Transfer Complete */
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#define IMXRT_IRQ_EDMA7_23 (IMXRT_IRQ_EXTINT + 7) /* eDMA Channel 7/23 Transfer Complete */
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#define IMXRT_IRQ_EDMA8_24 (IMXRT_IRQ_EXTINT + 8) /* eDMA Channel 8/24 Transfer Complete */
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#define IMXRT_IRQ_EDMA9_25 (IMXRT_IRQ_EXTINT + 9) /* eDMA Channel 9/25 Transfer Complete */
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#define IMXRT_IRQ_EDMA10_26 (IMXRT_IRQ_EXTINT + 10) /* eDMA Channel 10/26 Transfer Complete */
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#define IMXRT_IRQ_EDMA11_27 (IMXRT_IRQ_EXTINT + 11) /* eDMA Channel 11/27 Transfer Complete */
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#define IMXRT_IRQ_EDMA12_28 (IMXRT_IRQ_EXTINT + 12) /* eDMA Channel 12/28 Transfer Complete */
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#define IMXRT_IRQ_EDMA13_29 (IMXRT_IRQ_EXTINT + 13) /* eDMA Channel 13/29 Transfer Complete */
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#define IMXRT_IRQ_EDMA14_30 (IMXRT_IRQ_EXTINT + 14) /* eDMA Channel 14/30 Transfer Complete */
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#define IMXRT_IRQ_EDMA15_31 (IMXRT_IRQ_EXTINT + 15) /* eDMA Channel 15/31 Transfer Complete */
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#define IMXRT_IRQ_EDMA_ERROR (IMXRT_IRQ_EXTINT + 16) /* Error Interrupt, Channels 0-15 / 16-31 */
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#define IMXRT_IRQ_CM70 (IMXRT_IRQ_EXTINT + 17) /* CTI trigger outputs (internal: CTIIRQ[0]) */
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#define IMXRT_IRQ_CM71 (IMXRT_IRQ_EXTINT + 18) /* CTI trigger outputs (internal: CTIIRQ[1]) */
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#define IMXRT_IRQ_CM7CP (IMXRT_IRQ_EXTINT + 19) /* CorePlatform exception IRQ */
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#define IMXRT_IRQ_LPUART1 (IMXRT_IRQ_EXTINT + 20) /* UART1 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART2 (IMXRT_IRQ_EXTINT + 21) /* UART2 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART3 (IMXRT_IRQ_EXTINT + 22) /* UART3 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART4 (IMXRT_IRQ_EXTINT + 23) /* UART4 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART5 (IMXRT_IRQ_EXTINT + 24) /* UART5 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART6 (IMXRT_IRQ_EXTINT + 25) /* UART6 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART7 (IMXRT_IRQ_EXTINT + 26) /* UART7 TX/RX interrupt */
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#define IMXRT_IRQ_LPUART8 (IMXRT_IRQ_EXTINT + 27) /* UART8 TX/RX interrupt */
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#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */
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#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */
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#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */
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#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C4 Interrupt */
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#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */
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#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */
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#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */
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#define IMXRT_IRQ_LPSPI4 (IMXRT_IRQ_EXTINT + 35) /* LPSPI4 interrupt */
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#define IMXRT_IRQ_CAN1 (IMXRT_IRQ_EXTINT + 36) /* CAN1 interrupt */
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#define IMXRT_IRQ_CAN2 (IMXRT_IRQ_EXTINT + 37) /* CAN2 interrupt */
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#define IMXRT_IRQ_CM7FR (IMXRT_IRQ_EXTINT + 38) /* FlexRAM address fault */
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#define IMXRT_IRQ_KPP (IMXRT_IRQ_EXTINT + 39) /* Keypad Interrupt */
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#define IMXRT_IRQ_TSCDIG (IMXRT_IRQ_EXTINT + 40) /* TSC interrupt */
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#define IMXRT_IRQ_GPRIRQ (IMXRT_IRQ_EXTINT + 41) /* Notify cores on exception while boot */
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#define IMXRT_IRQ_LCDIF (IMXRT_IRQ_EXTINT + 42) /* LCDIF Sync Interrupt */
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#define IMXRT_IRQ_CSI (IMXRT_IRQ_EXTINT + 43) /* CSI interrupt */
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#define IMXRT_IRQ_PXP (IMXRT_IRQ_EXTINT + 44) /* PXP interrupt */
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#define IMXRT_IRQ_WDOG2 (IMXRT_IRQ_EXTINT + 45) /* Watchdog Timer reset */
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#define IMXRT_IRQ_SNVS (IMXRT_IRQ_EXTINT + 46) /* SNVS Functional Interrupt */
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#define IMXRT_IRQ_SNVSSEC (IMXRT_IRQ_EXTINT + 47) /* SNVS Security Interrupt */
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#define IMXRT_IRQ_SNVSSB (IMXRT_IRQ_EXTINT + 48) /* ON-OFF short button press */
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#define IMXRT_IRQ_CSU (IMXRT_IRQ_EXTINT + 49) /* CSU Interrupt Request 1 */
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#define IMXRT_IRQ_DCP (IMXRT_IRQ_EXTINT + 50) /* DCP channel/CRC interrupts (channel != 0) */
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#define IMXRT_IRQ_DCP0 (IMXRT_IRQ_EXTINT + 51) /* DCP channel 0 interrupt */
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#define IMXRT_IRQ_RESERVED52 (IMXRT_IRQ_EXTINT + 52) /* Reserved */
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#define IMXRT_IRQ_TRNG (IMXRT_IRQ_EXTINT + 53) /* TRNG Interrupt */
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#define IMXRT_IRQ_SJC (IMXRT_IRQ_EXTINT + 54) /* SJC Interrupt from General Purpose register */
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#define IMXRT_IRQ_BEE (IMXRT_IRQ_EXTINT + 55) /* BEE IRQ */
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#define IMXRT_IRQ_SAI1 (IMXRT_IRQ_EXTINT + 56) /* SAI1 interrupt */
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#define IMXRT_IRQ_SAI2 (IMXRT_IRQ_EXTINT + 57) /* SAI2 interrupt */
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#define IMXRT_IRQ_SAI3RX (IMXRT_IRQ_EXTINT + 58) /* SAI3 RX interrupt */
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#define IMXRT_IRQ_SAI3TX (IMXRT_IRQ_EXTINT + 59) /* SAI3 TX interrupt */
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#define IMXRT_IRQ_SPDIF (IMXRT_IRQ_EXTINT + 60) /* SPDIF interrupt */
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#define IMXRT_IRQ_PMU (IMXRT_IRQ_EXTINT + 61) /* Brown-out event 1.1, 2.5 or 3.0 regulators */
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#define IMXRT_IRQ_RESERVED62 (IMXRT_IRQ_EXTINT + 62) /* Reserved */
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#define IMXRT_IRQ_TEMP (IMXRT_IRQ_EXTINT + 63) /* Temperature Monitor */
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#define IMXRT_IRQ_TEMPPANIC (IMXRT_IRQ_EXTINT + 64) /* TempSensor panic */
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#define IMXRT_IRQ_USBPHY0 (IMXRT_IRQ_EXTINT + 65) /* USBPHY (UTMI0) interrupt */
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#define IMXRT_IRQ_USBPHY1 (IMXRT_IRQ_EXTINT + 66) /* USBPHY (UTMI1) interrupt */
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#define IMXRT_IRQ_ADC1 (IMXRT_IRQ_EXTINT + 67) /* ADC1 interrupt */
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#define IMXRT_IRQ_ADC2 (IMXRT_IRQ_EXTINT + 68) /* ADC2 interrupt */
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#define IMXRT_IRQ_DCDC (IMXRT_IRQ_EXTINT + 69) /* DCDC interrupt */
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#define IMXRT_IRQ_RESERVED70 (IMXRT_IRQ_EXTINT + 70) /* Reserved */
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#define IMXRT_IRQ_RESERVED71 (IMXRT_IRQ_EXTINT + 71) /* Reserved */
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#define IMXRT_IRQ_GPIO1_0 (IMXRT_IRQ_EXTINT + 72) /* GPIO1 INT0 interrupt */
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#define IMXRT_IRQ_GPIO1_1 (IMXRT_IRQ_EXTINT + 73) /* GPIO1 INT1 interrupt */
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#define IMXRT_IRQ_GPIO1_2 (IMXRT_IRQ_EXTINT + 74) /* GPIO1 INT2 interrupt */
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#define IMXRT_IRQ_GPIO1_3 (IMXRT_IRQ_EXTINT + 75) /* GPIO1 INT3 interrupt */
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#define IMXRT_IRQ_GPIO1_4 (IMXRT_IRQ_EXTINT + 76) /* GPIO1 INT4 interrupt */
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#define IMXRT_IRQ_GPIO1_5 (IMXRT_IRQ_EXTINT + 77) /* GPIO1 INT5 interrupt */
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#define IMXRT_IRQ_GPIO1_6 (IMXRT_IRQ_EXTINT + 78) /* GPIO1 INT6 interrupt */
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#define IMXRT_IRQ_GPIO1_7 (IMXRT_IRQ_EXTINT + 79) /* GPIO1 INT7 interrupt */
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#define IMXRT_IRQ_GPIO1_0_15 (IMXRT_IRQ_EXTINT + 80) /* GPIO1 INT0-15 interrupt */
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#define IMXRT_IRQ_GPIO1_16_31 (IMXRT_IRQ_EXTINT + 81) /* GPIO1 INT16-31 interrupt */
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#define IMXRT_IRQ_GPIO2_0_15 (IMXRT_IRQ_EXTINT + 82) /* GPIO2 INT0-15 interrupt */
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#define IMXRT_IRQ_GPIO2_16_31 (IMXRT_IRQ_EXTINT + 83) /* GPIO2 INT16-31 interrupt */
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#define IMXRT_IRQ_GPIO3_0_15 (IMXRT_IRQ_EXTINT + 84) /* GPIO3 INT0-15 interrupt */
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#define IMXRT_IRQ_GPIO3_16_31 (IMXRT_IRQ_EXTINT + 85) /* GPIO3 INT16-31 interrupt */
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#define IMXRT_IRQ_GPIO4_0_15 (IMXRT_IRQ_EXTINT + 86) /* GPIO4 INT0-15 interrupt */
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#define IMXRT_IRQ_GPIO4_16_31 (IMXRT_IRQ_EXTINT + 87) /* GPIO4 INT16-31 interrupt */
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#define IMXRT_IRQ_GPIO5_0_15 (IMXRT_IRQ_EXTINT + 88) /* GPIO5 INT0-15 interrupt */
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#define IMXRT_IRQ_GPIO5_16_31 (IMXRT_IRQ_EXTINT + 89) /* GPIO5 INT16-31 interrupt */
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#define IMXRT_IRQ_FLEXIO1 (IMXRT_IRQ_EXTINT + 90) /* IPI compare interrupt */
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#define IMXRT_IRQ_FLEXIO2 (IMXRT_IRQ_EXTINT + 91) /* IPI compare interrupt */
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#define IMXRT_IRQ_WDOG1 (IMXRT_IRQ_EXTINT + 92) /* Watchdog Timer reset */
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#define IMXRT_IRQ_RTWDOG (IMXRT_IRQ_EXTINT + 93) /* Watchdog Timer reset */
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#define IMXRT_IRQ_EWM (IMXRT_IRQ_EXTINT + 94) /* EWM interrupt */
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#define IMXRT_IRQ_CCM_1 (IMXRT_IRQ_EXTINT + 95) /* CCM interrupt 1 */
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#define IMXRT_IRQ_CCM_2 (IMXRT_IRQ_EXTINT + 96) /* CCM interrupt 2 */
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#define IMXRT_IRQ_GPC (IMXRT_IRQ_EXTINT + 97) /* GPC interrupt 1 */
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#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */
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#define IMXRT_IRQ_RESERVED99 (IMXRT_IRQ_EXTINT + 99) /* Reserved */
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#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */
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#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */
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#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */
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#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */
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#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */
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#define IMXRT_IRQ_FLEXPWM1_3 (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */
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#define IMXRT_IRQ_FLEXPWM1_F (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt */
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#define IMXRT_IRQ_FLEXSPI2 (IMXRT_IRQ_EXTINT + 107) /* FlexSPI2 interrupt */
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#define IMXRT_IRQ_FLEXSPI (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */
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#define IMXRT_IRQ_SEMC (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */
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#define IMXRT_IRQ_USDHC1 (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */
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#define IMXRT_IRQ_USDHC2 (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */
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#define IMXRT_IRQ_USBOTG2 (IMXRT_IRQ_EXTINT + 112) /* USBO2 USB OTG2 interrupt */
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#define IMXRT_IRQ_USBOTG1 (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */
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#define IMXRT_IRQ_ENET (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */
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#define IMXRT_IRQ_ENET1588 (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */
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#define IMXRT_IRQ_XBAR1_0_1 (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */
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#define IMXRT_IRQ_XBAR1_2_3 (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */
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#define IMXRT_IRQ_ADCETC_0 (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */
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#define IMXRT_IRQ_ADCETC_1 (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */
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#define IMXRT_IRQ_ADCETC_2 (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */
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#define IMXRT_IRQ_ADCETC_ERR (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */
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#define IMXRT_IRQ_PIT (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */
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#define IMXRT_IRQ_ACMP1 (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */
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#define IMXRT_IRQ_ACMP2 (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */
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#define IMXRT_IRQ_ACMP3 (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */
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#define IMXRT_IRQ_ACMP4 (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */
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#define IMXRT_IRQ_RESERVED127 (IMXRT_IRQ_EXTINT + 127) /* Reserved */
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#define IMXRT_IRQ_RESERVED128 (IMXRT_IRQ_EXTINT + 128) /* Reserved */
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#define IMXRT_IRQ_ENC1 (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */
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#define IMXRT_IRQ_ENC2 (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */
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#define IMXRT_IRQ_ENC3 (IMXRT_IRQ_EXTINT + 131) /* ENC3 interrupt */
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#define IMXRT_IRQ_ENC4 (IMXRT_IRQ_EXTINT + 132) /* ENC4 interrupt */
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#define IMXRT_IRQ_QTIMER1 (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */
|
||||
#define IMXRT_IRQ_QTIMER2 (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */
|
||||
#define IMXRT_IRQ_QTIMER3 (IMXRT_IRQ_EXTINT + 135) /* QTIMER3 timer 0-3 interrupt */
|
||||
#define IMXRT_IRQ_QTIMER4 (IMXRT_IRQ_EXTINT + 136) /* QTIMER4 timer 0-3 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM2_0 (IMXRT_IRQ_EXTINT + 137) /* LEXPWM2 capture/compare/reload 0 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM2_1 (IMXRT_IRQ_EXTINT + 138) /* LEXPWM2 capture/compare/reload 1 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM2_2 (IMXRT_IRQ_EXTINT + 139) /* LEXPWM2 capture/compare/reload 1 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM2_3 (IMXRT_IRQ_EXTINT + 140) /* LEXPWM2 capture/compare/reload 3 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM2_F (IMXRT_IRQ_EXTINT + 141) /* LEXPWM2 fault interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM3_0 (IMXRT_IRQ_EXTINT + 142) /* LEXPWM3 capture/compare/reload 0 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM3_1 (IMXRT_IRQ_EXTINT + 143) /* LEXPWM3 capture/compare/reload 1 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM3_2 (IMXRT_IRQ_EXTINT + 144) /* LEXPWM3 capture/compare/reload 2 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM3_F (IMXRT_IRQ_EXTINT + 146) /* LEXPWM3 fault interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM4_0 (IMXRT_IRQ_EXTINT + 147) /* LEXPWM4 capture/compare/reload 0 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM4_1 (IMXRT_IRQ_EXTINT + 148) /* LEXPWM4 capture/compare/reload 1 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM4_2 (IMXRT_IRQ_EXTINT + 149) /* LEXPWM4 capture/compare/reload 2 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM4_3 (IMXRT_IRQ_EXTINT + 150) /* LEXPWM4 capture/compare/reload 3 interrupt */
|
||||
#define IMXRT_IRQ_FLEXPWM4_F (IMXRT_IRQ_EXTINT + 151) /* LEXPWM4 fault interrupt */
|
||||
#define IMXRT_IRQ_ENET2 (IMXRT_IRQ_EXTINT + 152) /* ENET2 MAC0 interrupt */
|
||||
#define IMXRT_IRQ_ENET2_1588 (IMXRT_IRQ_EXTINT + 153) /* ENET2 MAC 0 1588 Timer Interrupt */
|
||||
#define IMXRT_IRQ_CAN3 (IMXRT_IRQ_EXTINT + 154) /* CAN3 interrupt */
|
||||
#define IMXRT_IRQ_RESERVED155 (IMXRT_IRQ_EXTINT + 155) /* Reserved */
|
||||
#define IMXRT_IRQ_FLEXIO3 (IMXRT_IRQ_EXTINT + 156) /* IPI compare interrupt */
|
||||
#define IMXRT_IRQ_GPIO_6789 (IMXRT_IRQ_EXTINT + 157) /* GPIO {6789} or'ed Interrupt */
|
||||
#define IMXRT_IRQ_RESERVED158 (IMXRT_IRQ_EXTINT + 158) /* Reserved */
|
||||
#define IMXRT_IRQ_RESERVED159 (IMXRT_IRQ_EXTINT + 159) /* Reserved */
|
||||
|
||||
#define IMXRT_IRQ_NEXTINT 160
|
||||
|
||||
/* GPIO second level interrupt **********************************************************/
|
||||
|
||||
#define IMXRT_GPIO_IRQ_FIRST (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT)
|
||||
#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ
|
||||
/* GPIO1 has dedicated interrupts for pins 0-7
|
||||
* REVISIT: I am assuming that you really cannot use the dedicated and the multiplex
|
||||
* interrupts concurrently.
|
||||
*/
|
||||
|
||||
# define IMXRT_IRQ_GPIO1_0 (_IMXRT_GPIO1_0_15_BASE + 0) /* GPIO1 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_1 (_IMXRT_GPIO1_0_15_BASE + 1) /* GPIO1 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_2 (_IMXRT_GPIO1_0_15_BASE + 2) /* GPIO1 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_3 (_IMXRT_GPIO1_0_15_BASE + 3) /* GPIO1 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_4 (_IMXRT_GPIO1_0_15_BASE + 4) /* GPIO1 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_5 (_IMXRT_GPIO1_0_15_BASE + 5) /* GPIO1 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_6 (_IMXRT_GPIO1_0_15_BASE + 6) /* GPIO1 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_7 (_IMXRT_GPIO1_0_15_BASE + 7) /* GPIO1 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_8 (_IMXRT_GPIO1_0_15_BASE + 8) /* GPIO1 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_9 (_IMXRT_GPIO1_0_15_BASE + 9) /* GPIO1 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_10 (_IMXRT_GPIO1_0_15_BASE + 10) /* GPIO1 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_11 (_IMXRT_GPIO1_0_15_BASE + 11) /* GPIO1 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_12 (_IMXRT_GPIO1_0_15_BASE + 12) /* GPIO1 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_13 (_IMXRT_GPIO1_0_15_BASE + 13) /* GPIO1 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_14 (_IMXRT_GPIO1_0_15_BASE + 14) /* GPIO1 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_15 (_IMXRT_GPIO1_0_15_BASE + 15) /* GPIO1 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO1_8_15_NIRQS 16
|
||||
# define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO1_8_15_NIRQS 0
|
||||
# define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO1_16 (_IMXRT_GPIO1_16_31_BASE + 0) /* GPIO1 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_17 (_IMXRT_GPIO1_16_31_BASE + 1) /* GPIO1 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_18 (_IMXRT_GPIO1_16_31_BASE + 2) /* GPIO1 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_19 (_IMXRT_GPIO1_16_31_BASE + 3) /* GPIO1 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_20 (_IMXRT_GPIO1_16_31_BASE + 4) /* GPIO1 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_21 (_IMXRT_GPIO1_16_31_BASE + 5) /* GPIO1 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_22 (_IMXRT_GPIO1_16_31_BASE + 6) /* GPIO1 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_23 (_IMXRT_GPIO1_16_31_BASE + 7) /* GPIO1 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_24 (_IMXRT_GPIO1_16_31_BASE + 8) /* GPIO1 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_25 (_IMXRT_GPIO1_16_31_BASE + 9) /* GPIO1 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_26 (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_27 (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_28 (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_29 (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_30 (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO1_31 (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO1_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS)
|
||||
# define IMXRT_GPIO1_NIRQS (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE
|
||||
# define IMXRT_GPIO1_NIRQS _IMXRT_GPIO1_8_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO2_0 (_IMXRT_GPIO2_0_15_BASE + 0) /* GPIO2 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_1 (_IMXRT_GPIO2_0_15_BASE + 1) /* GPIO2 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_2 (_IMXRT_GPIO2_0_15_BASE + 2) /* GPIO2 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_3 (_IMXRT_GPIO2_0_15_BASE + 3) /* GPIO2 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_4 (_IMXRT_GPIO2_0_15_BASE + 4) /* GPIO2 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_5 (_IMXRT_GPIO2_0_15_BASE + 5) /* GPIO2 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_6 (_IMXRT_GPIO2_0_15_BASE + 6) /* GPIO2 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_7 (_IMXRT_GPIO2_0_15_BASE + 7) /* GPIO2 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_8 (_IMXRT_GPIO2_0_15_BASE + 8) /* GPIO2 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_9 (_IMXRT_GPIO2_0_15_BASE + 9) /* GPIO2 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_10 (_IMXRT_GPIO2_0_15_BASE + 10) /* GPIO2 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_11 (_IMXRT_GPIO2_0_15_BASE + 11) /* GPIO2 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_12 (_IMXRT_GPIO2_0_15_BASE + 12) /* GPIO2 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_13 (_IMXRT_GPIO2_0_15_BASE + 13) /* GPIO2 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_14 (_IMXRT_GPIO2_0_15_BASE + 14) /* GPIO2 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_15 (_IMXRT_GPIO2_0_15_BASE + 15) /* GPIO2 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO2_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO2_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO2_16 (_IMXRT_GPIO2_16_31_BASE + 0) /* GPIO2 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_17 (_IMXRT_GPIO2_16_31_BASE + 1) /* GPIO2 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_18 (_IMXRT_GPIO2_16_31_BASE + 2) /* GPIO2 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_19 (_IMXRT_GPIO2_16_31_BASE + 3) /* GPIO2 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_20 (_IMXRT_GPIO2_16_31_BASE + 4) /* GPIO2 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_21 (_IMXRT_GPIO2_16_31_BASE + 5) /* GPIO2 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_22 (_IMXRT_GPIO2_16_31_BASE + 6) /* GPIO2 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_23 (_IMXRT_GPIO2_16_31_BASE + 7) /* GPIO2 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_24 (_IMXRT_GPIO2_16_31_BASE + 8) /* GPIO2 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_25 (_IMXRT_GPIO2_16_31_BASE + 9) /* GPIO2 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_26 (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_27 (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_28 (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_29 (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_30 (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO2_31 (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO2_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS)
|
||||
# define IMXRT_GPIO2_NIRQS (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE
|
||||
# define IMXRT_GPIO2_NIRQS _IMXRT_GPIO2_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO3_0 (_IMXRT_GPIO3_0_15_BASE + 0) /* GPIO3 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_1 (_IMXRT_GPIO3_0_15_BASE + 1) /* GPIO3 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_2 (_IMXRT_GPIO3_0_15_BASE + 2) /* GPIO3 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_3 (_IMXRT_GPIO3_0_15_BASE + 3) /* GPIO3 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_4 (_IMXRT_GPIO3_0_15_BASE + 4) /* GPIO3 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_5 (_IMXRT_GPIO3_0_15_BASE + 5) /* GPIO3 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_6 (_IMXRT_GPIO3_0_15_BASE + 6) /* GPIO3 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_7 (_IMXRT_GPIO3_0_15_BASE + 7) /* GPIO3 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_8 (_IMXRT_GPIO3_0_15_BASE + 8) /* GPIO3 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_9 (_IMXRT_GPIO3_0_15_BASE + 9) /* GPIO3 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_10 (_IMXRT_GPIO3_0_15_BASE + 10) /* GPIO3 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_11 (_IMXRT_GPIO3_0_15_BASE + 11) /* GPIO3 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_12 (_IMXRT_GPIO3_0_15_BASE + 12) /* GPIO3 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_13 (_IMXRT_GPIO3_0_15_BASE + 13) /* GPIO3 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_14 (_IMXRT_GPIO3_0_15_BASE + 14) /* GPIO3 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_15 (_IMXRT_GPIO3_0_15_BASE + 15) /* GPIO3 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO3_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO3_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO3_16 (_IMXRT_GPIO3_16_31_BASE + 0) /* GPIO3 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_17 (_IMXRT_GPIO3_16_31_BASE + 1) /* GPIO3 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_18 (_IMXRT_GPIO3_16_31_BASE + 2) /* GPIO3 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_19 (_IMXRT_GPIO3_16_31_BASE + 3) /* GPIO3 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_20 (_IMXRT_GPIO3_16_31_BASE + 4) /* GPIO3 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_21 (_IMXRT_GPIO3_16_31_BASE + 5) /* GPIO3 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_22 (_IMXRT_GPIO3_16_31_BASE + 6) /* GPIO3 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_23 (_IMXRT_GPIO3_16_31_BASE + 7) /* GPIO3 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_24 (_IMXRT_GPIO3_16_31_BASE + 8) /* GPIO3 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_25 (_IMXRT_GPIO3_16_31_BASE + 9) /* GPIO3 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_26 (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_27 (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_28 (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_29 (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_30 (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO3_31 (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO3_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO4_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS)
|
||||
# define IMXRT_GPIO3_NIRQS (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO4_0_15_BASE _IMXRT_GPIO3_16_31_BASE
|
||||
# define IMXRT_GPIO3_NIRQS _IMXRT_GPIO3_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO4_0 (_IMXRT_GPIO4_0_15_BASE + 0) /* GPIO4 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_1 (_IMXRT_GPIO4_0_15_BASE + 1) /* GPIO4 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_2 (_IMXRT_GPIO4_0_15_BASE + 2) /* GPIO4 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_3 (_IMXRT_GPIO4_0_15_BASE + 3) /* GPIO4 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_4 (_IMXRT_GPIO4_0_15_BASE + 4) /* GPIO4 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_5 (_IMXRT_GPIO4_0_15_BASE + 5) /* GPIO4 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_6 (_IMXRT_GPIO4_0_15_BASE + 6) /* GPIO4 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_7 (_IMXRT_GPIO4_0_15_BASE + 7) /* GPIO4 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_8 (_IMXRT_GPIO4_0_15_BASE + 8) /* GPIO4 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_9 (_IMXRT_GPIO4_0_15_BASE + 9) /* GPIO4 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_10 (_IMXRT_GPIO4_0_15_BASE + 10) /* GPIO4 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_11 (_IMXRT_GPIO4_0_15_BASE + 11) /* GPIO4 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_12 (_IMXRT_GPIO4_0_15_BASE + 12) /* GPIO4 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_13 (_IMXRT_GPIO4_0_15_BASE + 13) /* GPIO4 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_14 (_IMXRT_GPIO4_0_15_BASE + 14) /* GPIO4 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_15 (_IMXRT_GPIO4_0_15_BASE + 15) /* GPIO4 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO4_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO4_16_31_BASE (_IMXRT_GPIO4_0_15_BASE + _IMXRT_GPIO4_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO4_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO4_16_31_BASE _IMXRT_GPIO4_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO4_16 (_IMXRT_GPIO4_16_31_BASE + 0) /* GPIO4 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_17 (_IMXRT_GPIO4_16_31_BASE + 1) /* GPIO4 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_18 (_IMXRT_GPIO4_16_31_BASE + 2) /* GPIO4 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_19 (_IMXRT_GPIO4_16_31_BASE + 3) /* GPIO4 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_20 (_IMXRT_GPIO4_16_31_BASE + 4) /* GPIO4 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_21 (_IMXRT_GPIO4_16_31_BASE + 5) /* GPIO4 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_22 (_IMXRT_GPIO4_16_31_BASE + 6) /* GPIO4 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_23 (_IMXRT_GPIO4_16_31_BASE + 7) /* GPIO4 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_24 (_IMXRT_GPIO4_16_31_BASE + 8) /* GPIO4 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_25 (_IMXRT_GPIO4_16_31_BASE + 9) /* GPIO4 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_26 (_IMXRT_GPIO4_16_31_BASE + 10) /* GPIO4 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_27 (_IMXRT_GPIO4_16_31_BASE + 11) /* GPIO4 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_28 (_IMXRT_GPIO4_16_31_BASE + 12) /* GPIO4 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_29 (_IMXRT_GPIO4_16_31_BASE + 13) /* GPIO4 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_30 (_IMXRT_GPIO4_16_31_BASE + 14) /* GPIO4 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO4_31 (_IMXRT_GPIO4_16_31_BASE + 15) /* GPIO4 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO4_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO4_16_31_BASE + _IMXRT_GPIO4_16_31_NIRQS)
|
||||
# define IMXRT_GPIO4_NIRQS (_IMXRT_GPIO4_0_15_NIRQS + _IMXRT_GPIO4_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO4_16_31_BASE
|
||||
# define IMXRT_GPIO4_NIRQS _IMXRT_GPIO4_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO5_0 (_IMXRT_GPIO5_0_15_BASE + 0) /* GPIO5 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_1 (_IMXRT_GPIO5_0_15_BASE + 1) /* GPIO5 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_2 (_IMXRT_GPIO5_0_15_BASE + 2) /* GPIO5 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_3 (_IMXRT_GPIO5_0_15_BASE + 3) /* GPIO5 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_4 (_IMXRT_GPIO5_0_15_BASE + 4) /* GPIO5 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_5 (_IMXRT_GPIO5_0_15_BASE + 5) /* GPIO5 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_6 (_IMXRT_GPIO5_0_15_BASE + 6) /* GPIO5 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_7 (_IMXRT_GPIO5_0_15_BASE + 7) /* GPIO5 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_8 (_IMXRT_GPIO5_0_15_BASE + 8) /* GPIO5 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_9 (_IMXRT_GPIO5_0_15_BASE + 9) /* GPIO5 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_10 (_IMXRT_GPIO5_0_15_BASE + 10) /* GPIO5 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_11 (_IMXRT_GPIO5_0_15_BASE + 11) /* GPIO5 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_12 (_IMXRT_GPIO5_0_15_BASE + 12) /* GPIO5 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_13 (_IMXRT_GPIO5_0_15_BASE + 13) /* GPIO5 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_14 (_IMXRT_GPIO5_0_15_BASE + 14) /* GPIO5 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_15 (_IMXRT_GPIO5_0_15_BASE + 15) /* GPIO5 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO5_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO5_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO5_16 (_IMXRT_GPIO5_16_31_BASE + 0) /* GPIO5 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_17 (_IMXRT_GPIO5_16_31_BASE + 1) /* GPIO5 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_18 (_IMXRT_GPIO5_16_31_BASE + 2) /* GPIO5 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_19 (_IMXRT_GPIO5_16_31_BASE + 3) /* GPIO5 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_20 (_IMXRT_GPIO5_16_31_BASE + 4) /* GPIO5 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_21 (_IMXRT_GPIO5_16_31_BASE + 5) /* GPIO5 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_22 (_IMXRT_GPIO5_16_31_BASE + 6) /* GPIO5 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_23 (_IMXRT_GPIO5_16_31_BASE + 7) /* GPIO5 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_24 (_IMXRT_GPIO5_16_31_BASE + 8) /* GPIO5 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_25 (_IMXRT_GPIO5_16_31_BASE + 9) /* GPIO5 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_26 (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_27 (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_28 (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_29 (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_30 (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO5_31 (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO5_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO6_0_15_BASE (_IMXRT_GPIO5_16_31_BASE + _IMXRT_GPIO5_16_31_NIRQS)
|
||||
# define IMXRT_GPIO5_NIRQS (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO6_0_15_BASE _IMXRT_GPIO5_16_31_BASE
|
||||
# define IMXRT_GPIO5_NIRQS _IMXRT_GPIO5_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO6_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO6_0 (_IMXRT_GPIO6_0_15_BASE + 0) /* GPIO6 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_1 (_IMXRT_GPIO6_0_15_BASE + 1) /* GPIO6 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_2 (_IMXRT_GPIO6_0_15_BASE + 2) /* GPIO6 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_3 (_IMXRT_GPIO6_0_15_BASE + 3) /* GPIO6 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_4 (_IMXRT_GPIO6_0_15_BASE + 4) /* GPIO6 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_5 (_IMXRT_GPIO6_0_15_BASE + 5) /* GPIO6 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_6 (_IMXRT_GPIO6_0_15_BASE + 6) /* GPIO6 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_7 (_IMXRT_GPIO6_0_15_BASE + 7) /* GPIO6 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_8 (_IMXRT_GPIO6_0_15_BASE + 8) /* GPIO6 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_9 (_IMXRT_GPIO6_0_15_BASE + 9) /* GPIO6 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_10 (_IMXRT_GPIO6_0_15_BASE + 10) /* GPIO6 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_11 (_IMXRT_GPIO6_0_15_BASE + 11) /* GPIO6 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_12 (_IMXRT_GPIO6_0_15_BASE + 12) /* GPIO6 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_13 (_IMXRT_GPIO6_0_15_BASE + 13) /* GPIO6 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_14 (_IMXRT_GPIO6_0_15_BASE + 14) /* GPIO6 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_15 (_IMXRT_GPIO6_0_15_BASE + 15) /* GPIO6 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO6_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO6_16_31_BASE (_IMXRT_GPIO6_0_15_BASE + _IMXRT_GPIO6_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO6_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO6_16_31_BASE _IMXRT_GPIO6_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO6_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO6_16 (_IMXRT_GPIO6_16_31_BASE + 0) /* GPIO6 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_17 (_IMXRT_GPIO6_16_31_BASE + 1) /* GPIO6 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_18 (_IMXRT_GPIO6_16_31_BASE + 2) /* GPIO6 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_19 (_IMXRT_GPIO6_16_31_BASE + 3) /* GPIO6 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_20 (_IMXRT_GPIO6_16_31_BASE + 4) /* GPIO6 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_21 (_IMXRT_GPIO6_16_31_BASE + 5) /* GPIO6 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_22 (_IMXRT_GPIO6_16_31_BASE + 6) /* GPIO6 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_23 (_IMXRT_GPIO6_16_31_BASE + 7) /* GPIO6 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_24 (_IMXRT_GPIO6_16_31_BASE + 8) /* GPIO6 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_25 (_IMXRT_GPIO6_16_31_BASE + 9) /* GPIO6 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_26 (_IMXRT_GPIO6_16_31_BASE + 10) /* GPIO6 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_27 (_IMXRT_GPIO6_16_31_BASE + 11) /* GPIO6 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_28 (_IMXRT_GPIO6_16_31_BASE + 12) /* GPIO6 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_29 (_IMXRT_GPIO6_16_31_BASE + 13) /* GPIO6 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_30 (_IMXRT_GPIO6_16_31_BASE + 14) /* GPIO6 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO6_31 (_IMXRT_GPIO6_16_31_BASE + 15) /* GPIO6 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO6_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO7_0_15_BASE (_IMXRT_GPIO6_16_31_BASE + _IMXRT_GPIO6_16_31_NIRQS)
|
||||
# define IMXRT_GPIO6_NIRQS (_IMXRT_GPIO6_0_15_NIRQS + _IMXRT_GPIO6_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO7_0_15_BASE _IMXRT_GPIO6_16_31_BASE
|
||||
# define IMXRT_GPIO6_NIRQS _IMXRT_GPIO6_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO7_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO7_0 (_IMXRT_GPIO7_0_15_BASE + 0) /* GPIO7 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_1 (_IMXRT_GPIO7_0_15_BASE + 1) /* GPIO7 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_2 (_IMXRT_GPIO7_0_15_BASE + 2) /* GPIO7 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_3 (_IMXRT_GPIO7_0_15_BASE + 3) /* GPIO7 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_4 (_IMXRT_GPIO7_0_15_BASE + 4) /* GPIO7 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_5 (_IMXRT_GPIO7_0_15_BASE + 5) /* GPIO7 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_6 (_IMXRT_GPIO7_0_15_BASE + 6) /* GPIO7 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_7 (_IMXRT_GPIO7_0_15_BASE + 7) /* GPIO7 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_8 (_IMXRT_GPIO7_0_15_BASE + 8) /* GPIO7 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_9 (_IMXRT_GPIO7_0_15_BASE + 9) /* GPIO7 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_10 (_IMXRT_GPIO7_0_15_BASE + 10) /* GPIO7 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_11 (_IMXRT_GPIO7_0_15_BASE + 11) /* GPIO7 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_12 (_IMXRT_GPIO7_0_15_BASE + 12) /* GPIO7 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_13 (_IMXRT_GPIO7_0_15_BASE + 13) /* GPIO7 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_14 (_IMXRT_GPIO7_0_15_BASE + 14) /* GPIO7 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_15 (_IMXRT_GPIO7_0_15_BASE + 15) /* GPIO7 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO7_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO7_16_31_BASE (_IMXRT_GPIO7_0_15_BASE + _IMXRT_GPIO7_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO7_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO7_16_31_BASE _IMXRT_GPIO7_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO7_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO7_16 (_IMXRT_GPIO7_16_31_BASE + 0) /* GPIO7 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_17 (_IMXRT_GPIO7_16_31_BASE + 1) /* GPIO7 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_18 (_IMXRT_GPIO7_16_31_BASE + 2) /* GPIO7 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_19 (_IMXRT_GPIO7_16_31_BASE + 3) /* GPIO7 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_20 (_IMXRT_GPIO7_16_31_BASE + 4) /* GPIO7 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_21 (_IMXRT_GPIO7_16_31_BASE + 5) /* GPIO7 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_22 (_IMXRT_GPIO7_16_31_BASE + 6) /* GPIO7 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_23 (_IMXRT_GPIO7_16_31_BASE + 7) /* GPIO7 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_24 (_IMXRT_GPIO7_16_31_BASE + 8) /* GPIO7 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_25 (_IMXRT_GPIO7_16_31_BASE + 9) /* GPIO7 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_26 (_IMXRT_GPIO7_16_31_BASE + 10) /* GPIO7 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_27 (_IMXRT_GPIO7_16_31_BASE + 11) /* GPIO7 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_28 (_IMXRT_GPIO7_16_31_BASE + 12) /* GPIO7 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_29 (_IMXRT_GPIO7_16_31_BASE + 13) /* GPIO7 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_30 (_IMXRT_GPIO7_16_31_BASE + 14) /* GPIO7 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO7_31 (_IMXRT_GPIO7_16_31_BASE + 15) /* GPIO7 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO7_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO8_0_15_BASE (_IMXRT_GPIO7_16_31_BASE + _IMXRT_GPIO7_16_31_NIRQS)
|
||||
# define IMXRT_GPIO7_NIRQS (_IMXRT_GPIO7_0_15_NIRQS + _IMXRT_GPIO7_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO8_0_15_BASE _IMXRT_GPIO7_16_31_BASE
|
||||
# define IMXRT_GPIO7_NIRQS _IMXRT_GPIO7_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO8_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO8_0 (_IMXRT_GPIO8_0_15_BASE + 0) /* GPIO8 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_1 (_IMXRT_GPIO8_0_15_BASE + 1) /* GPIO8 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_2 (_IMXRT_GPIO8_0_15_BASE + 2) /* GPIO8 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_3 (_IMXRT_GPIO8_0_15_BASE + 3) /* GPIO8 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_4 (_IMXRT_GPIO8_0_15_BASE + 4) /* GPIO8 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_5 (_IMXRT_GPIO8_0_15_BASE + 5) /* GPIO8 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_6 (_IMXRT_GPIO8_0_15_BASE + 6) /* GPIO8 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_7 (_IMXRT_GPIO8_0_15_BASE + 7) /* GPIO8 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_8 (_IMXRT_GPIO8_0_15_BASE + 8) /* GPIO8 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_9 (_IMXRT_GPIO8_0_15_BASE + 9) /* GPIO8 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_10 (_IMXRT_GPIO8_0_15_BASE + 10) /* GPIO8 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_11 (_IMXRT_GPIO8_0_15_BASE + 11) /* GPIO8 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_12 (_IMXRT_GPIO8_0_15_BASE + 12) /* GPIO8 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_13 (_IMXRT_GPIO8_0_15_BASE + 13) /* GPIO8 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_14 (_IMXRT_GPIO8_0_15_BASE + 14) /* GPIO8 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_15 (_IMXRT_GPIO8_0_15_BASE + 15) /* GPIO8 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO8_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO8_16_31_BASE (_IMXRT_GPIO8_0_15_BASE + _IMXRT_GPIO8_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO8_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO8_16_31_BASE _IMXRT_GPIO8_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO8_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO8_16 (_IMXRT_GPIO8_16_31_BASE + 0) /* GPIO8 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_17 (_IMXRT_GPIO8_16_31_BASE + 1) /* GPIO8 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_18 (_IMXRT_GPIO8_16_31_BASE + 2) /* GPIO8 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_19 (_IMXRT_GPIO8_16_31_BASE + 3) /* GPIO8 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_20 (_IMXRT_GPIO8_16_31_BASE + 4) /* GPIO8 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_21 (_IMXRT_GPIO8_16_31_BASE + 5) /* GPIO8 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_22 (_IMXRT_GPIO8_16_31_BASE + 6) /* GPIO8 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_23 (_IMXRT_GPIO8_16_31_BASE + 7) /* GPIO8 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_24 (_IMXRT_GPIO8_16_31_BASE + 8) /* GPIO8 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_25 (_IMXRT_GPIO8_16_31_BASE + 9) /* GPIO8 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_26 (_IMXRT_GPIO8_16_31_BASE + 10) /* GPIO8 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_27 (_IMXRT_GPIO8_16_31_BASE + 11) /* GPIO8 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_28 (_IMXRT_GPIO8_16_31_BASE + 12) /* GPIO8 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_29 (_IMXRT_GPIO8_16_31_BASE + 13) /* GPIO8 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_30 (_IMXRT_GPIO8_16_31_BASE + 14) /* GPIO8 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO8_31 (_IMXRT_GPIO8_16_31_BASE + 15) /* GPIO8 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO8_16_31_NIRQS 16
|
||||
# define _IMXRT_GPIO9_0_15_BASE (_IMXRT_GPIO8_16_31_BASE + _IMXRT_GPIO8_16_31_NIRQS)
|
||||
# define IMXRT_GPIO8_NIRQS (_IMXRT_GPIO8_0_15_NIRQS + _IMXRT_GPIO8_16_31_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO9_0_15_BASE _IMXRT_GPIO8_16_31_BASE
|
||||
# define IMXRT_GPIO8_NIRQS _IMXRT_GPIO8_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO9_0_15_IRQ
|
||||
# define IMXRT_IRQ_GPIO9_0 (_IMXRT_GPIO9_0_15_BASE + 0) /* GPIO9 pin 0 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_1 (_IMXRT_GPIO9_0_15_BASE + 1) /* GPIO9 pin 1 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_2 (_IMXRT_GPIO9_0_15_BASE + 2) /* GPIO9 pin 2 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_3 (_IMXRT_GPIO9_0_15_BASE + 3) /* GPIO9 pin 3 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_4 (_IMXRT_GPIO9_0_15_BASE + 4) /* GPIO9 pin 4 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_5 (_IMXRT_GPIO9_0_15_BASE + 5) /* GPIO9 pin 5 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_6 (_IMXRT_GPIO9_0_15_BASE + 6) /* GPIO9 pin 6 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_7 (_IMXRT_GPIO9_0_15_BASE + 7) /* GPIO9 pin 7 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_8 (_IMXRT_GPIO9_0_15_BASE + 8) /* GPIO9 pin 8 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_9 (_IMXRT_GPIO9_0_15_BASE + 9) /* GPIO9 pin 9 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_10 (_IMXRT_GPIO9_0_15_BASE + 10) /* GPIO9 pin 10 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_11 (_IMXRT_GPIO9_0_15_BASE + 11) /* GPIO9 pin 11 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_12 (_IMXRT_GPIO9_0_15_BASE + 12) /* GPIO9 pin 12 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_13 (_IMXRT_GPIO9_0_15_BASE + 13) /* GPIO9 pin 13 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_14 (_IMXRT_GPIO9_0_15_BASE + 14) /* GPIO9 pin 14 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_15 (_IMXRT_GPIO9_0_15_BASE + 15) /* GPIO9 pin 15 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO9_0_15_NIRQS 16
|
||||
# define _IMXRT_GPIO9_16_31_BASE (_IMXRT_GPIO9_0_15_BASE + _IMXRT_GPIO9_0_15_NIRQS)
|
||||
#else
|
||||
# define _IMXRT_GPIO9_0_15_NIRQS 0
|
||||
# define _IMXRT_GPIO9_16_31_BASE _IMXRT_GPIO9_0_15_BASE
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO9_16_31_IRQ
|
||||
# define IMXRT_IRQ_GPIO9_16 (_IMXRT_GPIO9_16_31_BASE + 0) /* GPIO9 pin 16 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_17 (_IMXRT_GPIO9_16_31_BASE + 1) /* GPIO9 pin 17 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_18 (_IMXRT_GPIO9_16_31_BASE + 2) /* GPIO9 pin 18 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_19 (_IMXRT_GPIO9_16_31_BASE + 3) /* GPIO9 pin 19 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_20 (_IMXRT_GPIO9_16_31_BASE + 4) /* GPIO9 pin 20 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_21 (_IMXRT_GPIO9_16_31_BASE + 5) /* GPIO9 pin 21 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_22 (_IMXRT_GPIO9_16_31_BASE + 6) /* GPIO9 pin 22 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_23 (_IMXRT_GPIO9_16_31_BASE + 7) /* GPIO9 pin 23 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_24 (_IMXRT_GPIO9_16_31_BASE + 8) /* GPIO9 pin 24 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_25 (_IMXRT_GPIO9_16_31_BASE + 9) /* GPIO9 pin 25 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_26 (_IMXRT_GPIO9_16_31_BASE + 10) /* GPIO9 pin 26 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_27 (_IMXRT_GPIO9_16_31_BASE + 11) /* GPIO9 pin 27 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_28 (_IMXRT_GPIO9_16_31_BASE + 12) /* GPIO9 pin 28 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_29 (_IMXRT_GPIO9_16_31_BASE + 13) /* GPIO9 pin 29 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_30 (_IMXRT_GPIO9_16_31_BASE + 14) /* GPIO9 pin 30 interrupt */
|
||||
# define IMXRT_IRQ_GPIO9_31 (_IMXRT_GPIO9_16_31_BASE + 15) /* GPIO9 pin 31 interrupt */
|
||||
|
||||
# define _IMXRT_GPIO9_16_31_NIRQS 16
|
||||
# define IMXRT_GPIO9_NIRQS (_IMXRT_GPIO9_0_15_NIRQS + _IMXRT_GPIO9_16_31_NIRQS)
|
||||
#else
|
||||
# define IMXRT_GPIO9_NIRQS _IMXRT_GPIO9_0_15_NIRQS
|
||||
#endif
|
||||
|
||||
#define IMXRT_GPIO_NIRQS (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \
|
||||
IMXRT_GPIO3_NIRQS + IMXRT_GPIO4_NIRQS + \
|
||||
IMXRT_GPIO5_NIRQS + IMXRT_GPIO6_NIRQS + \
|
||||
IMXRT_GPIO7_NIRQS + IMXRT_GPIO9_NIRQS + \
|
||||
IMXRT_GPIO9_NIRQS )
|
||||
#define IMXRT_GPIO_IRQ_LAST (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS)
|
||||
|
||||
/* Total number of IRQ numbers **********************************************************/
|
||||
|
||||
#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************************/
|
||||
|
||||
/****************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT106X_IRQ_H */
|
||||
@ -2,7 +2,8 @@
|
||||
* arch/arm/include/imxrt/irq.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -79,6 +80,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
|
||||
# include <arch/imxrt/imxrt105x_irq.h>
|
||||
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
|
||||
# include <arch/imxrt/imxrt106x_irq.h>
|
||||
#else
|
||||
# error Unrecognized i.MX RT architecture
|
||||
#endif
|
||||
|
||||
@ -28,6 +28,22 @@ config ARCH_CHIP_MIMXRT1052CVL5A
|
||||
bool "MIMXRT1052DVL6A"
|
||||
select ARCH_FAMILY_MIMXRT1052CVL5A
|
||||
|
||||
config ARCH_CHIP_MIMXRT1061DVL6A
|
||||
bool "MIMXRT1061DVL6A"
|
||||
select ARCH_FAMILY_MXRT106xDVL6A
|
||||
|
||||
config ARCH_CHIP_MIMXRT1061CVL5A
|
||||
bool "MIMXRT1061CVL5A"
|
||||
select ARCH_FAMILY_IMIMXRT106xCVL5A
|
||||
|
||||
config ARCH_CHIP_MIMXRT1062DVL6A
|
||||
bool "MIMXRT1062DVL6A"
|
||||
select ARCH_FAMILY_MXRT106xDVL6A
|
||||
|
||||
config ARCH_CHIP_MIMXRT1062CVL5A
|
||||
bool "MIMXRT1062DVL6A"
|
||||
select ARCH_FAMILY_MIMXRT1062CVL5A
|
||||
|
||||
endchoice # i.MX RT Chip Selection
|
||||
|
||||
# i.MX RT Families
|
||||
@ -56,6 +72,31 @@ config ARCH_FAMILY_IMXRT105x
|
||||
select ARMV7M_HAVE_ITCM
|
||||
select ARMV7M_HAVE_DTCM
|
||||
|
||||
config ARCH_FAMILY_MXRT106xDVL6A
|
||||
bool
|
||||
default n
|
||||
select ARCH_FAMILY_IMXRT106x
|
||||
---help---
|
||||
i.MX RT1060 Crossover Processors for Consumer Products
|
||||
|
||||
config ARCH_FAMILY_MIMXRT1062CVL5A
|
||||
bool
|
||||
default n
|
||||
select ARCH_FAMILY_IMXRT106x
|
||||
---help---
|
||||
i.MX RT1056 Crossover Processors for Industrial Products
|
||||
|
||||
config ARCH_FAMILY_IMXRT106x
|
||||
bool
|
||||
default n
|
||||
select ARCH_HAVE_FPU
|
||||
select ARCH_HAVE_DPFPU # REVISIT
|
||||
select ARMV7M_HAVE_ICACHE
|
||||
select ARMV7M_HAVE_DCACHE
|
||||
select ARMV7M_HAVE_ITCM
|
||||
select ARMV7M_HAVE_DTCM
|
||||
select IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
# Peripheral support
|
||||
|
||||
config IMXRT_HAVE_LPUART
|
||||
@ -70,6 +111,10 @@ config IMXRT_LPSPI
|
||||
bool
|
||||
default n
|
||||
|
||||
config IMXRT_HIGHSPEED_GPIO
|
||||
bool
|
||||
default n
|
||||
|
||||
menu "i.MX RT Peripheral Selection"
|
||||
|
||||
config IMXRT_EDMA
|
||||
@ -327,6 +372,46 @@ config IMXRT_GPIO5_16_31_IRQ
|
||||
bool "GPIO5 Pins 16-31 interrupts"
|
||||
default n
|
||||
|
||||
config IMXRT_GPIO6_0_15_IRQ
|
||||
bool "GPIO6 Pins 8-15 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO6_16_31_IRQ
|
||||
bool "GPIO6 Pins 16-31 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO7_0_15_IRQ
|
||||
bool "GPIO7 Pins 0-15 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO7_16_31_IRQ
|
||||
bool "GPIO7 Pins 16-31 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO8_0_15_IRQ
|
||||
bool "GPIO8 Pins 0-15 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO8_16_31_IRQ
|
||||
bool "GPIO8 Pins 16-31 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO9_0_15_IRQ
|
||||
bool "GPIO9 Pins 0-15 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
config IMXRT_GPIO9_16_31_IRQ
|
||||
bool "GPIO9 Pins 16-31 interrupts"
|
||||
default n
|
||||
depends on IMXRT_HIGHSPEED_GPIO
|
||||
|
||||
endif # IMXRT_GPIO_IRQ
|
||||
|
||||
menu "Ethernet Configuration"
|
||||
@ -446,7 +531,7 @@ config IMXRT_BOOT_SRAM
|
||||
endchoice # i.MX RT Boot Configuration
|
||||
|
||||
choice
|
||||
prompt "i.MX6 Primary RAM"
|
||||
prompt "i.MX RT Primary RAM"
|
||||
default IMXRT_OCRAM_PRIMARY
|
||||
---help---
|
||||
The primary RAM is the RAM that contains the system BLOB's .data and
|
||||
@ -464,7 +549,7 @@ config IMXRT_SRAM_PRIMARY
|
||||
bool "External SRAM primary"
|
||||
depends on IMXRT_SEMC_SRAM
|
||||
|
||||
endchoice # i.MX6 Primary RAM
|
||||
endchoice # i.MX RT Primary RAM
|
||||
|
||||
menu "i.MX RT Heap Configuration"
|
||||
|
||||
@ -512,7 +597,7 @@ config IMXRT_SRAM_HEAPOFFSET
|
||||
Used to reserve memory at the beginning of SRAM for, as an example,
|
||||
a framebuffer.
|
||||
|
||||
endmenu # i.MX6 Primary RAM
|
||||
endmenu # i.MX RT Heap Configuration
|
||||
endmenu # Memory Configuration
|
||||
|
||||
menu "USDHC Configuration"
|
||||
|
||||
127
arch/arm/src/imxrt/chip/imxrt105x_gpio.h
Normal file
127
arch/arm/src/imxrt/chip/imxrt105x_gpio.h
Normal file
@ -0,0 +1,127 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/imxrt/imxrt105x_gpio.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/imxrt_memorymap.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
|
||||
#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */
|
||||
#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */
|
||||
#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */
|
||||
#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */
|
||||
#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */
|
||||
#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */
|
||||
#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */
|
||||
#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */
|
||||
#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */
|
||||
#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */
|
||||
#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H */
|
||||
1991
arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h
Normal file
1991
arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -54,7 +54,7 @@
|
||||
#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */
|
||||
/* 0x00218000 416KB ROMCP Reserved */
|
||||
/* 0x00280000 1536KB Reserved */
|
||||
/* 0x00400000 128MB Reserved */
|
||||
/* 0x00400000 124MB Reserved */
|
||||
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
|
||||
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
|
||||
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
|
||||
|
||||
174
arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
Normal file
174
arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
Normal file
@ -0,0 +1,174 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/imxrt/chip/imxrt106x_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Preprocessor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Peripheral DMA request channels */
|
||||
|
||||
#define IMXRT_DMACHAN_FLEXIO1 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
|
||||
#define IMXRT_DMACHAN_FLEXIO2 1 /* FlexIO1 DMA 0/1, Async DMA 0/1 */
|
||||
#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_CAN3 11 /* FLEXCAN3 DMA */
|
||||
#define IMXRT_DMACHAN_CSI 12 /* CSI Write DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */
|
||||
#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */
|
||||
#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */
|
||||
#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */
|
||||
#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */
|
||||
#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_RX0 40 /* FlexPWM3 RX sub-module0 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */
|
||||
#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */
|
||||
#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */
|
||||
#define IMXRT_DMACHAN_QTIMER3_RXTX0 56 /* QTimer1 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */
|
||||
#define IMXRT_DMACHAN_QTIMER3_RXTX1 57 /* QTimer1 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */
|
||||
#define IMXRT_DMACHAN_QTIMER3_RXTX2 58 /* QTimer1 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */
|
||||
#define IMXRT_DMACHAN_QTIMER3_RXTX3 59 /* QTimer1 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */
|
||||
#define IMXRT_DMACHAN_FLEXSPI2_RX 60 /* FlexSPI2 RX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_FLEXSPI2_TX 61 /* FlexSPI2 TX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_FLEXIO1_01 64 /* FlexIO1 DMA 0 / Async DMA 0 / DMA 1 / Async DMA 1 */
|
||||
#define IMXRT_DMACHAN_FLEXIO2_23 65 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */
|
||||
#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_PXP 75 /* PXP DMA Event */
|
||||
#define IMXRT_DMACHAN_LCDIF 76 /* LCDIF DMA Event */
|
||||
#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */
|
||||
#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */
|
||||
#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */
|
||||
#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */
|
||||
#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */
|
||||
#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */
|
||||
#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */
|
||||
#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */
|
||||
#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */
|
||||
#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */
|
||||
#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_RX0 104 /* FlexPWM4 RX sub-module0 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_RX1 105 /* FlexPWM4 RX sub-module1 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_RX2 106 /* FlexPWM4 RX sub-module2 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_RX3 107 /* FlexPWM4 RX sub-module3 capture */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_TX0 108 /* FlexPWM4 TX sub-module0 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_TX1 109 /* FlexPWM4 TX sub-module1 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_TX2 110 /* FlexPWM4 TX sub-module2 value */
|
||||
#define IMXRT_DMACHAN_FLEXPWM4_TX3 111 /* FlexPWM4 TX sub-module3 value */
|
||||
#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */
|
||||
#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */
|
||||
#define IMXRT_DMACHAN_QTIMER4_RXTX0 120 /* QTimer4 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */
|
||||
#define IMXRT_DMACHAN_QTIMER4_RXTX1 121 /* QTimer4 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */
|
||||
#define IMXRT_DMACHAN_QTIMER4_RXTX2 122 /* QTimer4 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */
|
||||
#define IMXRT_DMACHAN_QTIMER4_RXTX3 123 /* QTimer4 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */
|
||||
#define IMXRT_DMACHAN_ENET2_0 124 /* ENET2 Timer DMA 0 */
|
||||
#define IMXRT_DMACHAN_ENET2_1 125 /* ENET2 Timer DMA 1 */
|
||||
|
||||
#define IMXRT_DMA_NCHANNLES 128 /* Includes reserved channels */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H */
|
||||
175
arch/arm/src/imxrt/chip/imxrt106x_gpio.h
Normal file
175
arch/arm/src/imxrt/chip/imxrt106x_gpio.h
Normal file
@ -0,0 +1,175 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/imxrt/imxrt106x_gpio.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/imxrt_memorymap.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
|
||||
#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */
|
||||
#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */
|
||||
#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */
|
||||
#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */
|
||||
#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */
|
||||
#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */
|
||||
#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */
|
||||
#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */
|
||||
#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */
|
||||
#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */
|
||||
#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
# define IMXRT_GPIO6_DR (IMXRT_GPIO6_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
# define IMXRT_GPIO6_GDIR (IMXRT_GPIO6_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
# define IMXRT_GPIO6_PSR (IMXRT_GPIO6_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
# define IMXRT_GPIO6_ICR1 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
# define IMXRT_GPIO6_ICR2 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
# define IMXRT_GPIO6_IMR (IMXRT_GPIO6_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
# define IMXRT_GPIO6_ISR (IMXRT_GPIO6_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
# define IMXRT_GPIO6_EDGE (IMXRT_GPIO6_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
# define IMXRT_GPIO6_SET (IMXRT_GPIO6_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
# define IMXRT_GPIO6_CLEAR (IMXRT_GPIO6_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
# define IMXRT_GPIO6_TOGGLE (IMXRT_GPIO6_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
# define IMXRT_GPIO7_DR (IMXRT_GPIO7_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
# define IMXRT_GPIO7_GDIR (IMXRT_GPIO7_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
# define IMXRT_GPIO7_PSR (IMXRT_GPIO7_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
# define IMXRT_GPIO7_ICR1 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
# define IMXRT_GPIO7_ICR2 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
# define IMXRT_GPIO7_IMR (IMXRT_GPIO7_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
# define IMXRT_GPIO7_ISR (IMXRT_GPIO7_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
# define IMXRT_GPIO7_EDGE (IMXRT_GPIO7_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
# define IMXRT_GPIO7_SET (IMXRT_GPIO7_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
# define IMXRT_GPIO7_CLEAR (IMXRT_GPIO7_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
# define IMXRT_GPIO7_TOGGLE (IMXRT_GPIO7_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
# define IMXRT_GPIO8_DR (IMXRT_GPIO8_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
# define IMXRT_GPIO8_GDIR (IMXRT_GPIO8_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
# define IMXRT_GPIO8_PSR (IMXRT_GPIO8_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
# define IMXRT_GPIO8_ICR1 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
# define IMXRT_GPIO8_ICR2 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
# define IMXRT_GPIO8_IMR (IMXRT_GPIO8_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
# define IMXRT_GPIO8_ISR (IMXRT_GPIO8_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
# define IMXRT_GPIO8_EDGE (IMXRT_GPIO8_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
# define IMXRT_GPIO8_SET (IMXRT_GPIO8_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
# define IMXRT_GPIO8_CLEAR (IMXRT_GPIO8_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
# define IMXRT_GPIO8_TOGGLE (IMXRT_GPIO8_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
# define IMXRT_GPIO9_DR (IMXRT_GPIO9_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
# define IMXRT_GPIO9_GDIR (IMXRT_GPIO9_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
# define IMXRT_GPIO9_PSR (IMXRT_GPIO9_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
# define IMXRT_GPIO9_ICR1 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
# define IMXRT_GPIO9_ICR2 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
# define IMXRT_GPIO9_IMR (IMXRT_GPIO9_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
# define IMXRT_GPIO9_ISR (IMXRT_GPIO9_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
# define IMXRT_GPIO9_EDGE (IMXRT_GPIO9_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
# define IMXRT_GPIO9_SET (IMXRT_GPIO9_BASE + IMXRT_GPIO_SET_OFFSET)
|
||||
# define IMXRT_GPIO9_CLEAR (IMXRT_GPIO9_BASE + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
# define IMXRT_GPIO9_TOGGLE (IMXRT_GPIO9_BASE + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H */
|
||||
2543
arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h
Normal file
2543
arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h
Normal file
File diff suppressed because it is too large
Load Diff
301
arch/arm/src/imxrt/chip/imxrt106x_memorymap.h
Normal file
301
arch/arm/src/imxrt/chip/imxrt106x_memorymap.h
Normal file
@ -0,0 +1,301 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/imxrt/chip/imxrt105x_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* System memory map */
|
||||
|
||||
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
|
||||
/* 0x00080000 512KB ITCM Reserved */
|
||||
/* 0x00100000 1MB ITCM Reserved */
|
||||
#define IMXRT_ROMCP_BASE 0x00200000 /* 128KB ROMCP */
|
||||
/* 0x00220000 384KB ROMCP Reserved */
|
||||
/* 0x00280000 1536KB Reserved */
|
||||
/* 0x00400000 124MB Reserved */
|
||||
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
|
||||
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
|
||||
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
|
||||
/* 0x20080000 512KB DTCM Reserved */
|
||||
/* 0x20100000 1MB Reserved */
|
||||
#define IMXRT_OCRAM2_BASE 0x20200000 /* 512KB OCRAM2 */
|
||||
#define IMXRT_OCRAM_BASE 0x20280000 /* 512KB OCRAM FlexRAM */
|
||||
/* 0x20300000 512KB OCRAM Reserved */
|
||||
/* 0x20400000 252MB Reserved */
|
||||
/* 0x30000000 256MB Reserved */
|
||||
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
|
||||
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
|
||||
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
|
||||
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
|
||||
/* 40400000 12MB Reserved */
|
||||
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
|
||||
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
|
||||
/* 41200000 1MB Reserved for "per" GPV */
|
||||
/* 41300000 1MB Reserved for "ems" GPV */
|
||||
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
|
||||
/* 0x41500000 1MB GPV Reserved */
|
||||
/* 0x41600000 1MB GPV Reserved */
|
||||
/* 0x41700000 1MB GPV Reserved */
|
||||
/* 0x41800000 8MB Reserved */
|
||||
#define IMXRT_AIPS5_BASE 0x42000000 /* 1MB AIPS-5 */
|
||||
/* 0x42100000 31MB Reserved */
|
||||
/* 0x44000000 64MB Reserved */
|
||||
/* 0x48000000 384MB Reserved */
|
||||
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 256MB FlexSPI/ FlexSPI ciphertext */
|
||||
#define IMXRT_FLEX2CIPHER_BASE 0x70000000 /* 240MB FlexSPI2/ FlexSPI ciphertext */
|
||||
#define IMXRT_FLEXSPI2TX_BASE 0x7f000000 /* 4MB FlexSPI2 TX FIFO */
|
||||
#define IMXRT_FLEXSPI2RX_BASE 0x7f400000 /* 4MB FlexSPI2 RX FIFO */
|
||||
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
|
||||
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
|
||||
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
|
||||
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
|
||||
/* 0xe0100000 511MB Reserved */
|
||||
|
||||
/* AIPS-1 memory map */
|
||||
|
||||
/* 0x40000000 256KB Reserved */
|
||||
/* 0x40040000 240KB Reserved */
|
||||
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
|
||||
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
|
||||
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
|
||||
/* 0x40088000 16KB Reserved */
|
||||
/* 0x4008c000 16KB Reserved */
|
||||
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
|
||||
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
|
||||
/* 0x40098000 16KB Reserved */
|
||||
/* 0x4009c000 16KB Reserved */
|
||||
/* 0x400a0000 16KB Reserved */
|
||||
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
|
||||
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
|
||||
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
|
||||
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */
|
||||
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
|
||||
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
|
||||
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
|
||||
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
|
||||
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
|
||||
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
|
||||
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
|
||||
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
|
||||
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
|
||||
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
|
||||
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
|
||||
/* 0x400e0000 16KB Reserved */
|
||||
/* 0x400e4000 16KB Reserved */
|
||||
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
|
||||
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
|
||||
/* 400f0000 16KB Reserved */
|
||||
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
|
||||
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
|
||||
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
|
||||
|
||||
/* AIPS-2 memory map */
|
||||
|
||||
/* 0x40100000 256KB Reserved */
|
||||
/* 0x40140000 240KB Reserved */
|
||||
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
|
||||
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
|
||||
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
|
||||
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
|
||||
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
|
||||
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
|
||||
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
|
||||
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
|
||||
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
|
||||
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
|
||||
/* 0x401a4000 16KB Reserved */
|
||||
/* 0x401a8000 16KB Reserved */
|
||||
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
|
||||
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
|
||||
/* 0x401b4000 16KB Reserved */
|
||||
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
|
||||
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
|
||||
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
|
||||
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
|
||||
/* 0x401c8000 16KB Reserved */
|
||||
/* 0x401cc000 16KB Reserved */
|
||||
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
|
||||
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
|
||||
#define IMXRT_CAN3_BASE 0x401d8000 /* 16KB CAN3 */
|
||||
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
|
||||
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
|
||||
#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */
|
||||
#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */
|
||||
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
|
||||
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
|
||||
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
|
||||
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
|
||||
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
|
||||
|
||||
/* AIPS-3 memory map */
|
||||
|
||||
/* 0x40200000 256KB Reserved */
|
||||
/* 0x40240000 240KB Reserved */
|
||||
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
|
||||
/* 0x40280000 16KB Reserved */
|
||||
/* 0x40284000 16KB Reserved */
|
||||
/* 0x40288000 16KB Reserved */
|
||||
/* 0x4028c000 16KB Reserved */
|
||||
/* 0x40290000 16KB Reserved */
|
||||
/* 0x40294000 16KB Reserved */
|
||||
/* 0x40298000 16KB Reserved */
|
||||
/* 0x4029c000 16KB Reserved */
|
||||
/* 0x402a0000 16KB Reserved */
|
||||
#define IMXRT_FLEXSPI2C_BASE 0x402a4000 /* 16KB FlexSPI2 */
|
||||
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI */
|
||||
/* 0x402ac000 16KB Reserved */
|
||||
/* 0x402b0000 16KB Reserved */
|
||||
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
|
||||
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
|
||||
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
|
||||
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
|
||||
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
|
||||
/* 0x402c8000 16KB Reserved */
|
||||
/* 0x402cc000 16KB Reserved */
|
||||
/* 0x402d0000 16KB Reserved */
|
||||
/* 0x402d4000 16KB Reserved */
|
||||
#define IMXRT_ENET2_BASE 0x402d4000 /* 16KB ENET2 */
|
||||
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
|
||||
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
|
||||
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */
|
||||
/* 0x402e4000 16KB Reserved */
|
||||
/* 0x402e8000 16KB Reserved */
|
||||
/* 0x402ec000 16KB Reserved */
|
||||
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
|
||||
/* 0x402f4000 16KB Reserved */
|
||||
/* 0x402f8000 16KB Reserved */
|
||||
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
|
||||
|
||||
/* AIPS-4 memory map */
|
||||
|
||||
/* 0x40300000 256KB Reserved */
|
||||
/* 0x40340000 240KB Reserved */
|
||||
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
|
||||
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
|
||||
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
|
||||
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
|
||||
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
|
||||
/* 0x40390000 16KB Reserved */
|
||||
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
|
||||
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
|
||||
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
|
||||
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
|
||||
/* 0x403a4000 16KB Reserved */
|
||||
/* 0x403a8000 16KB Reserved */
|
||||
/* 0x403ac000 16KB Reserved */
|
||||
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
|
||||
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
|
||||
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
|
||||
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
|
||||
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
|
||||
#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */
|
||||
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
|
||||
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
|
||||
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
|
||||
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
|
||||
/* 0x403d8000 16KB Reserved */
|
||||
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
|
||||
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
|
||||
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
|
||||
#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */
|
||||
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
|
||||
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
|
||||
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
|
||||
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
|
||||
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
|
||||
|
||||
/* AIPS-5 memory map */
|
||||
|
||||
#define IMXRT_GPIO6_BASE 0x42000000 /* 16KB GPIO6 */
|
||||
#define IMXRT_GPIO7_BASE 0x42004000 /* 16KB GPIO7 */
|
||||
#define IMXRT_GPIO8_BASE 0x42008000 /* 16KB GPIO8 */
|
||||
#define IMXRT_GPIO9_BASE 0x4200c000 /* 16KB GPIO9 */
|
||||
/* 0x42010000 16KB Reserved */
|
||||
/* 0x42014000 16KB Reserved */
|
||||
/* 0x42018000 16KB Reserved */
|
||||
/* 0x4201c000 16KB Reserved */
|
||||
#define IMXRT_FLEXIO3_BASE 0x42020000 /* 16KB FlexIO3 */
|
||||
/* 0x42024000 16KB Reserved */
|
||||
/* 0x42028000 16KB Reserved */
|
||||
/* 0x4202c000 16KB Reserved */
|
||||
/* 0x42030000 16KB Reserved */
|
||||
/* 0x42034000 16KB Reserved */
|
||||
/* 0x42038000 16KB Reserved */
|
||||
/* 0x4203c000 16KB Reserved */
|
||||
/* 0x42040000 16KB Reserved */
|
||||
/* 0x42044000 16KB Reserved */
|
||||
/* 0x42048000 16KB Reserved */
|
||||
/* 0x4204c000 16KB Reserved */
|
||||
/* 0x42050000 16KB Reserved */
|
||||
/* 0x42054000 16KB Reserved */
|
||||
/* 0x42058000 16KB Reserved */
|
||||
/* 0x4205c000 16KB Reserved */
|
||||
/* 0x42060000 16KB Reserved */
|
||||
/* 0x42064000 16KB Reserved */
|
||||
/* 0x42068000 16KB Reserved */
|
||||
/* 0x4206c000 16KB Reserved */
|
||||
/* 0x42070000 16KB Reserved */
|
||||
/* 0x42074000 16KB Reserved */
|
||||
/* 0x42078000 16KB Reserved */
|
||||
/* 0x4207c000 16KB Reserved */
|
||||
/* 0x42080000 512KB Reserved Off Platform */
|
||||
|
||||
/* PPB memory map */
|
||||
|
||||
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
|
||||
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
|
||||
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
|
||||
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
|
||||
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
|
||||
/* 0xe0045000 236KB PPB Reserved */
|
||||
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
|
||||
/* 0xe0081000 444KB PPB Reserved */
|
||||
/* 0xe00f0000 52KB PPB Reserved */
|
||||
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
|
||||
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
|
||||
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H */
|
||||
1088
arch/arm/src/imxrt/chip/imxrt106x_pinmux.h
Normal file
1088
arch/arm/src/imxrt/chip/imxrt106x_pinmux.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,8 @@
|
||||
* arch/arm/src/imxrt/chip/imxrt_dmamux.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -45,6 +46,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
|
||||
# include "chip/imxrt105x_dmamux.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
|
||||
# include "chip/imxrt106x_dmamux.h"
|
||||
#else
|
||||
# error Unrecognized i.MX RT architecture
|
||||
#endif
|
||||
|
||||
@ -2,7 +2,8 @@
|
||||
* arch/arm/src/imxrt/imxrt_gpio.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -41,7 +42,14 @@
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/imxrt_memorymap.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
|
||||
# include "chip/imxrt105x_gpio.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
|
||||
# include "chip/imxrt106x_gpio.h"
|
||||
#else
|
||||
# error Unrecognized i.MX RT architecture
|
||||
#endif
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -52,68 +60,14 @@
|
||||
#define GPIO3 2 /* Port 3 index */
|
||||
#define GPIO4 3 /* Port 4 index */
|
||||
#define GPIO5 4 /* Port 5 index */
|
||||
|
||||
#define IMXRT_GPIO_NPORTS 5 /* Five total ports */
|
||||
#if IMXRT_GPIO_NPORTS > 5
|
||||
#define GPIO6 5 /* Port 6 index */
|
||||
#define GPIO7 6 /* Port 7 index */
|
||||
#define GPIO8 7 /* Port 8 index */
|
||||
#define GPIO9 8 /* Port 9 index */
|
||||
#endif
|
||||
#define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
|
||||
#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */
|
||||
#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */
|
||||
#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */
|
||||
#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */
|
||||
#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */
|
||||
#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */
|
||||
#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */
|
||||
#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
|
||||
#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET)
|
||||
#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET)
|
||||
#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET)
|
||||
#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET)
|
||||
#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET)
|
||||
|
||||
/* Register bit definitions *****************************************************************/
|
||||
|
||||
/* Most registers are laid out simply with one bit per pin */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -44,6 +44,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
|
||||
# include "chip/imxrt105x_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
|
||||
# include "chip/imxrt106x_memorymap.h"
|
||||
#else
|
||||
# error Unrecognized i.MX RT architecture
|
||||
#endif
|
||||
|
||||
@ -2,7 +2,8 @@
|
||||
* arch/arm/src/imxrt/chip/imxrt_pinmux.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -44,6 +45,8 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_IMXRT105x)
|
||||
# include "chip/imxrt105x_pinmux.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x)
|
||||
# include "chip/imxrt106x_pinmux.h"
|
||||
#else
|
||||
# error Unrecognized i.MX RT architecture
|
||||
#endif
|
||||
|
||||
@ -96,13 +96,19 @@
|
||||
* banks. This logic assumes that there is at most one of each (or at least
|
||||
* only one contiguous block of addresses for each). This would need to
|
||||
* be exceed considerably to support multiple SDRAM or SRAM memory regions.
|
||||
*
|
||||
* SOC with 512KiB
|
||||
*
|
||||
* IMXRT_DTCM_BASE 0x20000000 512KB DTCM
|
||||
* 0x20080000 512KB DTCM Reserved
|
||||
* 0x20100000 1MB Reserved
|
||||
* IMXRT_OCRAM_BASE 0x20200000 512KB OCRAM
|
||||
*
|
||||
* SOC with 1MiB
|
||||
* IMXRT_OCRAM2_BASE 0x20200000 512KB OCRAM2
|
||||
* IMXRT_OCRAM_BASE 0x20280000 512KB OCRAM FlexRAM
|
||||
*/
|
||||
|
||||
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
|
||||
/* 0x20080000 512KB DTCM Reserved */
|
||||
/* 0x20100000 1MB Reserved */
|
||||
#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */
|
||||
|
||||
/* There there then several memory configurations with a one primary memory
|
||||
* region and up to two additional memory regions which may be OCRAM,
|
||||
* external SDRAM, or external SRAM.
|
||||
@ -114,10 +120,21 @@
|
||||
|
||||
/* REVISIT: Assume that if OCRAM is the primary RAM, then DTCM and ITCM are
|
||||
* not being used.
|
||||
* When configured DTCM and ITCM consume OCRAM from the address space
|
||||
* labeled IMXRT_OCRAM_BASE that uses the FlexRAM controller to allocate
|
||||
* the function of OCRAM.
|
||||
*
|
||||
* The 1 MB version of the SOC have a second 512Kib of OCRAM that can not
|
||||
* be consumed by the DTCM or ITCM.
|
||||
*/
|
||||
|
||||
#if defined(IMXRT_OCRAM2_BASE)
|
||||
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE
|
||||
#else
|
||||
# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_OCRAM_PRIMARY)
|
||||
# define PRIMARY_RAM_START IMXRT_OCRAM_BASE /* CONFIG_RAM_START */
|
||||
# define PRIMARY_RAM_START _IMXRT_OCRAM_BASE /* CONFIG_RAM_START */
|
||||
# define PRIMARY_RAM_SIZE IMXRT_OCRAM_SIZE /* CONFIG_RAM_SIZE */
|
||||
# define IMXRT_OCRAM_ASSIGNED 1
|
||||
#elif defined(CONFIG_IMXRT_SDRAM_PRIMARY)
|
||||
@ -137,12 +154,16 @@
|
||||
/* REVISIT: I am not sure how this works. But I am assuming that if DTCM
|
||||
* is enabled, then ITCM is not and we can just use the DTCM base address to
|
||||
* access OCRAM.
|
||||
*
|
||||
* The FlexRAM controller manages the allocation of DTCM and ITCM from the
|
||||
* OCRAM. The amount allocated it 2^n KiB where n is 2-9 and is configured in
|
||||
* the GPR register space.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_IMXRT_DTCM
|
||||
# define IMXRT_OCRAM_START IMXRT_DTCM_BASE
|
||||
#else
|
||||
# define IMXRT_OCRAM_START IMXRT_OCRAM_BASE
|
||||
# define IMXRT_OCRAM_START _IMXRT_OCRAM_BASE
|
||||
#endif
|
||||
|
||||
#if CONFIG_MM_REGIONS > 1
|
||||
|
||||
@ -46,7 +46,7 @@
|
||||
#include "chip/imxrt_ccm.h"
|
||||
#include "chip/imxrt_dcdc.h"
|
||||
#include "imxrt_clockconfig.h"
|
||||
#include "chip/imxrt105x_memorymap.h"
|
||||
#include "chip/imxrt_memorymap.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
|
||||
@ -263,6 +263,12 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
|
||||
g_gpio3_padmux, /* GPIO3 */
|
||||
g_gpio4_padmux, /* GPIO4 */
|
||||
g_gpio5_padmux, /* GPIO5 */
|
||||
#if IMXRT_GPIO_NPORTS > 5
|
||||
g_gpio1_padmux, /* GPIO6 */
|
||||
g_gpio2_padmux, /* GPIO7 */
|
||||
g_gpio3_padmux, /* GPIO8 */
|
||||
g_gpio4_padmux, /* GPIO9 */
|
||||
#endif
|
||||
NULL /* End of list */
|
||||
};
|
||||
|
||||
@ -270,7 +276,7 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] =
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */
|
||||
/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base addresses */
|
||||
|
||||
uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] =
|
||||
{
|
||||
@ -287,6 +293,18 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] =
|
||||
#if IMXRT_GPIO_NPORTS > 4
|
||||
, IMXRT_GPIO5_BASE
|
||||
#endif
|
||||
#if IMXRT_GPIO_NPORTS > 5
|
||||
, IMXRT_GPIO6_BASE
|
||||
#endif
|
||||
#if IMXRT_GPIO_NPORTS > 6
|
||||
, IMXRT_GPIO7_BASE
|
||||
#endif
|
||||
#if IMXRT_GPIO_NPORTS > 7
|
||||
, IMXRT_GPIO8_BASE
|
||||
#endif
|
||||
#if IMXRT_GPIO_NPORTS > 8
|
||||
, IMXRT_GPIO9_BASE
|
||||
#endif
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -299,6 +317,12 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] =
|
||||
|
||||
static uintptr_t imxrt_padmux_address(unsigned int index)
|
||||
{
|
||||
#if defined(IMXRT_PAD1MUX_OFFSET)
|
||||
if (index >= IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX)
|
||||
{
|
||||
return (IMXRT_PAD1MUX_OFFSET(index - IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX));
|
||||
}
|
||||
#endif
|
||||
if (index >= IMXRT_PADMUX_WAKEUP_INDEX)
|
||||
{
|
||||
return (IMXRT_PADMUX_ADDRESS_SNVS(index - IMXRT_PADMUX_WAKEUP_INDEX));
|
||||
@ -313,6 +337,12 @@ static uintptr_t imxrt_padmux_address(unsigned int index)
|
||||
|
||||
static uintptr_t imxrt_padctl_address(unsigned int index)
|
||||
{
|
||||
#if defined(IMXRT_PAD1CTL_OFFSET)
|
||||
if (index >= IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX)
|
||||
{
|
||||
return (IMXRT_PAD1CTL_OFFSET(index - IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX));
|
||||
}
|
||||
#endif
|
||||
if (index >= IMXRT_PADCTL_WAKEUP_INDEX)
|
||||
{
|
||||
return (IMXRT_PADCTL_ADDRESS_SNVS(index - IMXRT_PADCTL_WAKEUP_INDEX));
|
||||
@ -378,6 +408,51 @@ static inline bool imxrt_gpio_getinput(int port, int pin)
|
||||
return ((regval & GPIO_PIN(pin)) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_gpio_select
|
||||
* GPIO{1234}(l) and GPIO{6789}(h) share same IO MUX function, GPIO_MUXn
|
||||
* selects one GPIO function.
|
||||
* 0: GPIOl[n] is selected
|
||||
* 1: GPIOh[n] is selected
|
||||
****************************************************************************/
|
||||
|
||||
static inline int imxrt_gpio_select(int port, int pin)
|
||||
{
|
||||
#if IMXRT_GPIO_NPORTS > 5
|
||||
uint32_t gpr = port;
|
||||
uint32_t setbits = 1 << pin;
|
||||
uint32_t clearbits = 1 << pin;
|
||||
uintptr_t regaddr = (uintptr_t) IMXRT_IOMUXC_GPR_GPR26;
|
||||
|
||||
if (port != GPIO5)
|
||||
{
|
||||
/* Uses GPR26 as the base */
|
||||
|
||||
if (port >= GPIO6)
|
||||
{
|
||||
/* Map port to correct gpr index and set the GPIO_MUX3_GPIO[b]_SEL
|
||||
* bit
|
||||
*/
|
||||
|
||||
gpr = port - GPIO6;
|
||||
clearbits = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The port is correct gpr index, so just clear the
|
||||
* GPIO_MUX3_GPIO[b]_SEL bit.
|
||||
*/
|
||||
|
||||
setbits = 0;
|
||||
}
|
||||
|
||||
regaddr |= gpr * sizeof(uint32_t);
|
||||
modifyreg32(regaddr, clearbits, setbits);
|
||||
}
|
||||
#endif
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imxrt_gpio_configinput
|
||||
****************************************************************************/
|
||||
@ -410,10 +485,11 @@ static int imxrt_gpio_configinput(gpio_pinset_t pinset)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
regaddr = imxrt_padmux_address(index);
|
||||
putreg32(PADMUX_MUXMODE_ALT5, regaddr);
|
||||
|
||||
imxrt_gpio_select(port, pin);
|
||||
|
||||
/* Configure pin pad settings */
|
||||
|
||||
index = imxrt_padmux_map(index);
|
||||
|
||||
@ -2,7 +2,8 @@
|
||||
* arch/arm/src/imxrt/imxrt_gpio.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -45,6 +46,7 @@
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/imxrt_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
@ -53,14 +55,19 @@
|
||||
|
||||
/* 32-bit Encoding:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM
|
||||
* GPIO INPUT 00.. ..EE .GGP PPPP MMMM MMMM MMMM MMMM
|
||||
* GPIO OUTPUT 01V. .S.. .GGP PPPP MMMM MMMM MMMM MMMM
|
||||
* PERIPHERAL 10AA AS.. IIII IIII MMMM MMMM MMMM MMMM
|
||||
* GPIO INPUT 00.. .EEG GGGP PPPP MMMM MMMM MMMM MMMM
|
||||
* INT INPUT 11.. .EEG GGGP PPPP MMMM MMMM MMMM MMMM
|
||||
* GPIO OUTPUT 01V. ..SG GGGP PPPP MMMM MMMM MMMM MMMM
|
||||
* PERIPHERAL 10AA AAS. IIII IIII MMMM MMMM MMMM MMMM
|
||||
*/
|
||||
|
||||
/* Input/Output Selection:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ENCODING II.. .... .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
@ -81,20 +88,29 @@
|
||||
|
||||
/* GPIO Port Number
|
||||
*
|
||||
* GPIO INPUT 00.. .... .GG. .... .... .... .... ....
|
||||
* GPIO OUTPUT 01.. .... .GG. .... .... .... .... ....
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* GPIO INPUT 00.. ...G GGG. .... .... .... .... ....
|
||||
* GPIO OUTPUT 01.. ...G GGG. .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */
|
||||
#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
|
||||
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */
|
||||
# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */
|
||||
# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */
|
||||
# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */
|
||||
# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO4 */
|
||||
|
||||
# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */
|
||||
#if IMXRT_GPIO_NPORTS > 5
|
||||
# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */
|
||||
# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */
|
||||
# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */
|
||||
# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */
|
||||
#endif
|
||||
/* GPIO Pin Number:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* GPIO INPUT 00.. .... ...P PPPP .... .... .... ....
|
||||
* GPIO OUTPUT 01.. .... ...P PPPP .... .... .... ....
|
||||
*/
|
||||
@ -136,11 +152,13 @@
|
||||
|
||||
/* Peripheral Alternate Function:
|
||||
*
|
||||
* PERIPHERAL ..AA A... .... .... .... .... .... ....
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* PERIPHERAL ..AA AA.. .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_ALT_SHIFT (27) /* Bits 27-29: Peripheral alternate function */
|
||||
#define GPIO_ALT_MASK (7 << GPIO_ALT_SHIFT)
|
||||
#define GPIO_ALT_SHIFT (26) /* Bits 26-29: Peripheral alternate function */
|
||||
#define GPIO_ALT_MASK (0xf << GPIO_ALT_SHIFT)
|
||||
# define GPIO_ALT0 (0 << GPIO_ALT_SHIFT) /* Alternate function 0 */
|
||||
# define GPIO_ALT1 (1 << GPIO_ALT_SHIFT) /* Alternate function 1 */
|
||||
# define GPIO_ALT2 (2 << GPIO_ALT_SHIFT) /* Alternate function 2 */
|
||||
@ -149,22 +167,28 @@
|
||||
/* Alternate function 5 is GPIO */
|
||||
# define GPIO_ALT6 (6 << GPIO_ALT_SHIFT) /* Alternate function 6 */
|
||||
# define GPIO_ALT7 (7 << GPIO_ALT_SHIFT) /* Alternate function 7 */
|
||||
# define GPIO_ALT8 (8 << GPIO_ALT_SHIFT) /* Alternate function 8 */
|
||||
# define GPIO_ALT9 (9 << GPIO_ALT_SHIFT) /* Alternate function 9 */
|
||||
|
||||
/* Peripheral Software Input On Field:
|
||||
*
|
||||
* PERIPHERAL .... .S.. .... .... .... .... .... ....
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* PERIPHERAL .... ..S. .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_SION_SHIFT (26) /* Bits 26: Peripheral SION function */
|
||||
#define GPIO_SION_SHIFT (25) /* Bits 25: Peripheral SION function */
|
||||
#define GPIO_SION_MASK (1 << GPIO_SION_SHIFT)
|
||||
# define GPIO_SION_ENABLE (1 << GPIO_SION_SHIFT) /* enable SION */
|
||||
|
||||
/* Interrupt edge/level configuration
|
||||
*
|
||||
* GPIO INPUT ... ..EE .... .... .... .... .... ....
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* INT INPUT 11.. .EE. .... .... .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_INTCFG_SHIFT (24) /* Bits 24-25: Interrupt edge/level configuration */
|
||||
#define GPIO_INTCFG_SHIFT (25) /* Bits 25-26: Interrupt edge/level configuration */
|
||||
#define GPIO_INTCFG_MASK (3 << GPIO_INTCFG_SHIFT)
|
||||
# define GPIO_INT_LOWLEVEL (GPIO_ICR_LOWLEVEL << GPIO_INTCFG_SHIFT)
|
||||
# define GPIO_INT_HIGHLEVEL (GPIO_ICR_HIGHLEVEL << GPIO_INTCFG_SHIFT)
|
||||
@ -173,6 +197,8 @@
|
||||
|
||||
/* Pad Mux Register Index:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* PERIPHERAL .... .... IIII IIII .... .... .... ....
|
||||
*/
|
||||
|
||||
@ -182,6 +208,8 @@
|
||||
|
||||
/* IOMUX Pin Configuration:
|
||||
*
|
||||
* 3322 2222 2222 1111 1111 1100 0000 0000
|
||||
* 1098 7654 3210 9876 5432 1098 7654 3210
|
||||
* ENCODING .... .... .... .... MMMM MMMM MMMM MMMM
|
||||
*
|
||||
* See imxrt_iomuxc.h for detailed content.
|
||||
@ -192,7 +220,7 @@
|
||||
|
||||
/* Helper addressing macros */
|
||||
|
||||
#define IMXRT_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIO5 macros as indices */
|
||||
#define IMXRT_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */
|
||||
|
||||
#define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET)
|
||||
#define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET)
|
||||
@ -202,6 +230,9 @@
|
||||
#define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET)
|
||||
#define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET)
|
||||
#define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET)
|
||||
#define IMXRT_GPIO_SET(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_SET_OFFSET)
|
||||
#define IMXRT_GPIO_CLEAR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_CLEAR_OFFSET)
|
||||
#define IMXRT_GPIO_TOGGLE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_TOGGLE_OFFSET)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
@ -224,7 +255,7 @@ extern "C"
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */
|
||||
/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base addresses */
|
||||
|
||||
EXTERN uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS];
|
||||
|
||||
|
||||
@ -55,6 +55,16 @@
|
||||
|
||||
#ifdef CONFIG_IMXRT_GPIO_IRQ
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(_IMXRT_GPIO6_0_15_BASE)
|
||||
# define _IMXRT_FOLLOWS_GPIO6_16_31 _IMXRT_GPIO6_0_15_BASE
|
||||
#else
|
||||
# define _IMXRT_FOLLOWS_GPIO6_16_31 IMXRT_GPIO_IRQ_LAST
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
@ -131,8 +141,8 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ
|
||||
if (irq < IMXRT_GPIO_IRQ_LAST)
|
||||
#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ
|
||||
if (irq < _IMXRT_GPIO5_0_15_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO4_IMR;
|
||||
*pin = irq - _IMXRT_GPIO4_16_31_BASE + 16;
|
||||
@ -148,14 +158,82 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin)
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ
|
||||
if (irq < IMXRT_GPIO_IRQ_LAST)
|
||||
#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ
|
||||
if (irq < _IMXRT_FOLLOWS_GPIO6_16_31)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO5_IMR;
|
||||
*pin = irq - _IMXRT_GPIO5_16_31_BASE + 16;
|
||||
}
|
||||
else
|
||||
#endif
|
||||
|
||||
# ifdef CONFIG_IMXRT_GPIO6_0_15_IRQ
|
||||
if (irq < _IMXRT_GPIO6_16_31_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO6_IMR;
|
||||
*pin = irq - _IMXRT_GPIO6_0_15_BASE;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
# ifdef CONFIG_IMXRT_GPIO6_16_31_IRQ
|
||||
if (irq < _IMXRT_GPIO7_0_15_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO6_IMR;
|
||||
*pin = irq - _IMXRT_GPIO6_16_31_BASE + 16;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_IMXRT_GPIO7_0_15_IRQ
|
||||
if (irq < _IMXRT_GPIO7_16_31_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO7_IMR;
|
||||
*pin = irq - _IMXRT_GPIO7_0_15_BASE;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
# ifdef CONFIG_IMXRT_GPIO7_16_31_IRQ
|
||||
if (irq < _IMXRT_GPIO8_0_15_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO7_IMR;
|
||||
*pin = irq - _IMXRT_GPIO7_16_31_BASE + 16;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_IMXRT_GPIO8_0_15_IRQ
|
||||
if (irq < _IMXRT_GPIO8_16_31_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO8_IMR;
|
||||
*pin = irq - _IMXRT_GPIO8_0_15_BASE;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
# ifdef CONFIG_IMXRT_GPIO8_16_31_IRQ
|
||||
if (irq < _IMXRT_GPIO9_0_15_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO8_IMR;
|
||||
*pin = irq - _IMXRT_GPIO8_16_31_BASE + 16;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_IMXRT_GPIO9_0_15_IRQ
|
||||
if (irq < _IMXRT_GPIO9_16_31_BASE)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO9_IMR;
|
||||
*pin = irq - _IMXRT_GPIO9_0_15_BASE;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
# ifdef CONFIG_IMXRT_GPIO9_16_31_IRQ
|
||||
if (irq < IMXRT_GPIO_IRQ_LAST)
|
||||
{
|
||||
*regaddr = IMXRT_GPIO9_IMR;
|
||||
*pin = irq - _IMXRT_GPIO9_16_31_BASE + 16;
|
||||
}
|
||||
else
|
||||
# endif
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user