diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h index 1d9a95eac2..5229ab93ef 100644 --- a/arch/arm/include/imxrt/chip.h +++ b/arch/arm/include/imxrt/chip.h @@ -2,7 +2,8 @@ * arch/arm/include/imxrt/chip.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -48,18 +49,31 @@ /* Get customizations for each supported chip */ -/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz - * MIMXRT1051CVL5A - Consumer, Reduced Features, 600MHz - * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz - * MIMXRT1052CVL5A - Consumer, Full Feature, 600MHz - */ - #if defined(CONFIG_ARCH_CHIP_MIMXRT1051DVL6A) || \ defined(CONFIG_ARCH_CHIP_MIMXRT1051CVL5A) || \ defined(CONFIG_ARCH_CHIP_MIMXRT1052DVL6A) || \ defined(CONFIG_ARCH_CHIP_MIMXRT1052CVL5A) +/* MIMXRT1051CVL5A - Industrial, Reduced Features, 528MHz + * MIMXRT1051DVL6A - Consumer, Reduced Features, 600MHz + * MIMXRT1052CVL5A - Industrial, Full Feature, 528MHz + * MIMXRT1052DVL6A - Consumer, Full Feature, 600MHz + */ # define IMXRT_OCRAM_SIZE (512 * 1024) /* 512Kb OCRAM */ +# define IMXRT_GPIO_NPORTS 5 /* Five total ports */ + +#elif defined(CONFIG_ARCH_CHIP_MIMXRT1061DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1061CVL5A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1062DVL6A) || \ + defined(CONFIG_ARCH_CHIP_MIMXRT1062CVL5A) +/* MIMXRT1061CVL5A - Industrial, Reduced Features, 528MHz + * MIMXRT1061DVL6A - Consumer, Reduced Features, 600MHz + * MIMXRT1062CVL5A - Industrial, Full Feature, 528MHz + * MIMXRT1062DVL6A - Consumer, Full Feature, 600MHz + */ + +# define IMXRT_OCRAM_SIZE (1024 * 1024) /* 1024Kb OCRAM */ +# define IMXRT_GPIO_NPORTS 9 /* Nine total ports */ #else # error "Unknown i.MX RT chip type" #endif diff --git a/arch/arm/include/imxrt/imxrt105x_irq.h b/arch/arm/include/imxrt/imxrt105x_irq.h index b3b188fe20..870c838639 100644 --- a/arch/arm/include/imxrt/imxrt105x_irq.h +++ b/arch/arm/include/imxrt/imxrt105x_irq.h @@ -81,7 +81,7 @@ #define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */ #define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */ #define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */ -#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C- Interrupt */ +#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C4 Interrupt */ #define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */ #define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */ #define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */ diff --git a/arch/arm/include/imxrt/imxrt106x_irq.h b/arch/arm/include/imxrt/imxrt106x_irq.h new file mode 100644 index 0000000000..21efa6174c --- /dev/null +++ b/arch/arm/include/imxrt/imxrt106x_irq.h @@ -0,0 +1,725 @@ +/**************************************************************************************** + * arch/arm/include/imxrt/imxrt106x_irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly through + * nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_IMXRT_IMXRT106X_IRQ_H +#define __ARCH_ARM_INCLUDE_IMXRT_IMXRT106X_IRQ_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ + +/* External interrupts (priority levels >= 256) *****************************************/ + +#define IMXRT_IRQ_EDMA0_16 (IMXRT_IRQ_EXTINT + 0) /* eDMA Channel 0/16 Transfer Complete */ +#define IMXRT_IRQ_EDMA1_17 (IMXRT_IRQ_EXTINT + 1) /* eDMA Channel 1/17 Transfer Complete */ +#define IMXRT_IRQ_EDMA2_18 (IMXRT_IRQ_EXTINT + 2) /* eDMA Channel 2/18 Transfer Complete */ +#define IMXRT_IRQ_EDMA3_19 (IMXRT_IRQ_EXTINT + 3) /* eDMA Channel 3/19 Transfer Complete */ +#define IMXRT_IRQ_EDMA4_20 (IMXRT_IRQ_EXTINT + 4) /* eDMA Channel 4/20 Transfer Complete */ +#define IMXRT_IRQ_EDMA5_21 (IMXRT_IRQ_EXTINT + 5) /* eDMA Channel 5/21 Transfer Complete */ +#define IMXRT_IRQ_EDMA6_22 (IMXRT_IRQ_EXTINT + 6) /* eDMA Channel 6/22 Transfer Complete */ +#define IMXRT_IRQ_EDMA7_23 (IMXRT_IRQ_EXTINT + 7) /* eDMA Channel 7/23 Transfer Complete */ +#define IMXRT_IRQ_EDMA8_24 (IMXRT_IRQ_EXTINT + 8) /* eDMA Channel 8/24 Transfer Complete */ +#define IMXRT_IRQ_EDMA9_25 (IMXRT_IRQ_EXTINT + 9) /* eDMA Channel 9/25 Transfer Complete */ +#define IMXRT_IRQ_EDMA10_26 (IMXRT_IRQ_EXTINT + 10) /* eDMA Channel 10/26 Transfer Complete */ +#define IMXRT_IRQ_EDMA11_27 (IMXRT_IRQ_EXTINT + 11) /* eDMA Channel 11/27 Transfer Complete */ +#define IMXRT_IRQ_EDMA12_28 (IMXRT_IRQ_EXTINT + 12) /* eDMA Channel 12/28 Transfer Complete */ +#define IMXRT_IRQ_EDMA13_29 (IMXRT_IRQ_EXTINT + 13) /* eDMA Channel 13/29 Transfer Complete */ +#define IMXRT_IRQ_EDMA14_30 (IMXRT_IRQ_EXTINT + 14) /* eDMA Channel 14/30 Transfer Complete */ +#define IMXRT_IRQ_EDMA15_31 (IMXRT_IRQ_EXTINT + 15) /* eDMA Channel 15/31 Transfer Complete */ +#define IMXRT_IRQ_EDMA_ERROR (IMXRT_IRQ_EXTINT + 16) /* Error Interrupt, Channels 0-15 / 16-31 */ +#define IMXRT_IRQ_CM70 (IMXRT_IRQ_EXTINT + 17) /* CTI trigger outputs (internal: CTIIRQ[0]) */ +#define IMXRT_IRQ_CM71 (IMXRT_IRQ_EXTINT + 18) /* CTI trigger outputs (internal: CTIIRQ[1]) */ +#define IMXRT_IRQ_CM7CP (IMXRT_IRQ_EXTINT + 19) /* CorePlatform exception IRQ */ +#define IMXRT_IRQ_LPUART1 (IMXRT_IRQ_EXTINT + 20) /* UART1 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART2 (IMXRT_IRQ_EXTINT + 21) /* UART2 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART3 (IMXRT_IRQ_EXTINT + 22) /* UART3 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART4 (IMXRT_IRQ_EXTINT + 23) /* UART4 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART5 (IMXRT_IRQ_EXTINT + 24) /* UART5 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART6 (IMXRT_IRQ_EXTINT + 25) /* UART6 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART7 (IMXRT_IRQ_EXTINT + 26) /* UART7 TX/RX interrupt */ +#define IMXRT_IRQ_LPUART8 (IMXRT_IRQ_EXTINT + 27) /* UART8 TX/RX interrupt */ +#define IMXRT_IRQ_LPI2C1 (IMXRT_IRQ_EXTINT + 28) /* I2C1 Interrupt */ +#define IMXRT_IRQ_LPI2C2 (IMXRT_IRQ_EXTINT + 29) /* I2C2 Interrupt */ +#define IMXRT_IRQ_LPI2C3 (IMXRT_IRQ_EXTINT + 30) /* I2C3 Interrupt */ +#define IMXRT_IRQ_LPI2C4 (IMXRT_IRQ_EXTINT + 31) /* I2C4 Interrupt */ +#define IMXRT_IRQ_LPSPI1 (IMXRT_IRQ_EXTINT + 32) /* LPSPI1 interrupt */ +#define IMXRT_IRQ_LPSPI2 (IMXRT_IRQ_EXTINT + 33) /* LPSPI2 interrupt */ +#define IMXRT_IRQ_LPSPI3 (IMXRT_IRQ_EXTINT + 34) /* LPSPI3 interrupt */ +#define IMXRT_IRQ_LPSPI4 (IMXRT_IRQ_EXTINT + 35) /* LPSPI4 interrupt */ +#define IMXRT_IRQ_CAN1 (IMXRT_IRQ_EXTINT + 36) /* CAN1 interrupt */ +#define IMXRT_IRQ_CAN2 (IMXRT_IRQ_EXTINT + 37) /* CAN2 interrupt */ +#define IMXRT_IRQ_CM7FR (IMXRT_IRQ_EXTINT + 38) /* FlexRAM address fault */ +#define IMXRT_IRQ_KPP (IMXRT_IRQ_EXTINT + 39) /* Keypad Interrupt */ +#define IMXRT_IRQ_TSCDIG (IMXRT_IRQ_EXTINT + 40) /* TSC interrupt */ +#define IMXRT_IRQ_GPRIRQ (IMXRT_IRQ_EXTINT + 41) /* Notify cores on exception while boot */ +#define IMXRT_IRQ_LCDIF (IMXRT_IRQ_EXTINT + 42) /* LCDIF Sync Interrupt */ +#define IMXRT_IRQ_CSI (IMXRT_IRQ_EXTINT + 43) /* CSI interrupt */ +#define IMXRT_IRQ_PXP (IMXRT_IRQ_EXTINT + 44) /* PXP interrupt */ +#define IMXRT_IRQ_WDOG2 (IMXRT_IRQ_EXTINT + 45) /* Watchdog Timer reset */ +#define IMXRT_IRQ_SNVS (IMXRT_IRQ_EXTINT + 46) /* SNVS Functional Interrupt */ +#define IMXRT_IRQ_SNVSSEC (IMXRT_IRQ_EXTINT + 47) /* SNVS Security Interrupt */ +#define IMXRT_IRQ_SNVSSB (IMXRT_IRQ_EXTINT + 48) /* ON-OFF short button press */ +#define IMXRT_IRQ_CSU (IMXRT_IRQ_EXTINT + 49) /* CSU Interrupt Request 1 */ +#define IMXRT_IRQ_DCP (IMXRT_IRQ_EXTINT + 50) /* DCP channel/CRC interrupts (channel != 0) */ +#define IMXRT_IRQ_DCP0 (IMXRT_IRQ_EXTINT + 51) /* DCP channel 0 interrupt */ +#define IMXRT_IRQ_RESERVED52 (IMXRT_IRQ_EXTINT + 52) /* Reserved */ +#define IMXRT_IRQ_TRNG (IMXRT_IRQ_EXTINT + 53) /* TRNG Interrupt */ +#define IMXRT_IRQ_SJC (IMXRT_IRQ_EXTINT + 54) /* SJC Interrupt from General Purpose register */ +#define IMXRT_IRQ_BEE (IMXRT_IRQ_EXTINT + 55) /* BEE IRQ */ +#define IMXRT_IRQ_SAI1 (IMXRT_IRQ_EXTINT + 56) /* SAI1 interrupt */ +#define IMXRT_IRQ_SAI2 (IMXRT_IRQ_EXTINT + 57) /* SAI2 interrupt */ +#define IMXRT_IRQ_SAI3RX (IMXRT_IRQ_EXTINT + 58) /* SAI3 RX interrupt */ +#define IMXRT_IRQ_SAI3TX (IMXRT_IRQ_EXTINT + 59) /* SAI3 TX interrupt */ +#define IMXRT_IRQ_SPDIF (IMXRT_IRQ_EXTINT + 60) /* SPDIF interrupt */ +#define IMXRT_IRQ_PMU (IMXRT_IRQ_EXTINT + 61) /* Brown-out event 1.1, 2.5 or 3.0 regulators */ +#define IMXRT_IRQ_RESERVED62 (IMXRT_IRQ_EXTINT + 62) /* Reserved */ +#define IMXRT_IRQ_TEMP (IMXRT_IRQ_EXTINT + 63) /* Temperature Monitor */ +#define IMXRT_IRQ_TEMPPANIC (IMXRT_IRQ_EXTINT + 64) /* TempSensor panic */ +#define IMXRT_IRQ_USBPHY0 (IMXRT_IRQ_EXTINT + 65) /* USBPHY (UTMI0) interrupt */ +#define IMXRT_IRQ_USBPHY1 (IMXRT_IRQ_EXTINT + 66) /* USBPHY (UTMI1) interrupt */ +#define IMXRT_IRQ_ADC1 (IMXRT_IRQ_EXTINT + 67) /* ADC1 interrupt */ +#define IMXRT_IRQ_ADC2 (IMXRT_IRQ_EXTINT + 68) /* ADC2 interrupt */ +#define IMXRT_IRQ_DCDC (IMXRT_IRQ_EXTINT + 69) /* DCDC interrupt */ +#define IMXRT_IRQ_RESERVED70 (IMXRT_IRQ_EXTINT + 70) /* Reserved */ +#define IMXRT_IRQ_RESERVED71 (IMXRT_IRQ_EXTINT + 71) /* Reserved */ +#define IMXRT_IRQ_GPIO1_0 (IMXRT_IRQ_EXTINT + 72) /* GPIO1 INT0 interrupt */ +#define IMXRT_IRQ_GPIO1_1 (IMXRT_IRQ_EXTINT + 73) /* GPIO1 INT1 interrupt */ +#define IMXRT_IRQ_GPIO1_2 (IMXRT_IRQ_EXTINT + 74) /* GPIO1 INT2 interrupt */ +#define IMXRT_IRQ_GPIO1_3 (IMXRT_IRQ_EXTINT + 75) /* GPIO1 INT3 interrupt */ +#define IMXRT_IRQ_GPIO1_4 (IMXRT_IRQ_EXTINT + 76) /* GPIO1 INT4 interrupt */ +#define IMXRT_IRQ_GPIO1_5 (IMXRT_IRQ_EXTINT + 77) /* GPIO1 INT5 interrupt */ +#define IMXRT_IRQ_GPIO1_6 (IMXRT_IRQ_EXTINT + 78) /* GPIO1 INT6 interrupt */ +#define IMXRT_IRQ_GPIO1_7 (IMXRT_IRQ_EXTINT + 79) /* GPIO1 INT7 interrupt */ +#define IMXRT_IRQ_GPIO1_0_15 (IMXRT_IRQ_EXTINT + 80) /* GPIO1 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO1_16_31 (IMXRT_IRQ_EXTINT + 81) /* GPIO1 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO2_0_15 (IMXRT_IRQ_EXTINT + 82) /* GPIO2 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO2_16_31 (IMXRT_IRQ_EXTINT + 83) /* GPIO2 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO3_0_15 (IMXRT_IRQ_EXTINT + 84) /* GPIO3 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO3_16_31 (IMXRT_IRQ_EXTINT + 85) /* GPIO3 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO4_0_15 (IMXRT_IRQ_EXTINT + 86) /* GPIO4 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO4_16_31 (IMXRT_IRQ_EXTINT + 87) /* GPIO4 INT16-31 interrupt */ +#define IMXRT_IRQ_GPIO5_0_15 (IMXRT_IRQ_EXTINT + 88) /* GPIO5 INT0-15 interrupt */ +#define IMXRT_IRQ_GPIO5_16_31 (IMXRT_IRQ_EXTINT + 89) /* GPIO5 INT16-31 interrupt */ +#define IMXRT_IRQ_FLEXIO1 (IMXRT_IRQ_EXTINT + 90) /* IPI compare interrupt */ +#define IMXRT_IRQ_FLEXIO2 (IMXRT_IRQ_EXTINT + 91) /* IPI compare interrupt */ +#define IMXRT_IRQ_WDOG1 (IMXRT_IRQ_EXTINT + 92) /* Watchdog Timer reset */ +#define IMXRT_IRQ_RTWDOG (IMXRT_IRQ_EXTINT + 93) /* Watchdog Timer reset */ +#define IMXRT_IRQ_EWM (IMXRT_IRQ_EXTINT + 94) /* EWM interrupt */ +#define IMXRT_IRQ_CCM_1 (IMXRT_IRQ_EXTINT + 95) /* CCM interrupt 1 */ +#define IMXRT_IRQ_CCM_2 (IMXRT_IRQ_EXTINT + 96) /* CCM interrupt 2 */ +#define IMXRT_IRQ_GPC (IMXRT_IRQ_EXTINT + 97) /* GPC interrupt 1 */ +#define IMXRT_IRQ_SRC (IMXRT_IRQ_EXTINT + 98) /* SRC interrupt */ +#define IMXRT_IRQ_RESERVED99 (IMXRT_IRQ_EXTINT + 99) /* Reserved */ +#define IMXRT_IRQ_GPT1 (IMXRT_IRQ_EXTINT + 100) /* GPT1 interrupt */ +#define IMXRT_IRQ_GPT2 (IMXRT_IRQ_EXTINT + 101) /* GPT2 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_0 (IMXRT_IRQ_EXTINT + 102) /* FLEXPWM1 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_1 (IMXRT_IRQ_EXTINT + 103) /* FLEXPWM1 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_2 (IMXRT_IRQ_EXTINT + 104) /* FLEXPWM1 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_3 (IMXRT_IRQ_EXTINT + 105) /* FLEXPWM1 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM1_F (IMXRT_IRQ_EXTINT + 106) /* FLEXPWM1 fault interrupt */ +#define IMXRT_IRQ_FLEXSPI2 (IMXRT_IRQ_EXTINT + 107) /* FlexSPI2 interrupt */ +#define IMXRT_IRQ_FLEXSPI (IMXRT_IRQ_EXTINT + 108) /* FlexSPI interrupt */ +#define IMXRT_IRQ_SEMC (IMXRT_IRQ_EXTINT + 109) /* SEMC interrupt */ +#define IMXRT_IRQ_USDHC1 (IMXRT_IRQ_EXTINT + 110) /* USDHC1 interrupt */ +#define IMXRT_IRQ_USDHC2 (IMXRT_IRQ_EXTINT + 111) /* USDHC2 interrupt */ +#define IMXRT_IRQ_USBOTG2 (IMXRT_IRQ_EXTINT + 112) /* USBO2 USB OTG2 interrupt */ +#define IMXRT_IRQ_USBOTG1 (IMXRT_IRQ_EXTINT + 113) /* USBO2 USB OTG1 interrupt */ +#define IMXRT_IRQ_ENET (IMXRT_IRQ_EXTINT + 114) /* ENET MAC 0 interrupt */ +#define IMXRT_IRQ_ENET1588 (IMXRT_IRQ_EXTINT + 115) /* ENET MAC 0 1588 Timer Interrupt */ +#define IMXRT_IRQ_XBAR1_0_1 (IMXRT_IRQ_EXTINT + 116) /* XBAR1 interrupt 0/1 */ +#define IMXRT_IRQ_XBAR1_2_3 (IMXRT_IRQ_EXTINT + 117) /* XBAR1 interrupt 2/3 */ +#define IMXRT_IRQ_ADCETC_0 (IMXRT_IRQ_EXTINT + 118) /* ADC_ETC interrupt 0 */ +#define IMXRT_IRQ_ADCETC_1 (IMXRT_IRQ_EXTINT + 119) /* ADC_ETC interrupt 1 */ +#define IMXRT_IRQ_ADCETC_2 (IMXRT_IRQ_EXTINT + 120) /* ADC_ETC interrupt 2 */ +#define IMXRT_IRQ_ADCETC_ERR (IMXRT_IRQ_EXTINT + 121) /* ADC_ETC error interrupt */ +#define IMXRT_IRQ_PIT (IMXRT_IRQ_EXTINT + 122) /* PIT interrupt */ +#define IMXRT_IRQ_ACMP1 (IMXRT_IRQ_EXTINT + 123) /* ACMP1 interrupt */ +#define IMXRT_IRQ_ACMP2 (IMXRT_IRQ_EXTINT + 124) /* ACMP2 interrupt */ +#define IMXRT_IRQ_ACMP3 (IMXRT_IRQ_EXTINT + 125) /* ACMP3 interrupt */ +#define IMXRT_IRQ_ACMP4 (IMXRT_IRQ_EXTINT + 126) /* ACMP4 interrupt */ +#define IMXRT_IRQ_RESERVED127 (IMXRT_IRQ_EXTINT + 127) /* Reserved */ +#define IMXRT_IRQ_RESERVED128 (IMXRT_IRQ_EXTINT + 128) /* Reserved */ +#define IMXRT_IRQ_ENC1 (IMXRT_IRQ_EXTINT + 129) /* ENC1 interrupt */ +#define IMXRT_IRQ_ENC2 (IMXRT_IRQ_EXTINT + 130) /* ENC2 interrupt */ +#define IMXRT_IRQ_ENC3 (IMXRT_IRQ_EXTINT + 131) /* ENC3 interrupt */ +#define IMXRT_IRQ_ENC4 (IMXRT_IRQ_EXTINT + 132) /* ENC4 interrupt */ +#define IMXRT_IRQ_QTIMER1 (IMXRT_IRQ_EXTINT + 133) /* QTIMER1 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER2 (IMXRT_IRQ_EXTINT + 134) /* QTIMER2 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER3 (IMXRT_IRQ_EXTINT + 135) /* QTIMER3 timer 0-3 interrupt */ +#define IMXRT_IRQ_QTIMER4 (IMXRT_IRQ_EXTINT + 136) /* QTIMER4 timer 0-3 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_0 (IMXRT_IRQ_EXTINT + 137) /* LEXPWM2 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_1 (IMXRT_IRQ_EXTINT + 138) /* LEXPWM2 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_2 (IMXRT_IRQ_EXTINT + 139) /* LEXPWM2 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_3 (IMXRT_IRQ_EXTINT + 140) /* LEXPWM2 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM2_F (IMXRT_IRQ_EXTINT + 141) /* LEXPWM2 fault interrupt */ +#define IMXRT_IRQ_FLEXPWM3_0 (IMXRT_IRQ_EXTINT + 142) /* LEXPWM3 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM3_1 (IMXRT_IRQ_EXTINT + 143) /* LEXPWM3 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM3_2 (IMXRT_IRQ_EXTINT + 144) /* LEXPWM3 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM3_F (IMXRT_IRQ_EXTINT + 146) /* LEXPWM3 fault interrupt */ +#define IMXRT_IRQ_FLEXPWM4_0 (IMXRT_IRQ_EXTINT + 147) /* LEXPWM4 capture/compare/reload 0 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_1 (IMXRT_IRQ_EXTINT + 148) /* LEXPWM4 capture/compare/reload 1 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_2 (IMXRT_IRQ_EXTINT + 149) /* LEXPWM4 capture/compare/reload 2 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_3 (IMXRT_IRQ_EXTINT + 150) /* LEXPWM4 capture/compare/reload 3 interrupt */ +#define IMXRT_IRQ_FLEXPWM4_F (IMXRT_IRQ_EXTINT + 151) /* LEXPWM4 fault interrupt */ +#define IMXRT_IRQ_ENET2 (IMXRT_IRQ_EXTINT + 152) /* ENET2 MAC0 interrupt */ +#define IMXRT_IRQ_ENET2_1588 (IMXRT_IRQ_EXTINT + 153) /* ENET2 MAC 0 1588 Timer Interrupt */ +#define IMXRT_IRQ_CAN3 (IMXRT_IRQ_EXTINT + 154) /* CAN3 interrupt */ +#define IMXRT_IRQ_RESERVED155 (IMXRT_IRQ_EXTINT + 155) /* Reserved */ +#define IMXRT_IRQ_FLEXIO3 (IMXRT_IRQ_EXTINT + 156) /* IPI compare interrupt */ +#define IMXRT_IRQ_GPIO_6789 (IMXRT_IRQ_EXTINT + 157) /* GPIO {6789} or'ed Interrupt */ +#define IMXRT_IRQ_RESERVED158 (IMXRT_IRQ_EXTINT + 158) /* Reserved */ +#define IMXRT_IRQ_RESERVED159 (IMXRT_IRQ_EXTINT + 159) /* Reserved */ + +#define IMXRT_IRQ_NEXTINT 160 + +/* GPIO second level interrupt **********************************************************/ + +#define IMXRT_GPIO_IRQ_FIRST (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT) +#define _IMXRT_GPIO1_0_15_BASE IMXRT_GPIO_IRQ_FIRST + +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ + /* GPIO1 has dedicated interrupts for pins 0-7 + * REVISIT: I am assuming that you really cannot use the dedicated and the multiplex + * interrupts concurrently. + */ + +# define IMXRT_IRQ_GPIO1_0 (_IMXRT_GPIO1_0_15_BASE + 0) /* GPIO1 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO1_1 (_IMXRT_GPIO1_0_15_BASE + 1) /* GPIO1 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO1_2 (_IMXRT_GPIO1_0_15_BASE + 2) /* GPIO1 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO1_3 (_IMXRT_GPIO1_0_15_BASE + 3) /* GPIO1 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO1_4 (_IMXRT_GPIO1_0_15_BASE + 4) /* GPIO1 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO1_5 (_IMXRT_GPIO1_0_15_BASE + 5) /* GPIO1 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO1_6 (_IMXRT_GPIO1_0_15_BASE + 6) /* GPIO1 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO1_7 (_IMXRT_GPIO1_0_15_BASE + 7) /* GPIO1 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO1_8 (_IMXRT_GPIO1_0_15_BASE + 8) /* GPIO1 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO1_9 (_IMXRT_GPIO1_0_15_BASE + 9) /* GPIO1 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO1_10 (_IMXRT_GPIO1_0_15_BASE + 10) /* GPIO1 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO1_11 (_IMXRT_GPIO1_0_15_BASE + 11) /* GPIO1 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO1_12 (_IMXRT_GPIO1_0_15_BASE + 12) /* GPIO1 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO1_13 (_IMXRT_GPIO1_0_15_BASE + 13) /* GPIO1 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO1_14 (_IMXRT_GPIO1_0_15_BASE + 14) /* GPIO1 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO1_15 (_IMXRT_GPIO1_0_15_BASE + 15) /* GPIO1 pin 15 interrupt */ + +# define _IMXRT_GPIO1_8_15_NIRQS 16 +# define _IMXRT_GPIO1_16_31_BASE (_IMXRT_GPIO1_0_15_BASE + _IMXRT_GPIO1_8_15_NIRQS) +#else +# define _IMXRT_GPIO1_8_15_NIRQS 0 +# define _IMXRT_GPIO1_16_31_BASE _IMXRT_GPIO1_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO1_16_31_IRQ +# define IMXRT_IRQ_GPIO1_16 (_IMXRT_GPIO1_16_31_BASE + 0) /* GPIO1 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO1_17 (_IMXRT_GPIO1_16_31_BASE + 1) /* GPIO1 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO1_18 (_IMXRT_GPIO1_16_31_BASE + 2) /* GPIO1 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO1_19 (_IMXRT_GPIO1_16_31_BASE + 3) /* GPIO1 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO1_20 (_IMXRT_GPIO1_16_31_BASE + 4) /* GPIO1 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO1_21 (_IMXRT_GPIO1_16_31_BASE + 5) /* GPIO1 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO1_22 (_IMXRT_GPIO1_16_31_BASE + 6) /* GPIO1 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO1_23 (_IMXRT_GPIO1_16_31_BASE + 7) /* GPIO1 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO1_24 (_IMXRT_GPIO1_16_31_BASE + 8) /* GPIO1 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO1_25 (_IMXRT_GPIO1_16_31_BASE + 9) /* GPIO1 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO1_26 (_IMXRT_GPIO1_16_31_BASE + 10) /* GPIO1 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO1_27 (_IMXRT_GPIO1_16_31_BASE + 11) /* GPIO1 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO1_28 (_IMXRT_GPIO1_16_31_BASE + 12) /* GPIO1 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO1_29 (_IMXRT_GPIO1_16_31_BASE + 13) /* GPIO1 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO1_30 (_IMXRT_GPIO1_16_31_BASE + 14) /* GPIO1 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO1_31 (_IMXRT_GPIO1_16_31_BASE + 15) /* GPIO1 pin 31 interrupt */ + +# define _IMXRT_GPIO1_16_31_NIRQS 16 +# define _IMXRT_GPIO2_0_15_BASE (_IMXRT_GPIO1_16_31_BASE + _IMXRT_GPIO1_16_31_NIRQS) +# define IMXRT_GPIO1_NIRQS (_IMXRT_GPIO1_8_15_NIRQS + _IMXRT_GPIO1_16_31_NIRQS) +#else +# define _IMXRT_GPIO2_0_15_BASE _IMXRT_GPIO1_16_31_BASE +# define IMXRT_GPIO1_NIRQS _IMXRT_GPIO1_8_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO2_0_15_IRQ +# define IMXRT_IRQ_GPIO2_0 (_IMXRT_GPIO2_0_15_BASE + 0) /* GPIO2 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO2_1 (_IMXRT_GPIO2_0_15_BASE + 1) /* GPIO2 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO2_2 (_IMXRT_GPIO2_0_15_BASE + 2) /* GPIO2 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO2_3 (_IMXRT_GPIO2_0_15_BASE + 3) /* GPIO2 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO2_4 (_IMXRT_GPIO2_0_15_BASE + 4) /* GPIO2 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO2_5 (_IMXRT_GPIO2_0_15_BASE + 5) /* GPIO2 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO2_6 (_IMXRT_GPIO2_0_15_BASE + 6) /* GPIO2 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO2_7 (_IMXRT_GPIO2_0_15_BASE + 7) /* GPIO2 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO2_8 (_IMXRT_GPIO2_0_15_BASE + 8) /* GPIO2 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO2_9 (_IMXRT_GPIO2_0_15_BASE + 9) /* GPIO2 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO2_10 (_IMXRT_GPIO2_0_15_BASE + 10) /* GPIO2 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO2_11 (_IMXRT_GPIO2_0_15_BASE + 11) /* GPIO2 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO2_12 (_IMXRT_GPIO2_0_15_BASE + 12) /* GPIO2 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO2_13 (_IMXRT_GPIO2_0_15_BASE + 13) /* GPIO2 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO2_14 (_IMXRT_GPIO2_0_15_BASE + 14) /* GPIO2 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO2_15 (_IMXRT_GPIO2_0_15_BASE + 15) /* GPIO2 pin 15 interrupt */ + +# define _IMXRT_GPIO2_0_15_NIRQS 16 +# define _IMXRT_GPIO2_16_31_BASE (_IMXRT_GPIO2_0_15_BASE + _IMXRT_GPIO2_0_15_NIRQS) +#else +# define _IMXRT_GPIO2_0_15_NIRQS 0 +# define _IMXRT_GPIO2_16_31_BASE _IMXRT_GPIO2_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO2_16_31_IRQ +# define IMXRT_IRQ_GPIO2_16 (_IMXRT_GPIO2_16_31_BASE + 0) /* GPIO2 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO2_17 (_IMXRT_GPIO2_16_31_BASE + 1) /* GPIO2 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO2_18 (_IMXRT_GPIO2_16_31_BASE + 2) /* GPIO2 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO2_19 (_IMXRT_GPIO2_16_31_BASE + 3) /* GPIO2 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO2_20 (_IMXRT_GPIO2_16_31_BASE + 4) /* GPIO2 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO2_21 (_IMXRT_GPIO2_16_31_BASE + 5) /* GPIO2 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO2_22 (_IMXRT_GPIO2_16_31_BASE + 6) /* GPIO2 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO2_23 (_IMXRT_GPIO2_16_31_BASE + 7) /* GPIO2 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO2_24 (_IMXRT_GPIO2_16_31_BASE + 8) /* GPIO2 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO2_25 (_IMXRT_GPIO2_16_31_BASE + 9) /* GPIO2 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO2_26 (_IMXRT_GPIO2_16_31_BASE + 10) /* GPIO2 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO2_27 (_IMXRT_GPIO2_16_31_BASE + 11) /* GPIO2 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO2_28 (_IMXRT_GPIO2_16_31_BASE + 12) /* GPIO2 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO2_29 (_IMXRT_GPIO2_16_31_BASE + 13) /* GPIO2 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO2_30 (_IMXRT_GPIO2_16_31_BASE + 14) /* GPIO2 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO2_31 (_IMXRT_GPIO2_16_31_BASE + 15) /* GPIO2 pin 31 interrupt */ + +# define _IMXRT_GPIO2_16_31_NIRQS 16 +# define _IMXRT_GPIO3_0_15_BASE (_IMXRT_GPIO2_16_31_BASE + _IMXRT_GPIO2_16_31_NIRQS) +# define IMXRT_GPIO2_NIRQS (_IMXRT_GPIO2_0_15_NIRQS + _IMXRT_GPIO2_16_31_NIRQS) +#else +# define _IMXRT_GPIO3_0_15_BASE _IMXRT_GPIO2_16_31_BASE +# define IMXRT_GPIO2_NIRQS _IMXRT_GPIO2_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO3_0_15_IRQ +# define IMXRT_IRQ_GPIO3_0 (_IMXRT_GPIO3_0_15_BASE + 0) /* GPIO3 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO3_1 (_IMXRT_GPIO3_0_15_BASE + 1) /* GPIO3 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO3_2 (_IMXRT_GPIO3_0_15_BASE + 2) /* GPIO3 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO3_3 (_IMXRT_GPIO3_0_15_BASE + 3) /* GPIO3 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO3_4 (_IMXRT_GPIO3_0_15_BASE + 4) /* GPIO3 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO3_5 (_IMXRT_GPIO3_0_15_BASE + 5) /* GPIO3 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO3_6 (_IMXRT_GPIO3_0_15_BASE + 6) /* GPIO3 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO3_7 (_IMXRT_GPIO3_0_15_BASE + 7) /* GPIO3 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO3_8 (_IMXRT_GPIO3_0_15_BASE + 8) /* GPIO3 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO3_9 (_IMXRT_GPIO3_0_15_BASE + 9) /* GPIO3 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO3_10 (_IMXRT_GPIO3_0_15_BASE + 10) /* GPIO3 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO3_11 (_IMXRT_GPIO3_0_15_BASE + 11) /* GPIO3 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO3_12 (_IMXRT_GPIO3_0_15_BASE + 12) /* GPIO3 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO3_13 (_IMXRT_GPIO3_0_15_BASE + 13) /* GPIO3 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO3_14 (_IMXRT_GPIO3_0_15_BASE + 14) /* GPIO3 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO3_15 (_IMXRT_GPIO3_0_15_BASE + 15) /* GPIO3 pin 15 interrupt */ + +# define _IMXRT_GPIO3_0_15_NIRQS 16 +# define _IMXRT_GPIO3_16_31_BASE (_IMXRT_GPIO3_0_15_BASE + _IMXRT_GPIO3_0_15_NIRQS) +#else +# define _IMXRT_GPIO3_0_15_NIRQS 0 +# define _IMXRT_GPIO3_16_31_BASE _IMXRT_GPIO3_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO3_16_31_IRQ +# define IMXRT_IRQ_GPIO3_16 (_IMXRT_GPIO3_16_31_BASE + 0) /* GPIO3 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO3_17 (_IMXRT_GPIO3_16_31_BASE + 1) /* GPIO3 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO3_18 (_IMXRT_GPIO3_16_31_BASE + 2) /* GPIO3 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO3_19 (_IMXRT_GPIO3_16_31_BASE + 3) /* GPIO3 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO3_20 (_IMXRT_GPIO3_16_31_BASE + 4) /* GPIO3 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO3_21 (_IMXRT_GPIO3_16_31_BASE + 5) /* GPIO3 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO3_22 (_IMXRT_GPIO3_16_31_BASE + 6) /* GPIO3 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO3_23 (_IMXRT_GPIO3_16_31_BASE + 7) /* GPIO3 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO3_24 (_IMXRT_GPIO3_16_31_BASE + 8) /* GPIO3 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO3_25 (_IMXRT_GPIO3_16_31_BASE + 9) /* GPIO3 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO3_26 (_IMXRT_GPIO3_16_31_BASE + 10) /* GPIO3 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO3_27 (_IMXRT_GPIO3_16_31_BASE + 11) /* GPIO3 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO3_28 (_IMXRT_GPIO3_16_31_BASE + 12) /* GPIO3 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO3_29 (_IMXRT_GPIO3_16_31_BASE + 13) /* GPIO3 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO3_30 (_IMXRT_GPIO3_16_31_BASE + 14) /* GPIO3 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO3_31 (_IMXRT_GPIO3_16_31_BASE + 15) /* GPIO3 pin 31 interrupt */ + +# define _IMXRT_GPIO3_16_31_NIRQS 16 +# define _IMXRT_GPIO4_0_15_BASE (_IMXRT_GPIO3_16_31_BASE + _IMXRT_GPIO3_16_31_NIRQS) +# define IMXRT_GPIO3_NIRQS (_IMXRT_GPIO3_0_15_NIRQS + _IMXRT_GPIO3_16_31_NIRQS) +#else +# define _IMXRT_GPIO4_0_15_BASE _IMXRT_GPIO3_16_31_BASE +# define IMXRT_GPIO3_NIRQS _IMXRT_GPIO3_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ +# define IMXRT_IRQ_GPIO4_0 (_IMXRT_GPIO4_0_15_BASE + 0) /* GPIO4 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO4_1 (_IMXRT_GPIO4_0_15_BASE + 1) /* GPIO4 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO4_2 (_IMXRT_GPIO4_0_15_BASE + 2) /* GPIO4 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO4_3 (_IMXRT_GPIO4_0_15_BASE + 3) /* GPIO4 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO4_4 (_IMXRT_GPIO4_0_15_BASE + 4) /* GPIO4 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO4_5 (_IMXRT_GPIO4_0_15_BASE + 5) /* GPIO4 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO4_6 (_IMXRT_GPIO4_0_15_BASE + 6) /* GPIO4 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO4_7 (_IMXRT_GPIO4_0_15_BASE + 7) /* GPIO4 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO4_8 (_IMXRT_GPIO4_0_15_BASE + 8) /* GPIO4 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO4_9 (_IMXRT_GPIO4_0_15_BASE + 9) /* GPIO4 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO4_10 (_IMXRT_GPIO4_0_15_BASE + 10) /* GPIO4 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO4_11 (_IMXRT_GPIO4_0_15_BASE + 11) /* GPIO4 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO4_12 (_IMXRT_GPIO4_0_15_BASE + 12) /* GPIO4 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO4_13 (_IMXRT_GPIO4_0_15_BASE + 13) /* GPIO4 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO4_14 (_IMXRT_GPIO4_0_15_BASE + 14) /* GPIO4 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO4_15 (_IMXRT_GPIO4_0_15_BASE + 15) /* GPIO4 pin 15 interrupt */ + +# define _IMXRT_GPIO4_0_15_NIRQS 16 +# define _IMXRT_GPIO4_16_31_BASE (_IMXRT_GPIO4_0_15_BASE + _IMXRT_GPIO4_0_15_NIRQS) +#else +# define _IMXRT_GPIO4_0_15_NIRQS 0 +# define _IMXRT_GPIO4_16_31_BASE _IMXRT_GPIO4_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ +# define IMXRT_IRQ_GPIO4_16 (_IMXRT_GPIO4_16_31_BASE + 0) /* GPIO4 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO4_17 (_IMXRT_GPIO4_16_31_BASE + 1) /* GPIO4 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO4_18 (_IMXRT_GPIO4_16_31_BASE + 2) /* GPIO4 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO4_19 (_IMXRT_GPIO4_16_31_BASE + 3) /* GPIO4 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO4_20 (_IMXRT_GPIO4_16_31_BASE + 4) /* GPIO4 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO4_21 (_IMXRT_GPIO4_16_31_BASE + 5) /* GPIO4 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO4_22 (_IMXRT_GPIO4_16_31_BASE + 6) /* GPIO4 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO4_23 (_IMXRT_GPIO4_16_31_BASE + 7) /* GPIO4 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO4_24 (_IMXRT_GPIO4_16_31_BASE + 8) /* GPIO4 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO4_25 (_IMXRT_GPIO4_16_31_BASE + 9) /* GPIO4 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO4_26 (_IMXRT_GPIO4_16_31_BASE + 10) /* GPIO4 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO4_27 (_IMXRT_GPIO4_16_31_BASE + 11) /* GPIO4 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO4_28 (_IMXRT_GPIO4_16_31_BASE + 12) /* GPIO4 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO4_29 (_IMXRT_GPIO4_16_31_BASE + 13) /* GPIO4 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO4_30 (_IMXRT_GPIO4_16_31_BASE + 14) /* GPIO4 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO4_31 (_IMXRT_GPIO4_16_31_BASE + 15) /* GPIO4 pin 31 interrupt */ + +# define _IMXRT_GPIO4_16_31_NIRQS 16 +# define _IMXRT_GPIO5_0_15_BASE (_IMXRT_GPIO4_16_31_BASE + _IMXRT_GPIO4_16_31_NIRQS) +# define IMXRT_GPIO4_NIRQS (_IMXRT_GPIO4_0_15_NIRQS + _IMXRT_GPIO4_16_31_NIRQS) +#else +# define _IMXRT_GPIO5_0_15_BASE _IMXRT_GPIO4_16_31_BASE +# define IMXRT_GPIO4_NIRQS _IMXRT_GPIO4_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ +# define IMXRT_IRQ_GPIO5_0 (_IMXRT_GPIO5_0_15_BASE + 0) /* GPIO5 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO5_1 (_IMXRT_GPIO5_0_15_BASE + 1) /* GPIO5 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO5_2 (_IMXRT_GPIO5_0_15_BASE + 2) /* GPIO5 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO5_3 (_IMXRT_GPIO5_0_15_BASE + 3) /* GPIO5 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO5_4 (_IMXRT_GPIO5_0_15_BASE + 4) /* GPIO5 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO5_5 (_IMXRT_GPIO5_0_15_BASE + 5) /* GPIO5 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO5_6 (_IMXRT_GPIO5_0_15_BASE + 6) /* GPIO5 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO5_7 (_IMXRT_GPIO5_0_15_BASE + 7) /* GPIO5 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO5_8 (_IMXRT_GPIO5_0_15_BASE + 8) /* GPIO5 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO5_9 (_IMXRT_GPIO5_0_15_BASE + 9) /* GPIO5 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO5_10 (_IMXRT_GPIO5_0_15_BASE + 10) /* GPIO5 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO5_11 (_IMXRT_GPIO5_0_15_BASE + 11) /* GPIO5 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO5_12 (_IMXRT_GPIO5_0_15_BASE + 12) /* GPIO5 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO5_13 (_IMXRT_GPIO5_0_15_BASE + 13) /* GPIO5 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO5_14 (_IMXRT_GPIO5_0_15_BASE + 14) /* GPIO5 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO5_15 (_IMXRT_GPIO5_0_15_BASE + 15) /* GPIO5 pin 15 interrupt */ + +# define _IMXRT_GPIO5_0_15_NIRQS 16 +# define _IMXRT_GPIO5_16_31_BASE (_IMXRT_GPIO5_0_15_BASE + _IMXRT_GPIO5_0_15_NIRQS) +#else +# define _IMXRT_GPIO5_0_15_NIRQS 0 +# define _IMXRT_GPIO5_16_31_BASE _IMXRT_GPIO5_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ +# define IMXRT_IRQ_GPIO5_16 (_IMXRT_GPIO5_16_31_BASE + 0) /* GPIO5 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO5_17 (_IMXRT_GPIO5_16_31_BASE + 1) /* GPIO5 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO5_18 (_IMXRT_GPIO5_16_31_BASE + 2) /* GPIO5 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO5_19 (_IMXRT_GPIO5_16_31_BASE + 3) /* GPIO5 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO5_20 (_IMXRT_GPIO5_16_31_BASE + 4) /* GPIO5 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO5_21 (_IMXRT_GPIO5_16_31_BASE + 5) /* GPIO5 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO5_22 (_IMXRT_GPIO5_16_31_BASE + 6) /* GPIO5 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO5_23 (_IMXRT_GPIO5_16_31_BASE + 7) /* GPIO5 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO5_24 (_IMXRT_GPIO5_16_31_BASE + 8) /* GPIO5 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO5_25 (_IMXRT_GPIO5_16_31_BASE + 9) /* GPIO5 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO5_26 (_IMXRT_GPIO5_16_31_BASE + 10) /* GPIO5 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO5_27 (_IMXRT_GPIO5_16_31_BASE + 11) /* GPIO5 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO5_28 (_IMXRT_GPIO5_16_31_BASE + 12) /* GPIO5 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO5_29 (_IMXRT_GPIO5_16_31_BASE + 13) /* GPIO5 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO5_30 (_IMXRT_GPIO5_16_31_BASE + 14) /* GPIO5 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO5_31 (_IMXRT_GPIO5_16_31_BASE + 15) /* GPIO5 pin 31 interrupt */ + +# define _IMXRT_GPIO5_16_31_NIRQS 16 +# define _IMXRT_GPIO6_0_15_BASE (_IMXRT_GPIO5_16_31_BASE + _IMXRT_GPIO5_16_31_NIRQS) +# define IMXRT_GPIO5_NIRQS (_IMXRT_GPIO5_0_15_NIRQS + _IMXRT_GPIO5_16_31_NIRQS) +#else +# define _IMXRT_GPIO6_0_15_BASE _IMXRT_GPIO5_16_31_BASE +# define IMXRT_GPIO5_NIRQS _IMXRT_GPIO5_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO6_0_15_IRQ +# define IMXRT_IRQ_GPIO6_0 (_IMXRT_GPIO6_0_15_BASE + 0) /* GPIO6 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO6_1 (_IMXRT_GPIO6_0_15_BASE + 1) /* GPIO6 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO6_2 (_IMXRT_GPIO6_0_15_BASE + 2) /* GPIO6 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO6_3 (_IMXRT_GPIO6_0_15_BASE + 3) /* GPIO6 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO6_4 (_IMXRT_GPIO6_0_15_BASE + 4) /* GPIO6 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO6_5 (_IMXRT_GPIO6_0_15_BASE + 5) /* GPIO6 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO6_6 (_IMXRT_GPIO6_0_15_BASE + 6) /* GPIO6 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO6_7 (_IMXRT_GPIO6_0_15_BASE + 7) /* GPIO6 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO6_8 (_IMXRT_GPIO6_0_15_BASE + 8) /* GPIO6 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO6_9 (_IMXRT_GPIO6_0_15_BASE + 9) /* GPIO6 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO6_10 (_IMXRT_GPIO6_0_15_BASE + 10) /* GPIO6 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO6_11 (_IMXRT_GPIO6_0_15_BASE + 11) /* GPIO6 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO6_12 (_IMXRT_GPIO6_0_15_BASE + 12) /* GPIO6 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO6_13 (_IMXRT_GPIO6_0_15_BASE + 13) /* GPIO6 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO6_14 (_IMXRT_GPIO6_0_15_BASE + 14) /* GPIO6 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO6_15 (_IMXRT_GPIO6_0_15_BASE + 15) /* GPIO6 pin 15 interrupt */ + +# define _IMXRT_GPIO6_0_15_NIRQS 16 +# define _IMXRT_GPIO6_16_31_BASE (_IMXRT_GPIO6_0_15_BASE + _IMXRT_GPIO6_0_15_NIRQS) +#else +# define _IMXRT_GPIO6_0_15_NIRQS 0 +# define _IMXRT_GPIO6_16_31_BASE _IMXRT_GPIO6_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO6_16_31_IRQ +# define IMXRT_IRQ_GPIO6_16 (_IMXRT_GPIO6_16_31_BASE + 0) /* GPIO6 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO6_17 (_IMXRT_GPIO6_16_31_BASE + 1) /* GPIO6 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO6_18 (_IMXRT_GPIO6_16_31_BASE + 2) /* GPIO6 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO6_19 (_IMXRT_GPIO6_16_31_BASE + 3) /* GPIO6 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO6_20 (_IMXRT_GPIO6_16_31_BASE + 4) /* GPIO6 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO6_21 (_IMXRT_GPIO6_16_31_BASE + 5) /* GPIO6 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO6_22 (_IMXRT_GPIO6_16_31_BASE + 6) /* GPIO6 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO6_23 (_IMXRT_GPIO6_16_31_BASE + 7) /* GPIO6 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO6_24 (_IMXRT_GPIO6_16_31_BASE + 8) /* GPIO6 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO6_25 (_IMXRT_GPIO6_16_31_BASE + 9) /* GPIO6 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO6_26 (_IMXRT_GPIO6_16_31_BASE + 10) /* GPIO6 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO6_27 (_IMXRT_GPIO6_16_31_BASE + 11) /* GPIO6 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO6_28 (_IMXRT_GPIO6_16_31_BASE + 12) /* GPIO6 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO6_29 (_IMXRT_GPIO6_16_31_BASE + 13) /* GPIO6 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO6_30 (_IMXRT_GPIO6_16_31_BASE + 14) /* GPIO6 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO6_31 (_IMXRT_GPIO6_16_31_BASE + 15) /* GPIO6 pin 31 interrupt */ + +# define _IMXRT_GPIO6_16_31_NIRQS 16 +# define _IMXRT_GPIO7_0_15_BASE (_IMXRT_GPIO6_16_31_BASE + _IMXRT_GPIO6_16_31_NIRQS) +# define IMXRT_GPIO6_NIRQS (_IMXRT_GPIO6_0_15_NIRQS + _IMXRT_GPIO6_16_31_NIRQS) +#else +# define _IMXRT_GPIO7_0_15_BASE _IMXRT_GPIO6_16_31_BASE +# define IMXRT_GPIO6_NIRQS _IMXRT_GPIO6_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO7_0_15_IRQ +# define IMXRT_IRQ_GPIO7_0 (_IMXRT_GPIO7_0_15_BASE + 0) /* GPIO7 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO7_1 (_IMXRT_GPIO7_0_15_BASE + 1) /* GPIO7 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO7_2 (_IMXRT_GPIO7_0_15_BASE + 2) /* GPIO7 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO7_3 (_IMXRT_GPIO7_0_15_BASE + 3) /* GPIO7 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO7_4 (_IMXRT_GPIO7_0_15_BASE + 4) /* GPIO7 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO7_5 (_IMXRT_GPIO7_0_15_BASE + 5) /* GPIO7 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO7_6 (_IMXRT_GPIO7_0_15_BASE + 6) /* GPIO7 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO7_7 (_IMXRT_GPIO7_0_15_BASE + 7) /* GPIO7 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO7_8 (_IMXRT_GPIO7_0_15_BASE + 8) /* GPIO7 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO7_9 (_IMXRT_GPIO7_0_15_BASE + 9) /* GPIO7 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO7_10 (_IMXRT_GPIO7_0_15_BASE + 10) /* GPIO7 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO7_11 (_IMXRT_GPIO7_0_15_BASE + 11) /* GPIO7 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO7_12 (_IMXRT_GPIO7_0_15_BASE + 12) /* GPIO7 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO7_13 (_IMXRT_GPIO7_0_15_BASE + 13) /* GPIO7 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO7_14 (_IMXRT_GPIO7_0_15_BASE + 14) /* GPIO7 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO7_15 (_IMXRT_GPIO7_0_15_BASE + 15) /* GPIO7 pin 15 interrupt */ + +# define _IMXRT_GPIO7_0_15_NIRQS 16 +# define _IMXRT_GPIO7_16_31_BASE (_IMXRT_GPIO7_0_15_BASE + _IMXRT_GPIO7_0_15_NIRQS) +#else +# define _IMXRT_GPIO7_0_15_NIRQS 0 +# define _IMXRT_GPIO7_16_31_BASE _IMXRT_GPIO7_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO7_16_31_IRQ +# define IMXRT_IRQ_GPIO7_16 (_IMXRT_GPIO7_16_31_BASE + 0) /* GPIO7 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO7_17 (_IMXRT_GPIO7_16_31_BASE + 1) /* GPIO7 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO7_18 (_IMXRT_GPIO7_16_31_BASE + 2) /* GPIO7 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO7_19 (_IMXRT_GPIO7_16_31_BASE + 3) /* GPIO7 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO7_20 (_IMXRT_GPIO7_16_31_BASE + 4) /* GPIO7 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO7_21 (_IMXRT_GPIO7_16_31_BASE + 5) /* GPIO7 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO7_22 (_IMXRT_GPIO7_16_31_BASE + 6) /* GPIO7 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO7_23 (_IMXRT_GPIO7_16_31_BASE + 7) /* GPIO7 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO7_24 (_IMXRT_GPIO7_16_31_BASE + 8) /* GPIO7 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO7_25 (_IMXRT_GPIO7_16_31_BASE + 9) /* GPIO7 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO7_26 (_IMXRT_GPIO7_16_31_BASE + 10) /* GPIO7 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO7_27 (_IMXRT_GPIO7_16_31_BASE + 11) /* GPIO7 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO7_28 (_IMXRT_GPIO7_16_31_BASE + 12) /* GPIO7 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO7_29 (_IMXRT_GPIO7_16_31_BASE + 13) /* GPIO7 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO7_30 (_IMXRT_GPIO7_16_31_BASE + 14) /* GPIO7 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO7_31 (_IMXRT_GPIO7_16_31_BASE + 15) /* GPIO7 pin 31 interrupt */ + +# define _IMXRT_GPIO7_16_31_NIRQS 16 +# define _IMXRT_GPIO8_0_15_BASE (_IMXRT_GPIO7_16_31_BASE + _IMXRT_GPIO7_16_31_NIRQS) +# define IMXRT_GPIO7_NIRQS (_IMXRT_GPIO7_0_15_NIRQS + _IMXRT_GPIO7_16_31_NIRQS) +#else +# define _IMXRT_GPIO8_0_15_BASE _IMXRT_GPIO7_16_31_BASE +# define IMXRT_GPIO7_NIRQS _IMXRT_GPIO7_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO8_0_15_IRQ +# define IMXRT_IRQ_GPIO8_0 (_IMXRT_GPIO8_0_15_BASE + 0) /* GPIO8 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO8_1 (_IMXRT_GPIO8_0_15_BASE + 1) /* GPIO8 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO8_2 (_IMXRT_GPIO8_0_15_BASE + 2) /* GPIO8 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO8_3 (_IMXRT_GPIO8_0_15_BASE + 3) /* GPIO8 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO8_4 (_IMXRT_GPIO8_0_15_BASE + 4) /* GPIO8 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO8_5 (_IMXRT_GPIO8_0_15_BASE + 5) /* GPIO8 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO8_6 (_IMXRT_GPIO8_0_15_BASE + 6) /* GPIO8 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO8_7 (_IMXRT_GPIO8_0_15_BASE + 7) /* GPIO8 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO8_8 (_IMXRT_GPIO8_0_15_BASE + 8) /* GPIO8 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO8_9 (_IMXRT_GPIO8_0_15_BASE + 9) /* GPIO8 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO8_10 (_IMXRT_GPIO8_0_15_BASE + 10) /* GPIO8 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO8_11 (_IMXRT_GPIO8_0_15_BASE + 11) /* GPIO8 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO8_12 (_IMXRT_GPIO8_0_15_BASE + 12) /* GPIO8 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO8_13 (_IMXRT_GPIO8_0_15_BASE + 13) /* GPIO8 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO8_14 (_IMXRT_GPIO8_0_15_BASE + 14) /* GPIO8 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO8_15 (_IMXRT_GPIO8_0_15_BASE + 15) /* GPIO8 pin 15 interrupt */ + +# define _IMXRT_GPIO8_0_15_NIRQS 16 +# define _IMXRT_GPIO8_16_31_BASE (_IMXRT_GPIO8_0_15_BASE + _IMXRT_GPIO8_0_15_NIRQS) +#else +# define _IMXRT_GPIO8_0_15_NIRQS 0 +# define _IMXRT_GPIO8_16_31_BASE _IMXRT_GPIO8_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO8_16_31_IRQ +# define IMXRT_IRQ_GPIO8_16 (_IMXRT_GPIO8_16_31_BASE + 0) /* GPIO8 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO8_17 (_IMXRT_GPIO8_16_31_BASE + 1) /* GPIO8 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO8_18 (_IMXRT_GPIO8_16_31_BASE + 2) /* GPIO8 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO8_19 (_IMXRT_GPIO8_16_31_BASE + 3) /* GPIO8 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO8_20 (_IMXRT_GPIO8_16_31_BASE + 4) /* GPIO8 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO8_21 (_IMXRT_GPIO8_16_31_BASE + 5) /* GPIO8 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO8_22 (_IMXRT_GPIO8_16_31_BASE + 6) /* GPIO8 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO8_23 (_IMXRT_GPIO8_16_31_BASE + 7) /* GPIO8 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO8_24 (_IMXRT_GPIO8_16_31_BASE + 8) /* GPIO8 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO8_25 (_IMXRT_GPIO8_16_31_BASE + 9) /* GPIO8 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO8_26 (_IMXRT_GPIO8_16_31_BASE + 10) /* GPIO8 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO8_27 (_IMXRT_GPIO8_16_31_BASE + 11) /* GPIO8 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO8_28 (_IMXRT_GPIO8_16_31_BASE + 12) /* GPIO8 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO8_29 (_IMXRT_GPIO8_16_31_BASE + 13) /* GPIO8 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO8_30 (_IMXRT_GPIO8_16_31_BASE + 14) /* GPIO8 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO8_31 (_IMXRT_GPIO8_16_31_BASE + 15) /* GPIO8 pin 31 interrupt */ + +# define _IMXRT_GPIO8_16_31_NIRQS 16 +# define _IMXRT_GPIO9_0_15_BASE (_IMXRT_GPIO8_16_31_BASE + _IMXRT_GPIO8_16_31_NIRQS) +# define IMXRT_GPIO8_NIRQS (_IMXRT_GPIO8_0_15_NIRQS + _IMXRT_GPIO8_16_31_NIRQS) +#else +# define _IMXRT_GPIO9_0_15_BASE _IMXRT_GPIO8_16_31_BASE +# define IMXRT_GPIO8_NIRQS _IMXRT_GPIO8_0_15_NIRQS +#endif + +#ifdef CONFIG_IMXRT_GPIO9_0_15_IRQ +# define IMXRT_IRQ_GPIO9_0 (_IMXRT_GPIO9_0_15_BASE + 0) /* GPIO9 pin 0 interrupt */ +# define IMXRT_IRQ_GPIO9_1 (_IMXRT_GPIO9_0_15_BASE + 1) /* GPIO9 pin 1 interrupt */ +# define IMXRT_IRQ_GPIO9_2 (_IMXRT_GPIO9_0_15_BASE + 2) /* GPIO9 pin 2 interrupt */ +# define IMXRT_IRQ_GPIO9_3 (_IMXRT_GPIO9_0_15_BASE + 3) /* GPIO9 pin 3 interrupt */ +# define IMXRT_IRQ_GPIO9_4 (_IMXRT_GPIO9_0_15_BASE + 4) /* GPIO9 pin 4 interrupt */ +# define IMXRT_IRQ_GPIO9_5 (_IMXRT_GPIO9_0_15_BASE + 5) /* GPIO9 pin 5 interrupt */ +# define IMXRT_IRQ_GPIO9_6 (_IMXRT_GPIO9_0_15_BASE + 6) /* GPIO9 pin 6 interrupt */ +# define IMXRT_IRQ_GPIO9_7 (_IMXRT_GPIO9_0_15_BASE + 7) /* GPIO9 pin 7 interrupt */ +# define IMXRT_IRQ_GPIO9_8 (_IMXRT_GPIO9_0_15_BASE + 8) /* GPIO9 pin 8 interrupt */ +# define IMXRT_IRQ_GPIO9_9 (_IMXRT_GPIO9_0_15_BASE + 9) /* GPIO9 pin 9 interrupt */ +# define IMXRT_IRQ_GPIO9_10 (_IMXRT_GPIO9_0_15_BASE + 10) /* GPIO9 pin 10 interrupt */ +# define IMXRT_IRQ_GPIO9_11 (_IMXRT_GPIO9_0_15_BASE + 11) /* GPIO9 pin 11 interrupt */ +# define IMXRT_IRQ_GPIO9_12 (_IMXRT_GPIO9_0_15_BASE + 12) /* GPIO9 pin 12 interrupt */ +# define IMXRT_IRQ_GPIO9_13 (_IMXRT_GPIO9_0_15_BASE + 13) /* GPIO9 pin 13 interrupt */ +# define IMXRT_IRQ_GPIO9_14 (_IMXRT_GPIO9_0_15_BASE + 14) /* GPIO9 pin 14 interrupt */ +# define IMXRT_IRQ_GPIO9_15 (_IMXRT_GPIO9_0_15_BASE + 15) /* GPIO9 pin 15 interrupt */ + +# define _IMXRT_GPIO9_0_15_NIRQS 16 +# define _IMXRT_GPIO9_16_31_BASE (_IMXRT_GPIO9_0_15_BASE + _IMXRT_GPIO9_0_15_NIRQS) +#else +# define _IMXRT_GPIO9_0_15_NIRQS 0 +# define _IMXRT_GPIO9_16_31_BASE _IMXRT_GPIO9_0_15_BASE +#endif + +#ifdef CONFIG_IMXRT_GPIO9_16_31_IRQ +# define IMXRT_IRQ_GPIO9_16 (_IMXRT_GPIO9_16_31_BASE + 0) /* GPIO9 pin 16 interrupt */ +# define IMXRT_IRQ_GPIO9_17 (_IMXRT_GPIO9_16_31_BASE + 1) /* GPIO9 pin 17 interrupt */ +# define IMXRT_IRQ_GPIO9_18 (_IMXRT_GPIO9_16_31_BASE + 2) /* GPIO9 pin 18 interrupt */ +# define IMXRT_IRQ_GPIO9_19 (_IMXRT_GPIO9_16_31_BASE + 3) /* GPIO9 pin 19 interrupt */ +# define IMXRT_IRQ_GPIO9_20 (_IMXRT_GPIO9_16_31_BASE + 4) /* GPIO9 pin 20 interrupt */ +# define IMXRT_IRQ_GPIO9_21 (_IMXRT_GPIO9_16_31_BASE + 5) /* GPIO9 pin 21 interrupt */ +# define IMXRT_IRQ_GPIO9_22 (_IMXRT_GPIO9_16_31_BASE + 6) /* GPIO9 pin 22 interrupt */ +# define IMXRT_IRQ_GPIO9_23 (_IMXRT_GPIO9_16_31_BASE + 7) /* GPIO9 pin 23 interrupt */ +# define IMXRT_IRQ_GPIO9_24 (_IMXRT_GPIO9_16_31_BASE + 8) /* GPIO9 pin 24 interrupt */ +# define IMXRT_IRQ_GPIO9_25 (_IMXRT_GPIO9_16_31_BASE + 9) /* GPIO9 pin 25 interrupt */ +# define IMXRT_IRQ_GPIO9_26 (_IMXRT_GPIO9_16_31_BASE + 10) /* GPIO9 pin 26 interrupt */ +# define IMXRT_IRQ_GPIO9_27 (_IMXRT_GPIO9_16_31_BASE + 11) /* GPIO9 pin 27 interrupt */ +# define IMXRT_IRQ_GPIO9_28 (_IMXRT_GPIO9_16_31_BASE + 12) /* GPIO9 pin 28 interrupt */ +# define IMXRT_IRQ_GPIO9_29 (_IMXRT_GPIO9_16_31_BASE + 13) /* GPIO9 pin 29 interrupt */ +# define IMXRT_IRQ_GPIO9_30 (_IMXRT_GPIO9_16_31_BASE + 14) /* GPIO9 pin 30 interrupt */ +# define IMXRT_IRQ_GPIO9_31 (_IMXRT_GPIO9_16_31_BASE + 15) /* GPIO9 pin 31 interrupt */ + +# define _IMXRT_GPIO9_16_31_NIRQS 16 +# define IMXRT_GPIO9_NIRQS (_IMXRT_GPIO9_0_15_NIRQS + _IMXRT_GPIO9_16_31_NIRQS) +#else +# define IMXRT_GPIO9_NIRQS _IMXRT_GPIO9_0_15_NIRQS +#endif + +#define IMXRT_GPIO_NIRQS (IMXRT_GPIO1_NIRQS + IMXRT_GPIO2_NIRQS + \ + IMXRT_GPIO3_NIRQS + IMXRT_GPIO4_NIRQS + \ + IMXRT_GPIO5_NIRQS + IMXRT_GPIO6_NIRQS + \ + IMXRT_GPIO7_NIRQS + IMXRT_GPIO9_NIRQS + \ + IMXRT_GPIO9_NIRQS ) +#define IMXRT_GPIO_IRQ_LAST (_IMXRT_GPIO1_0_15_BASE + IMXRT_GPIO_NIRQS) + +/* Total number of IRQ numbers **********************************************************/ + +#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Inline functions + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Function Prototypes + ****************************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_IMXRT_IMXRT106X_IRQ_H */ diff --git a/arch/arm/include/imxrt/irq.h b/arch/arm/include/imxrt/irq.h index aa0521bdad..72bca14fab 100644 --- a/arch/arm/include/imxrt/irq.h +++ b/arch/arm/include/imxrt/irq.h @@ -2,7 +2,8 @@ * arch/arm/include/imxrt/irq.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -79,6 +80,8 @@ #if defined(CONFIG_ARCH_FAMILY_IMXRT105x) # include +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index d81556762f..87223e999b 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -28,6 +28,22 @@ config ARCH_CHIP_MIMXRT1052CVL5A bool "MIMXRT1052DVL6A" select ARCH_FAMILY_MIMXRT1052CVL5A +config ARCH_CHIP_MIMXRT1061DVL6A + bool "MIMXRT1061DVL6A" + select ARCH_FAMILY_MXRT106xDVL6A + +config ARCH_CHIP_MIMXRT1061CVL5A + bool "MIMXRT1061CVL5A" + select ARCH_FAMILY_IMIMXRT106xCVL5A + +config ARCH_CHIP_MIMXRT1062DVL6A + bool "MIMXRT1062DVL6A" + select ARCH_FAMILY_MXRT106xDVL6A + +config ARCH_CHIP_MIMXRT1062CVL5A + bool "MIMXRT1062DVL6A" + select ARCH_FAMILY_MIMXRT1062CVL5A + endchoice # i.MX RT Chip Selection # i.MX RT Families @@ -56,6 +72,31 @@ config ARCH_FAMILY_IMXRT105x select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM +config ARCH_FAMILY_MXRT106xDVL6A + bool + default n + select ARCH_FAMILY_IMXRT106x + ---help--- + i.MX RT1060 Crossover Processors for Consumer Products + +config ARCH_FAMILY_MIMXRT1062CVL5A + bool + default n + select ARCH_FAMILY_IMXRT106x + ---help--- + i.MX RT1056 Crossover Processors for Industrial Products + +config ARCH_FAMILY_IMXRT106x + bool + default n + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select IMXRT_HIGHSPEED_GPIO + # Peripheral support config IMXRT_HAVE_LPUART @@ -70,6 +111,10 @@ config IMXRT_LPSPI bool default n +config IMXRT_HIGHSPEED_GPIO + bool + default n + menu "i.MX RT Peripheral Selection" config IMXRT_EDMA @@ -327,6 +372,46 @@ config IMXRT_GPIO5_16_31_IRQ bool "GPIO5 Pins 16-31 interrupts" default n +config IMXRT_GPIO6_0_15_IRQ + bool "GPIO6 Pins 8-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO6_16_31_IRQ + bool "GPIO6 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO7_0_15_IRQ + bool "GPIO7 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO7_16_31_IRQ + bool "GPIO7 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO8_0_15_IRQ + bool "GPIO8 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO8_16_31_IRQ + bool "GPIO8 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO9_0_15_IRQ + bool "GPIO9 Pins 0-15 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + +config IMXRT_GPIO9_16_31_IRQ + bool "GPIO9 Pins 16-31 interrupts" + default n + depends on IMXRT_HIGHSPEED_GPIO + endif # IMXRT_GPIO_IRQ menu "Ethernet Configuration" @@ -446,7 +531,7 @@ config IMXRT_BOOT_SRAM endchoice # i.MX RT Boot Configuration choice - prompt "i.MX6 Primary RAM" + prompt "i.MX RT Primary RAM" default IMXRT_OCRAM_PRIMARY ---help--- The primary RAM is the RAM that contains the system BLOB's .data and @@ -464,7 +549,7 @@ config IMXRT_SRAM_PRIMARY bool "External SRAM primary" depends on IMXRT_SEMC_SRAM -endchoice # i.MX6 Primary RAM +endchoice # i.MX RT Primary RAM menu "i.MX RT Heap Configuration" @@ -512,7 +597,7 @@ config IMXRT_SRAM_HEAPOFFSET Used to reserve memory at the beginning of SRAM for, as an example, a framebuffer. -endmenu # i.MX6 Primary RAM +endmenu # i.MX RT Heap Configuration endmenu # Memory Configuration menu "USDHC Configuration" diff --git a/arch/arm/src/imxrt/chip/imxrt105x_gpio.h b/arch/arm/src/imxrt/chip/imxrt105x_gpio.h new file mode 100644 index 0000000000..c2dea41406 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt105x_gpio.h @@ -0,0 +1,127 @@ +/******************************************************************************************** + * arch/arm/src/imxrt/imxrt105x_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register offsets *************************************************************************/ + +#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ +#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ +#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ +#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ +#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ +#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ +#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ +#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ +#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */ +#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ +#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ + +/* Register addresses ***********************************************************************/ + +#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h new file mode 100644 index 0000000000..10c31f9ad1 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt105x_iomuxc.h @@ -0,0 +1,1991 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt105x_iomuxc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ + +/* Pad Mux Registers */ +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADMUX_GPIO_B0_00_INDEX 74 +#define IMXRT_PADMUX_GPIO_B0_01_INDEX 75 +#define IMXRT_PADMUX_GPIO_B0_02_INDEX 76 +#define IMXRT_PADMUX_GPIO_B0_03_INDEX 77 +#define IMXRT_PADMUX_GPIO_B0_04_INDEX 78 +#define IMXRT_PADMUX_GPIO_B0_05_INDEX 79 +#define IMXRT_PADMUX_GPIO_B0_06_INDEX 80 +#define IMXRT_PADMUX_GPIO_B0_07_INDEX 81 +#define IMXRT_PADMUX_GPIO_B0_08_INDEX 82 +#define IMXRT_PADMUX_GPIO_B0_09_INDEX 83 +#define IMXRT_PADMUX_GPIO_B0_10_INDEX 84 +#define IMXRT_PADMUX_GPIO_B0_11_INDEX 85 +#define IMXRT_PADMUX_GPIO_B0_12_INDEX 86 +#define IMXRT_PADMUX_GPIO_B0_13_INDEX 87 +#define IMXRT_PADMUX_GPIO_B0_14_INDEX 88 +#define IMXRT_PADMUX_GPIO_B0_15_INDEX 89 +#define IMXRT_PADMUX_GPIO_B1_00_INDEX 90 +#define IMXRT_PADMUX_GPIO_B1_01_INDEX 91 +#define IMXRT_PADMUX_GPIO_B1_02_INDEX 92 +#define IMXRT_PADMUX_GPIO_B1_03_INDEX 93 +#define IMXRT_PADMUX_GPIO_B1_04_INDEX 94 +#define IMXRT_PADMUX_GPIO_B1_05_INDEX 95 +#define IMXRT_PADMUX_GPIO_B1_06_INDEX 96 +#define IMXRT_PADMUX_GPIO_B1_07_INDEX 97 +#define IMXRT_PADMUX_GPIO_B1_08_INDEX 98 +#define IMXRT_PADMUX_GPIO_B1_09_INDEX 99 +#define IMXRT_PADMUX_GPIO_B1_10_INDEX 100 +#define IMXRT_PADMUX_GPIO_B1_11_INDEX 101 +#define IMXRT_PADMUX_GPIO_B1_12_INDEX 102 +#define IMXRT_PADMUX_GPIO_B1_13_INDEX 103 +#define IMXRT_PADMUX_GPIO_B1_14_INDEX 104 +#define IMXRT_PADMUX_GPIO_B1_15_INDEX 105 +#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 106 +#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 107 +#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 108 +#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 109 +#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 110 +#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 111 +#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 112 +#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 113 +#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 114 +#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 115 +#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 116 +#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 117 +#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 118 +#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 119 +#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 120 +#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 121 +#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 +#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 + +#define IMXRT_PADMUX_WAKEUP_INDEX 124 +#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 125 +#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 126 + +#define IMXRT_PADMUX_NREGISTERS 127 + +/* Pad Mux Register Offsets */ + +#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) +#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) + +#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 +#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 +#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c +#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 +#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 +#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 +#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c +#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 +#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 +#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 +#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c +#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 +#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 +#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 +#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c +#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 +#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 +#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 +#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c +#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 +#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 +#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 +#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c +#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 +#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 +#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 +#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c +#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 +#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 +#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 +#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c +#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 +#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 +#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 +#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c +#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 +#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 +#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 +#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac +#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 +#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 +#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 +#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc +#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 +#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 +#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 +#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc +#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 +#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 +#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 +#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc +#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 +#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 +#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 +#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec +#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 +#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 +#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 +#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc +#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 +#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 +#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 +#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c +#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 +#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 +#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 +#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c +#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 +#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 +#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 +#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c +#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 +#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 +#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 +#define IMXRT_PADMUX_GPIO_B0_00_OFFSET 0x013c +#define IMXRT_PADMUX_GPIO_B0_01_OFFSET 0x0140 +#define IMXRT_PADMUX_GPIO_B0_02_OFFSET 0x0144 +#define IMXRT_PADMUX_GPIO_B0_03_OFFSET 0x0148 +#define IMXRT_PADMUX_GPIO_B0_04_OFFSET 0x014c +#define IMXRT_PADMUX_GPIO_B0_05_OFFSET 0x0150 +#define IMXRT_PADMUX_GPIO_B0_06_OFFSET 0x0154 +#define IMXRT_PADMUX_GPIO_B0_07_OFFSET 0x0158 +#define IMXRT_PADMUX_GPIO_B0_08_OFFSET 0x015c +#define IMXRT_PADMUX_GPIO_B0_09_OFFSET 0x0160 +#define IMXRT_PADMUX_GPIO_B0_10_OFFSET 0x0164 +#define IMXRT_PADMUX_GPIO_B0_11_OFFSET 0x0168 +#define IMXRT_PADMUX_GPIO_B0_12_OFFSET 0x016c +#define IMXRT_PADMUX_GPIO_B0_13_OFFSET 0x0170 +#define IMXRT_PADMUX_GPIO_B0_14_OFFSET 0x0174 +#define IMXRT_PADMUX_GPIO_B0_15_OFFSET 0x0178 +#define IMXRT_PADMUX_GPIO_B1_00_OFFSET 0x017c +#define IMXRT_PADMUX_GPIO_B1_01_OFFSET 0x0180 +#define IMXRT_PADMUX_GPIO_B1_02_OFFSET 0x0184 +#define IMXRT_PADMUX_GPIO_B1_03_OFFSET 0x0188 +#define IMXRT_PADMUX_GPIO_B1_04_OFFSET 0x018c +#define IMXRT_PADMUX_GPIO_B1_05_OFFSET 0x0190 +#define IMXRT_PADMUX_GPIO_B1_06_OFFSET 0x0194 +#define IMXRT_PADMUX_GPIO_B1_07_OFFSET 0x0198 +#define IMXRT_PADMUX_GPIO_B1_08_OFFSET 0x019c +#define IMXRT_PADMUX_GPIO_B1_09_OFFSET 0x01a0 +#define IMXRT_PADMUX_GPIO_B1_10_OFFSET 0x01a4 +#define IMXRT_PADMUX_GPIO_B1_11_OFFSET 0x01a8 +#define IMXRT_PADMUX_GPIO_B1_12_OFFSET 0x01ac +#define IMXRT_PADMUX_GPIO_B1_13_OFFSET 0x01b0 +#define IMXRT_PADMUX_GPIO_B1_14_OFFSET 0x01b4 +#define IMXRT_PADMUX_GPIO_B1_15_OFFSET 0x01b8 +#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x01bc +#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x01c0 +#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x01c4 +#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x01c8 +#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x01cc +#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x01d0 +#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x01d4 +#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x01d8 +#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x01dc +#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x01e0 +#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x01e4 +#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x01e8 +#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x01ec +#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x01f0 +#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x01f4 +#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x01f8 +#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x01fc +#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0200 + +/* Pad Control Registers + * Pad Control Register Indices (used by software for table lookups) + */ + +#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADCTL_GPIO_B0_00_INDEX 74 +#define IMXRT_PADCTL_GPIO_B0_01_INDEX 75 +#define IMXRT_PADCTL_GPIO_B0_02_INDEX 76 +#define IMXRT_PADCTL_GPIO_B0_03_INDEX 77 +#define IMXRT_PADCTL_GPIO_B0_04_INDEX 78 +#define IMXRT_PADCTL_GPIO_B0_05_INDEX 79 +#define IMXRT_PADCTL_GPIO_B0_06_INDEX 80 +#define IMXRT_PADCTL_GPIO_B0_07_INDEX 81 +#define IMXRT_PADCTL_GPIO_B0_08_INDEX 82 +#define IMXRT_PADCTL_GPIO_B0_09_INDEX 83 +#define IMXRT_PADCTL_GPIO_B0_10_INDEX 84 +#define IMXRT_PADCTL_GPIO_B0_11_INDEX 85 +#define IMXRT_PADCTL_GPIO_B0_12_INDEX 86 +#define IMXRT_PADCTL_GPIO_B0_13_INDEX 87 +#define IMXRT_PADCTL_GPIO_B0_14_INDEX 88 +#define IMXRT_PADCTL_GPIO_B0_15_INDEX 89 +#define IMXRT_PADCTL_GPIO_B1_00_INDEX 90 +#define IMXRT_PADCTL_GPIO_B1_01_INDEX 91 +#define IMXRT_PADCTL_GPIO_B1_02_INDEX 92 +#define IMXRT_PADCTL_GPIO_B1_03_INDEX 93 +#define IMXRT_PADCTL_GPIO_B1_04_INDEX 94 +#define IMXRT_PADCTL_GPIO_B1_05_INDEX 95 +#define IMXRT_PADCTL_GPIO_B1_06_INDEX 96 +#define IMXRT_PADCTL_GPIO_B1_07_INDEX 97 +#define IMXRT_PADCTL_GPIO_B1_08_INDEX 98 +#define IMXRT_PADCTL_GPIO_B1_09_INDEX 99 +#define IMXRT_PADCTL_GPIO_B1_10_INDEX 100 +#define IMXRT_PADCTL_GPIO_B1_11_INDEX 101 +#define IMXRT_PADCTL_GPIO_B1_12_INDEX 102 +#define IMXRT_PADCTL_GPIO_B1_13_INDEX 103 +#define IMXRT_PADCTL_GPIO_B1_14_INDEX 104 +#define IMXRT_PADCTL_GPIO_B1_15_INDEX 105 +#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 106 +#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 107 +#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 108 +#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 109 +#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 110 +#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 111 +#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 112 +#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 113 +#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 114 +#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 115 +#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 116 +#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 117 +#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 118 +#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 119 +#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 120 +#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 121 +#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 +#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 + +#define IMXRT_PADCTL_WAKEUP_INDEX 124 +#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 125 +#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 126 + +#define IMXRT_PADCTL_NREGISTERS 127 + +/* Pad Control Register Offsets */ + +#define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) +#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n) << 2)) + +#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 +#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 +#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x020c +#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0210 +#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0214 +#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x0218 +#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x021c +#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x0220 +#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x0224 +#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x0228 +#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x022c +#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x0230 +#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x0234 +#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x0238 +#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x023c +#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x0240 +#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x0244 +#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x0248 +#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x024c +#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x0250 +#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x0254 +#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x0258 +#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x025c +#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x0260 +#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x0264 +#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x0268 +#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x026c +#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x0270 +#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x0274 +#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x0278 +#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x027c +#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0280 +#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0284 +#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x0288 +#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x028c +#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0290 +#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0294 +#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x0298 +#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x029c +#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x02a0 +#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x02a4 +#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x02a8 +#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x02ac +#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x02b0 +#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x02b4 +#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x02b8 +#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x02bc +#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x02c0 +#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x02c4 +#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x02c8 +#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x02cc +#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x02d0 +#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x02d4 +#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x02d8 +#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x02dc +#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x02e0 +#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x02e4 +#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x02e8 +#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x02ec +#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x02f0 +#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x02f4 +#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x02f8 +#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x02fc +#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0300 +#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0304 +#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x0308 +#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x030c +#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0310 +#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0314 +#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x0318 +#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x031c +#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x0320 +#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x0324 +#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x0328 +#define IMXRT_PADCTL_GPIO_B0_00_OFFSET 0x032c +#define IMXRT_PADCTL_GPIO_B0_01_OFFSET 0x0330 +#define IMXRT_PADCTL_GPIO_B0_02_OFFSET 0x0334 +#define IMXRT_PADCTL_GPIO_B0_03_OFFSET 0x0338 +#define IMXRT_PADCTL_GPIO_B0_04_OFFSET 0x033c +#define IMXRT_PADCTL_GPIO_B0_05_OFFSET 0x0340 +#define IMXRT_PADCTL_GPIO_B0_06_OFFSET 0x0344 +#define IMXRT_PADCTL_GPIO_B0_07_OFFSET 0x0348 +#define IMXRT_PADCTL_GPIO_B0_08_OFFSET 0x034c +#define IMXRT_PADCTL_GPIO_B0_09_OFFSET 0x0350 +#define IMXRT_PADCTL_GPIO_B0_10_OFFSET 0x0354 +#define IMXRT_PADCTL_GPIO_B0_11_OFFSET 0x0358 +#define IMXRT_PADCTL_GPIO_B0_12_OFFSET 0x035c +#define IMXRT_PADCTL_GPIO_B0_13_OFFSET 0x0360 +#define IMXRT_PADCTL_GPIO_B0_14_OFFSET 0x0364 +#define IMXRT_PADCTL_GPIO_B0_15_OFFSET 0x0368 +#define IMXRT_PADCTL_GPIO_B1_00_OFFSET 0x036c +#define IMXRT_PADCTL_GPIO_B1_01_OFFSET 0x0370 +#define IMXRT_PADCTL_GPIO_B1_02_OFFSET 0x0374 +#define IMXRT_PADCTL_GPIO_B1_03_OFFSET 0x0378 +#define IMXRT_PADCTL_GPIO_B1_04_OFFSET 0x037c +#define IMXRT_PADCTL_GPIO_B1_05_OFFSET 0x0380 +#define IMXRT_PADCTL_GPIO_B1_06_OFFSET 0x0384 +#define IMXRT_PADCTL_GPIO_B1_07_OFFSET 0x0388 +#define IMXRT_PADCTL_GPIO_B1_08_OFFSET 0x038c +#define IMXRT_PADCTL_GPIO_B1_09_OFFSET 0x0390 +#define IMXRT_PADCTL_GPIO_B1_10_OFFSET 0x0394 +#define IMXRT_PADCTL_GPIO_B1_11_OFFSET 0x0398 +#define IMXRT_PADCTL_GPIO_B1_12_OFFSET 0x039c +#define IMXRT_PADCTL_GPIO_B1_13_OFFSET 0x03a0 +#define IMXRT_PADCTL_GPIO_B1_14_OFFSET 0x03a4 +#define IMXRT_PADCTL_GPIO_B1_15_OFFSET 0x03a8 +#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x03ac +#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x03b0 +#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x03b4 +#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x03b8 +#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x03bc +#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x03c0 +#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x03c4 +#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x03c8 +#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x03cc +#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x03d0 +#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x03d4 +#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x03d8 +#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x03dc +#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x03e0 +#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x03e4 +#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x03e8 +#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x03ec +#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x03f0 + +/* Select Input Daisy Register Offsets */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x03f4 +#define IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET 0x03f8 +#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x03fc +#define IMXRT_INPUT_CSI_DATA02_OFFSET 0x0400 +#define IMXRT_INPUT_CSI_DATA03_OFFSET 0x0404 +#define IMXRT_INPUT_CSI_DATA04_OFFSET 0x0408 +#define IMXRT_INPUT_CSI_DATA05_OFFSET 0x040c +#define IMXRT_INPUT_CSI_DATA06_OFFSET 0x0410 +#define IMXRT_INPUT_CSI_DATA07_OFFSET 0x0414 +#define IMXRT_INPUT_CSI_DATA08_OFFSET 0x0418 +#define IMXRT_INPUT_CSI_DATA09_OFFSET 0x041c +#define IMXRT_INPUT_CSI_HSYNC_OFFSET 0x0420 +#define IMXRT_INPUT_CSI_PIXCLK_OFFSET 0x0424 +#define IMXRT_INPUT_CSI_VSYNC_OFFSET 0x0428 +#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x042c +#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0430 +#define IMXRT_INPUT_ENET0_RXDATA_OFFSET 0x0434 +#define IMXRT_INPUT_ENET1_RXDATA_OFFSET 0x0438 +#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x043c +#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0440 +#define IMXRT_INPUT_ENET0_TIMER_OFFSET 0x0444 +#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x0448 +#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x044c +#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0450 +#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0454 +#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0458 +#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x045c +#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0460 +#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0464 +#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0468 +#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x046c +#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0470 +#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0474 +#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0478 +#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x047c +#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0480 +#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0484 +#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0488 +#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x048c +#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0490 +#define IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET 0x0494 +#define IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET 0x0498 +#define IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET 0x049c +#define IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET 0x04a0 +#define IMXRT_INPUT_FLEXSPIA_DQS_OFFSET 0x04a4 +#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x04a8 +#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x04ac +#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x04b0 +#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x04b4 +#define IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET 0x04b8 +#define IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET 0x04bc +#define IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET 0x04c0 +#define IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET 0x04c4 +#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x04c8 +#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x04cc +#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x04d0 +#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x04d4 +#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x04d8 +#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x04dc +#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x04e0 +#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x04e4 +#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x04e8 +#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x04ec +#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x04f0 +#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x04f4 +#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x04f8 +#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x04fc +#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x0500 +#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x0504 +#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x0508 +#define IMXRT_INPUT_LPSPI3_PCS0_OFFSET 0x050c +#define IMXRT_INPUT_LPSPI3_SCK_OFFSET 0x0510 +#define IMXRT_INPUT_LPSPI3_SDI_OFFSET 0x0514 +#define IMXRT_INPUT_LPSPI3_SDO_OFFSET 0x0518 +#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x051c +#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x0520 +#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x0524 +#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x0528 +#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x052c +#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x0530 +#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x0534 +#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x0538 +#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x053c +#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x0540 +#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x0544 +#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x0548 +#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x054c +#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x0550 +#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x0554 +#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x0558 +#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x055c +#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0560 +#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0564 +#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x0568 +#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x056c +#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0570 +#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0574 +#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x0578 +#define IMXRT_INPUT_QTIMER3_TIMER0_OFFSET 0x057c +#define IMXRT_INPUT_QTIMER3_TIMER1_OFFSET 0x0580 +#define IMXRT_INPUT_QTIMER3_TIMER2_OFFSET 0x0584 +#define IMXRT_INPUT_QTIMER3_TIMER3_OFFSET 0x0588 +#define IMXRT_INPUT_SAI1_MCLK2_OFFSET 0x058c +#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0590 +#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0594 +#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x0598 +#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x059c +#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x05a0 +#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x05a4 +#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x05a8 +#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x05ac +#define IMXRT_INPUT_SAI2_MCLK2_OFFSET 0x05b0 +#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x05b4 +#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x05b8 +#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x05bc +#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x05c0 +#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x05c4 +#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x05c8 +#define IMXRT_INPUT_USB_OTG2_OC_OFFSET 0x05cc +#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x05d0 +#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x05d4 +#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x05d8 +#define IMXRT_INPUT_USDHC2_CLK_OFFSET 0x05dc +#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x05e0 +#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x05e4 +#define IMXRT_INPUT_USDHC2_DATA0_OFFSET 0x05e8 +#define IMXRT_INPUT_USDHC2_DATA1_OFFSET 0x05ec +#define IMXRT_INPUT_USDHC2_DATA2_OFFSET 0x05f0 +#define IMXRT_INPUT_USDHC2_DATA3_OFFSET 0x05f4 +#define IMXRT_INPUT_USDHC2_DATA4_OFFSET 0x05f8 +#define IMXRT_INPUT_USDHC2_DATA5_OFFSET 0x05fc +#define IMXRT_INPUT_USDHC2_DATA6_OFFSET 0x0600 +#define IMXRT_INPUT_USDHC2_DATA7_OFFSET 0x0604 +#define IMXRT_INPUT_USDHC2_WP_OFFSET 0x0608 +#define IMXRT_INPUT_XBAR1_IN02_OFFSET 0x060c +#define IMXRT_INPUT_XBAR1_IN03_OFFSET 0x0610 +#define IMXRT_INPUT_XBAR1_IN04_OFFSET 0x0614 +#define IMXRT_INPUT_XBAR1_IN05_OFFSET 0x0618 +#define IMXRT_INPUT_XBAR1_IN06_OFFSET 0x061c +#define IMXRT_INPUT_XBAR1_IN07_OFFSET 0x0620 +#define IMXRT_INPUT_XBAR1_IN08_OFFSET 0x0624 +#define IMXRT_INPUT_XBAR1_IN09_OFFSET 0x0628 +#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x062c +#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x0630 +#define IMXRT_INPUT_XBAR1_IN20_OFFSET 0x0634 +#define IMXRT_INPUT_XBAR1_IN22_OFFSET 0x0638 +#define IMXRT_INPUT_XBAR1_IN23_OFFSET 0x063c +#define IMXRT_INPUT_XBAR1_IN24_OFFSET 0x0640 +#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x0644 +#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x0648 +#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x064c +#define IMXRT_INPUT_XBAR1_IN25_OFFSET 0x0650 +#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 +#define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 + +/* Register addresses ***************************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) + +/* Pad Mux Registers */ + +#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) +#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) + +#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) + +/* Pad Control Registers */ + +#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) +#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) + +#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) + +/* Select Input Registers */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) +#define IMXRT_INPUT_ANATOP_USB_OTG2_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET) +#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) +#define IMXRT_INPUT_CSI_DATA02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA02_OFFSET) +#define IMXRT_INPUT_CSI_DATA03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA03_OFFSET) +#define IMXRT_INPUT_CSI_DATA04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA04_OFFSET) +#define IMXRT_INPUT_CSI_DATA05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA05_OFFSET) +#define IMXRT_INPUT_CSI_DATA06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA06_OFFSET) +#define IMXRT_INPUT_CSI_DATA07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA07_OFFSET) +#define IMXRT_INPUT_CSI_DATA08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA08_OFFSET) +#define IMXRT_INPUT_CSI_DATA09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA09_OFFSET) +#define IMXRT_INPUT_CSI_HSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_HSYNC_OFFSET) +#define IMXRT_INPUT_CSI_PIXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_PIXCLK_OFFSET) +#define IMXRT_INPUT_CSI_VSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_VSYNC_OFFSET) +#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) +#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) +#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) +#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) +#define IMXRT_INPUT_ENET0_TIMER (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_TIMER_OFFSET) +#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) +#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) +#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DQS (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DQS_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) +#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) +#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI3_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI3_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI3_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI3_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) +#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) +#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) +#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) +#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) +#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) +#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) +#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) +#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) +#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) +#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) +#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) +#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) +#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) +#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) +#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) +#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER3_OFFSET) +#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) +#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) +#define IMXRT_INPUT_USB_OTG2_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG2_OC_OFFSET) +#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) +#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) +#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) +#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC2_CMD (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CMD_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA0_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA1_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA2_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA3_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA4_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA5 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA5_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA6 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA6_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA7 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA7_OFFSET) +#define IMXRT_INPUT_USDHC2_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_WP_OFFSET) +#define IMXRT_INPUT_XBAR1_IN02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN02_OFFSET) +#define IMXRT_INPUT_XBAR1_IN03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN03_OFFSET) +#define IMXRT_INPUT_XBAR1_IN04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN04_OFFSET) +#define IMXRT_INPUT_XBAR1_IN05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) +#define IMXRT_INPUT_XBAR1_IN06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) +#define IMXRT_INPUT_XBAR1_IN07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN07_OFFSET) +#define IMXRT_INPUT_XBAR1_IN08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN08_OFFSET) +#define IMXRT_INPUT_XBAR1_IN09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN09_OFFSET) +#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) +#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) +#define IMXRT_INPUT_XBAR1_IN20 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN20_OFFSET) +#define IMXRT_INPUT_XBAR1_IN22 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN22_OFFSET) +#define IMXRT_INPUT_XBAR1_IN23 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN23_OFFSET) +#define IMXRT_INPUT_XBAR1_IN24 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN24_OFFSET) +#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) +#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) +#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) +#define IMXRT_INPUT_XBAR1_IN25 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN25_OFFSET) +#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) +#define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* General Purpose Register 0 (GPR0) - Reserved */ + +/* General Purpose Register 1 (GPR1) */ + +#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) +#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) +#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) +#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) +#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) +#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +#define GPR_GPR1_GINT (1 << 12) +#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) +#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) +#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) +#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) +#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) +#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) +#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) +#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) +#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) +#define GPR_GPR1_EXC_MON_OKAY (0 << 22) +#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) +#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) +#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) + +/* General Purpose Register 2 (GPR2) */ + +#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) +#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) +#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) +#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) +# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) +#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) +#define GPR_GPR2_MQS_EN (1 << 25) +#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) +#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) +#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) +#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) +#define GPR_GPR2_QTIM3_TMR_RESET (1 << 30) +#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) + +/* General Purpose Register 3 (GPR3) */ + +#define GPR_GPR3_OCRAM_CTL_SHIFT (0) +#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) +#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) +#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) +#define GPR_GPR3_OCRAM_STATUS_SHIFT (16) +#define GPR_GPR3_OCRAM_STATUS_MASK (15 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_STATUS_SHIFT) + +/* General Purpose Register 4 (GPR4) */ + +#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) +#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) +#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) +#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) +#define GPR_GPR4_ENET_STOP_REQ (1 << 4) +#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) +#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) +#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) +#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) +#define GPR_GPR4_PIT_STOP_REQ (1 << 10) +#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) +#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) +#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) +#define GPR_GRP4_EDMA_STOP_ACK (1 << 16) +#define GPR_GPR4_CAN1_STOP_ACK (1 << 17) +#define GPR_GPR4_CAN2_STOP_ACK (1 << 18) +#define GPR_GPR4_TRNG_STOP_ACK (1 << 19) +#define GPR_GPR4_ENET_STOP_ACK (1 << 20) +#define GPR_GPR4_SAI1_STOP_ACK (1 << 21) +#define GPR_GPR4_SAI2_STOP_ACK (1 << 22) +#define GPR_GPR4_SAI3_STOP_ACK (1 << 23) +#define GPR_GPR4_SEMC_STOP_ACK (1 << 25) +#define GPR_GPR4_PIT_STOP_ACK (1 << 26) +#define GPR_GPR4_FLEXSPI_STOP_ACK (1 << 27) +#define GPR_GPR4_FLEXIO1_STOP_ACK (1 << 28) +#define GPR_GPR4_FLEXIO2_STOP_ACK (1 << 29) + +/* General Purpose Register 5 (GPR5) */ + +#define GPR_GPR5_WDOG1_MASK (1 << 6) +#define GPR_GPR5_WDOG2_MASK (1 << 7) +#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) +#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) +#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET (0 << 25) +#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1 (1 << 25) +#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) +#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) + +/* General Purpose Register 6 (GPR6) */ + +#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0) +#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1) +#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2) +#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3) +#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4) +#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5) +#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6) +#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7) +#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8) +#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9) +#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10) +#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11) +#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12) +#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13) +#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14) +#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15) +#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) + +/* General Purpose Register 7 (GPR7) */ + +#define GPR_GPR7_LPI2C1_STOP_REQ (1 << 0) +#define GPR_GPR7_LPI2C2_STOP_REQ (1 << 1) +#define GPR_GPR7_LPI2C3_STOP_REQ (1 << 2) +#define GPR_GPR7_LPI2C4_STOP_REQ (1 << 3) +#define GPR_GPR7_LPSPI1_STOP_REQ (1 << 4) +#define GPR_GPR7_LPSPI2_STOP_REQ (1 << 5) +#define GPR_GPR7_LPSPI3_STOP_REQ (1 << 6) +#define GPR_GPR7_LPSPI4_STOP_REQ (1 << 7) +#define GPR_GPR7_LPUART1_STOP_REQ (1 << 8) +#define GPR_GPR7_LPUART2_STOP_REQ (1 << 9) +#define GPR_GPR7_LPUART3_STOP_REQ (1 << 10) +#define GPR_GPR7_LPUART4_STOP_REQ (1 << 11) +#define GPR_GPR7_LPUART5_STOP_REQ (1 << 12) +#define GPR_GPR7_LPUART6_STOP_REQ (1 << 13) +#define GPR_GPR7_LPUART7_STOP_REQ (1 << 14) +#define GPR_GPR7_LPUART8_STOP_REQ (1 << 15) +#define GPR_GPR7_LPI2C1_STOP_ACK (1 << 16) +#define GPR_GPR7_LPI2C2_STOP_ACK (1 << 17) +#define GPR_GPR7_LPI2C3_STOP_ACK (1 << 18) +#define GPR_GPR7_LPI2C4_STOP_ACK (1 << 19) +#define GPR_GPR7_LPSPI1_STOP_ACK (1 << 20) +#define GPR_GPR7_LPSPI2_STOP_ACK (1 << 21) +#define GPR_GPR7_LPSPI3_STOP_ACK (1 << 22) +#define GPR_GPR7_LPSPI4_STOP_ACK (1 << 23) +#define GPR_GPR7_LPUART1_STOP_ACK (1 << 24) +#define GPR_GPR7_LPUART2_STOP_ACK (1 << 25) +#define GPR_GPR7_LPUART3_STOP_ACK (1 << 26) +#define GPR_GPR7_LPUART4_STOP_ACK (1 << 27) +#define GPR_GPR7_LPUART5_STOP_ACK (1 << 28) +#define GPR_GPR7_LPUART6_STOP_ACK (1 << 29) +#define GPR_GPR7_LPUART7_STOP_ACK (1 << 30) +#define GPR_GPR7_LPUART8_STOP_ACK (1 << 31) + +/* General Purpose Register 8 (GPR8) */ + +#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0) +#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1) +#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_DOZED (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2) +#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3) +#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_DOZED (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4) +#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5) +#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_DOZED (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6) +#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7) +#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_DOZED (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8) +#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9) +#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_DOZED (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10) +#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11) +#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_DOZED (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12) +#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13) +#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_DOZED (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14) +#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15) +#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_DOZED (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16) +#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17) +#define GPR_GPR8_LPUART1_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_DOZED (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18) +#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19) +#define GPR_GPR8_LPUART2_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_DOZED (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20) +#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21) +#define GPR_GPR8_LPUART3_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_DOZED (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22) +#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23) +#define GPR_GPR8_LPUART4_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_DOZED (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24) +#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25) +#define GPR_GPR8_LPUART5_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_DOZED (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26) +#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27) +#define GPR_GPR8_LPUART6_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_DOZED (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28) +#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29) +#define GPR_GPR8_LPUART7_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_DOZED (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30) +#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31) +#define GPR_GPR8_LPUART8_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_DOZED (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) + +/* General Purpose Register 9 (GPR9) - Reserved */ + +/* General Purpose Register 10 (GPR10) */ + +#define GPR_GPR10_NIDEN (1 << 0) +#define GPR_GPR10_DBG_EN (1 << 1) +#define GPR_GPR10_SEC_ERR_RESP (1 << 2) +#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (1 << 4) +#define GPR_GPR10_OCRAM_TZ_EN (1 << 8) +#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9) +#define GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) +# define GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) +#define GPR_GPR10_LOCK_NIDEN (1 << 16) +#define GPR_GPR10_LOCK_DBG_EN (1 << 17) +#define GPR_GPR10_LOCK_SEC_ERR_RESP (1 << 18) +#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (1 << 20) +#define GPR_GPR10_LOCK_OCRAM_TZ_EN (1 << 24) +#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25) +#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) +# define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) + +/* General Purpose Register 11 (GPR11) */ + +#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS (0) +#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS (2) +#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS (4) +#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS (6) +#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS (8) +#define GPR_GPR11_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R0_EN (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R1_EN (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R2_EN (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R3_EN (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS (16) +#define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R0_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS (18) +#define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R1_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS (20) +#define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R2_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS (22) +#define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_FLEXSPI (2 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_LOCK_M7_APC_AC_R3_CTRL_SHIFTS) +#define GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS (24) +#define GPR_GPR11_LOCK_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R0_EN (1) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R1_EN (2) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R2_EN (4) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_LOCK_BEE_DE_R3_EN (8) << GPR_GPR11_LOCK_BEE_DE_RX_EN_SHIFTS) + +/* General Purpose Register 12 (GPR12) */ + +#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0) +#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1) +#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_DOZED (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2) +#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3) +#define GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_DOZED (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) +#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4) +#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_ACMP_IPG_ON_IN_STOP (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_ACMP_IPG_OFF_IN_STOP (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) + +/* General Purpose Register 13 (GPR13) */ + +#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE (1 << 0) +#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE (1 << 1) +#define GPR_GPR13_CACHE_ENET_CACHEABLE (1 << 7) +#define GPR_GPR13_CACHE_USB_CACHEABLE (1 << 13) + +/* General Purpose Register 14 (GPR14) */ + +#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (1 << 0) +#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (1 << 1) +#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (1 << 2) +#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (1 << 3) +#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (1 << 4) +#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (1 << 5) +#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (1 << 6) +#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (1 << 7) +#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (1 << 8) +#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (1 << 9) +#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (1 << 10) +#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (1 << 11) +#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16) +#define GPR_GPR14_CM7_CFGITCMSZ_MASK (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_0KB (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_4KB (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_8KB (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_16KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_32KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_64KB (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_128KB (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_256KB (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_512KB (10 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20) +#define GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_0KB (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_4KB (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_8KB (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_16KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_32KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_64KB (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_128KB (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_256KB (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_512KB (10 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) + +/* General Purpose Register 15 (GPR16) - Reserved */ + +/* General Purpose Register 16 (GPR16) */ + +#define GPR_GPR16_INIT_ITCM_EN (1 << 0) +#define GPR_GPR16_INIT_DTCM_EN (1 << 1) +#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF (1 << 2) +#define GPR_GPR16_CM7_INIT_VTOR_SHIFT (7) +#define GPR_GPR16_CM7_INIT_VTOR_MASK (0xffffff1 << GPR_GPR16_CM7_INIT_VTOR_SHIFT) +#define GPR_GPR16_CM7_INIT_VTOR(n) (((uint32_t)(n) & 0x1ffffff)) << GPR_GPR16_CM7_INIT_VTOR_SHIFT) + +/* General Purpose Register 17 (GPR17) */ + +#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0) +#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK_CFG(n) ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK0_SHIFT (0) +#define GPR_GPR17_FLEXRAM_BANK0_MASK (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_DTCM (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_ITCM (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK1_SHIFT (2) +#define GPR_GPR17_FLEXRAM_BANK1_MASK (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_DTCM (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_ITCM (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK2_SHIFT (4) +#define GPR_GPR17_FLEXRAM_BANK2_MASK (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_DTCM (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_ITCM (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK3_SHIFT (6) +#define GPR_GPR17_FLEXRAM_BANK3_MASK (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_DTCM (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_ITCM (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK4_SHIFT (8) +#define GPR_GPR17_FLEXRAM_BANK4_MASK (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_DTCM (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_ITCM (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK5_SHIFT (10) +#define GPR_GPR17_FLEXRAM_BANK5_MASK (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_DTCM (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_ITCM (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK6_SHIFT (12) +#define GPR_GPR17_FLEXRAM_BANK6_MASK (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_DTCM (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_ITCM (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK7_SHIFT (14) +#define GPR_GPR17_FLEXRAM_BANK7_MASK (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_DTCM (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_ITCM (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK8_SHIFT (16) +#define GPR_GPR17_FLEXRAM_BANK8_MASK (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_DTCM (2 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_ITCM (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK9_SHIFT (18) +#define GPR_GPR17_FLEXRAM_BANK9_MASK (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_DTCM (2 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_ITCM (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK10_SHIFT (20) +#define GPR_GPR17_FLEXRAM_BANK10_MASK (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_DTCM (2 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_ITCM (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK11_SHIFT (22) +#define GPR_GPR17_FLEXRAM_BANK11_MASK (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_DTCM (2 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_ITCM (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK12_SHIFT (24) +#define GPR_GPR17_FLEXRAM_BANK12_MASK (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_DTCM (2 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_ITCM (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK13_SHIFT (26) +#define GPR_GPR17_FLEXRAM_BANK13_MASK (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_DTCM (2 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_ITCM (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK14_SHIFT (28) +#define GPR_GPR17_FLEXRAM_BANK14_MASK (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_DTCM (2 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_ITCM (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK15_SHIFT (30) +#define GPR_GPR17_FLEXRAM_BANK15_MASK (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_DTCM (2 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_ITCM (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) + +/* General Purpose Register 18 (GPR18) */ + +#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (1 << 0) +#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3) +#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) +#define GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) + +/* General Purpose Register 19 (GPR19) */ + +#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (1 << 0) +#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3) +#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) +#define GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) + +/* General Purpose Register 20 (GPR20) */ + +#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (1 << 0) +#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3) +#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT) +#define GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT) + +/* General Purpose Register 21 (GPR21) */ + +#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (1 << 0) +#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3) +#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) +#define GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) + +/* General Purpose Register 22 (GPR22) */ + +#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (1 << 0) +#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3) +#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT) +#define GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT) + +/* General Purpose Register 23 (GPR23) */ + +#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (1 << 0) +#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3) +#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) +#define GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) + +/* General Purpose Register 24 (GPR24) */ + +#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (1 << 0) +#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3) +#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT) +#define GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT) + +/* General Purpose Register 25 (GPR25) */ + +#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (1 << 0) +#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3) +#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) +#define GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT105X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h b/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h index 31ce799baa..fe0ed3fa18 100644 --- a/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h +++ b/arch/arm/src/imxrt/chip/imxrt105x_memorymap.h @@ -54,7 +54,7 @@ #define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */ /* 0x00218000 416KB ROMCP Reserved */ /* 0x00280000 1536KB Reserved */ - /* 0x00400000 128MB Reserved */ + /* 0x00400000 124MB Reserved */ #define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ #define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ #define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ diff --git a/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h b/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h new file mode 100644 index 0000000000..52e9e84f29 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt106x_dmamux.h @@ -0,0 +1,174 @@ +/************************************************************************************ + * arch/arm/src/imxrt/chip/imxrt106x_dmamux.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Preprocessor Definitions + ************************************************************************************/ + +/* Peripheral DMA request channels */ + +#define IMXRT_DMACHAN_FLEXIO1 0 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ +#define IMXRT_DMACHAN_FLEXIO2 1 /* FlexIO1 DMA 0/1, Async DMA 0/1 */ +#define IMXRT_DMACHAN_LPUART1_TX 2 /* LPUART1 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART1_RX 3 /* LPUART1 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART3_TX 4 /* LPUART3 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART3_RX 5 /* LPUART3 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART5_TX 6 /* LPUART5 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART5_RX 7 /* LPUART5 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART7_TX 8 /* LPUART7 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART7_RX 9 /* LPUART7 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_CAN3 11 /* FLEXCAN3 DMA */ +#define IMXRT_DMACHAN_CSI 12 /* CSI Write DMA */ +#define IMXRT_DMACHAN_LPSPI1_RX 13 /* LPSPI1 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI1_TX 14 /* LPSPI1 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI3_RX 15 /* LPSPI3 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI3_TX 16 /* LPSPI3 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C1 17 /* LPI2C1 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C3 18 /* LPI2C3 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_SAI1_RX 19 /* SAI1 RX FIFO DMA */ +#define IMXRT_DMACHAN_SAI1_TX 20 /* SAI1 TX FIFO DMA */ +#define IMXRT_DMACHAN_SAI2_RX 21 /* SAI2 RX FIFO DMA */ +#define IMXRT_DMACHAN_SAI2_TX 22 /* SAI2 TX FIFO DMA */ +#define IMXRT_DMACHAN_ADC_ETC 23 /* ADC ETC DMA */ +#define IMXRT_DMACHAN_ADC1 24 /* ADC1 DMA */ +#define IMXRT_DMACHAN_ACMP1 25 /* ACMP1 DMA */ +#define IMXRT_DMACHAN_ACMP3 26 /* ACMP3 DMA */ +#define IMXRT_DMACHAN_FLEXSPI_RX 28 /* FlexSPI RX FIFO DMA */ +#define IMXRT_DMACHAN_FLEXSPI_TX 29 /* FlexSPI TX FIFO DMA */ +#define IMXRT_DMACHAN_XBAR1_0 30 /* XBAR1 DMA 0 */ +#define IMXRT_DMACHAN_XBAR1_1 31 /* XBAR1 DMA 1 */ +#define IMXRT_DMACHAN_FLEXPWM1_RX0 32 /* FlexPWM1 RX sub-module0 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_RX1 33 /* FlexPWM1 RX sub-module1 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_RX2 34 /* FlexPWM1 RX sub-module2 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_RX3 35 /* FlexPWM1 RX sub-module3 capture */ +#define IMXRT_DMACHAN_FLEXPWM1_TX0 36 /* FlexPWM1 TX sub-module0 value */ +#define IMXRT_DMACHAN_FLEXPWM1_TX1 37 /* FlexPWM1 TX sub-module1 value */ +#define IMXRT_DMACHAN_FLEXPWM1_TX2 38 /* FlexPWM1 TX sub-module2 value */ +#define IMXRT_DMACHAN_FLEXPWM1_TX3 39 /* FlexPWM1 TX sub-module3 value */ +#define IMXRT_DMACHAN_FLEXPWM3_RX0 40 /* FlexPWM3 RX sub-module0 capture */ +#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */ +#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */ +#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */ +#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */ +#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */ +#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */ +#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */ +#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */ +#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */ +#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */ +#define IMXRT_DMACHAN_QTIMER1_RX3 51 /* QTimer1 RX capture timer 3 */ +#define IMXRT_DMACHAN_QTIMER1_TX0 52 /* QTimer1 TX cmpld1 timer 0 / cmld2 timer 1 */ +#define IMXRT_DMACHAN_QTIMER1_TX1 53 /* QTimer1 TX cmpld1 timer 1 / cmld2 timer 0 */ +#define IMXRT_DMACHAN_QTIMER1_TX2 54 /* QTimer1 TX cmpld1 timer 2 / cmld2 timer 3 */ +#define IMXRT_DMACHAN_QTIMER1_TX3 55 /* QTimer1 TX cmpld1 timer 3 / cmld2 timer 2 */ +#define IMXRT_DMACHAN_QTIMER3_RXTX0 56 /* QTimer1 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */ +#define IMXRT_DMACHAN_QTIMER3_RXTX1 57 /* QTimer1 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */ +#define IMXRT_DMACHAN_QTIMER3_RXTX2 58 /* QTimer1 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */ +#define IMXRT_DMACHAN_QTIMER3_RXTX3 59 /* QTimer1 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */ +#define IMXRT_DMACHAN_FLEXSPI2_RX 60 /* FlexSPI2 RX FIFO DMA */ +#define IMXRT_DMACHAN_FLEXSPI2_TX 61 /* FlexSPI2 TX FIFO DMA */ +#define IMXRT_DMACHAN_FLEXIO1_01 64 /* FlexIO1 DMA 0 / Async DMA 0 / DMA 1 / Async DMA 1 */ +#define IMXRT_DMACHAN_FLEXIO2_23 65 /* FlexIO1 DMA 2 / Async DMA 2 / DMA 3 / Async DMA 3 */ +#define IMXRT_DMACHAN_LPUART2_TX 66 /* LPUART2 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART2_RX 67 /* LPUART2 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART4_TX 68 /* LPUART4 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART4_RX 69 /* LPUART4 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART6_TX 70 /* LPUART6 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART6_RX 71 /* LPUART6 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART8_TX 72 /* LPUART8 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPUART8_RX 73 /* LPUART8 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_PXP 75 /* PXP DMA Event */ +#define IMXRT_DMACHAN_LCDIF 76 /* LCDIF DMA Event */ +#define IMXRT_DMACHAN_LPSPI2_RX 77 /* LPSPI2 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI2_TX 78 /* LPSPI2 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI4_RX 79 /* LPSPI4 RX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPSPI4_TX 80 /* LPSPI4 TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C2 81 /* LPI2C2 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_LPI2C4 82 /* LPI2C4 Master/Slave RX/TX FIFO DMA / Async DMA */ +#define IMXRT_DMACHAN_SAI3_RX 83 /* SAI3 RX FIFO DMA */ +#define IMXRT_DMACHAN_SAI3_TX 84 /* SAI3 RX FIFO DMA */ +#define IMXRT_DMACHAN_SPDIF_RX 85 /* SPDIF RX DMA */ +#define IMXRT_DMACHAN_SPDIF_TX 86 /* SPDIF TX DMA */ +#define IMXRT_DMACHAN_ADC2 88 /* ADC2 DMA */ +#define IMXRT_DMACHAN_ACMP2 89 /* ACMP2 DMA */ +#define IMXRT_DMACHAN_ACMP4 90 /* ACMP4 DMA */ +#define IMXRT_DMACHAN_ENET_0 92 /* ENET Timer DMA 0 */ +#define IMXRT_DMACHAN_ENET_1 93 /* ENET Timer DMA 1 */ +#define IMXRT_DMACHAN_XBAR1_2 94 /* XBAR1 DMA 2 */ +#define IMXRT_DMACHAN_XBAR1_3 95 /* XBAR1 DMA 3 */ +#define IMXRT_DMACHAN_FLEXPWM2_RX0 96 /* FlexPWM2 RX sub-module0 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_RX1 97 /* FlexPWM2 RX sub-module1 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_RX2 98 /* FlexPWM2 RX sub-module2 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_RX3 99 /* FlexPWM2 RX sub-module3 capture */ +#define IMXRT_DMACHAN_FLEXPWM2_TX0 100 /* FlexPWM2 TX sub-module0 value */ +#define IMXRT_DMACHAN_FLEXPWM2_TX1 101 /* FlexPWM2 TX sub-module1 value */ +#define IMXRT_DMACHAN_FLEXPWM2_TX2 102 /* FlexPWM2 TX sub-module2 value */ +#define IMXRT_DMACHAN_FLEXPWM2_TX3 103 /* FlexPWM2 TX sub-module3 value */ +#define IMXRT_DMACHAN_FLEXPWM4_RX0 104 /* FlexPWM4 RX sub-module0 capture */ +#define IMXRT_DMACHAN_FLEXPWM4_RX1 105 /* FlexPWM4 RX sub-module1 capture */ +#define IMXRT_DMACHAN_FLEXPWM4_RX2 106 /* FlexPWM4 RX sub-module2 capture */ +#define IMXRT_DMACHAN_FLEXPWM4_RX3 107 /* FlexPWM4 RX sub-module3 capture */ +#define IMXRT_DMACHAN_FLEXPWM4_TX0 108 /* FlexPWM4 TX sub-module0 value */ +#define IMXRT_DMACHAN_FLEXPWM4_TX1 109 /* FlexPWM4 TX sub-module1 value */ +#define IMXRT_DMACHAN_FLEXPWM4_TX2 110 /* FlexPWM4 TX sub-module2 value */ +#define IMXRT_DMACHAN_FLEXPWM4_TX3 111 /* FlexPWM4 TX sub-module3 value */ +#define IMXRT_DMACHAN_QTIMER2_RX0 112 /* QTimer2 RX capture timer 0 */ +#define IMXRT_DMACHAN_QTIMER2_RX1 113 /* QTimer2 RX capture timer 1 */ +#define IMXRT_DMACHAN_QTIMER2_RX2 114 /* QTimer2 RX capture timer 2 */ +#define IMXRT_DMACHAN_QTIMER2_RX3 115 /* QTimer2 RX capture timer 3 */ +#define IMXRT_DMACHAN_QTIMER2_TX0 116 /* QTimer2 TX cmpld1 timer 0 / cmld2 timer 1 */ +#define IMXRT_DMACHAN_QTIMER2_TX1 117 /* QTimer2 TX cmpld1 timer 1 / cmld2 timer 0 */ +#define IMXRT_DMACHAN_QTIMER2_TX2 118 /* QTimer2 TX cmpld1 timer 2 / cmld2 timer 3 */ +#define IMXRT_DMACHAN_QTIMER2_TX3 119 /* QTimer2 TX cmpld1 timer 3 / cmld2 timer 2 */ +#define IMXRT_DMACHAN_QTIMER4_RXTX0 120 /* QTimer4 RX capture timer 0 / TX cmpld1 timer 0 / cmld2 timer 1 */ +#define IMXRT_DMACHAN_QTIMER4_RXTX1 121 /* QTimer4 RX capture timer 1 / TX cmpld1 timer 1 / cmld2 timer 0 */ +#define IMXRT_DMACHAN_QTIMER4_RXTX2 122 /* QTimer4 RX capture timer 2 / TX cmpld1 timer 2 / cmld2 timer 3 */ +#define IMXRT_DMACHAN_QTIMER4_RXTX3 123 /* QTimer4 RX capture timer 3 / TX cmpld1 timer 3 / cmld2 timer 2 */ +#define IMXRT_DMACHAN_ENET2_0 124 /* ENET2 Timer DMA 0 */ +#define IMXRT_DMACHAN_ENET2_1 125 /* ENET2 Timer DMA 1 */ + +#define IMXRT_DMA_NCHANNLES 128 /* Includes reserved channels */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_DMAMUX_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt106x_gpio.h b/arch/arm/src/imxrt/chip/imxrt106x_gpio.h new file mode 100644 index 0000000000..611ddfe350 --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt106x_gpio.h @@ -0,0 +1,175 @@ +/******************************************************************************************** + * arch/arm/src/imxrt/imxrt106x_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register offsets *************************************************************************/ + +#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ +#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ +#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ +#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ +#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ +#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ +#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ +#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ +#define IMXRT_GPIO_SET_OFFSET 0x0084 /* GPIO data register SET */ +#define IMXRT_GPIO_CLEAR_OFFSET 0x0088 /* GPIO data register CLEAR */ +#define IMXRT_GPIO_TOGGLE_OFFSET 0x008c /* GPIO data register TOGGLE */ + +/* Register addresses ***********************************************************************/ + +#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO1_SET (IMXRT_GPIO1_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO1_CLEAR (IMXRT_GPIO1_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO1_TOGGLE (IMXRT_GPIO1_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO2_SET (IMXRT_GPIO2_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO2_CLEAR (IMXRT_GPIO2_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO2_TOGGLE (IMXRT_GPIO2_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO3_SET (IMXRT_GPIO3_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO3_CLEAR (IMXRT_GPIO3_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO3_TOGGLE (IMXRT_GPIO3_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO4_SET (IMXRT_GPIO4_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO4_CLEAR (IMXRT_GPIO4_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO4_TOGGLE (IMXRT_GPIO4_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) +#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) +#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) +#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) +#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) +#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) +#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) +#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO5_SET (IMXRT_GPIO5_BASE + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO5_CLEAR (IMXRT_GPIO5_BASE + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO5_TOGGLE (IMXRT_GPIO5_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +# define IMXRT_GPIO6_DR (IMXRT_GPIO6_BASE + IMXRT_GPIO_DR_OFFSET) +# define IMXRT_GPIO6_GDIR (IMXRT_GPIO6_BASE + IMXRT_GPIO_GDIR_OFFSET) +# define IMXRT_GPIO6_PSR (IMXRT_GPIO6_BASE + IMXRT_GPIO_PSR_OFFSET) +# define IMXRT_GPIO6_ICR1 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR1_OFFSET) +# define IMXRT_GPIO6_ICR2 (IMXRT_GPIO6_BASE + IMXRT_GPIO_ICR2_OFFSET) +# define IMXRT_GPIO6_IMR (IMXRT_GPIO6_BASE + IMXRT_GPIO_IMR_OFFSET) +# define IMXRT_GPIO6_ISR (IMXRT_GPIO6_BASE + IMXRT_GPIO_ISR_OFFSET) +# define IMXRT_GPIO6_EDGE (IMXRT_GPIO6_BASE + IMXRT_GPIO_EDGE_OFFSET) +# define IMXRT_GPIO6_SET (IMXRT_GPIO6_BASE + IMXRT_GPIO_SET_OFFSET) +# define IMXRT_GPIO6_CLEAR (IMXRT_GPIO6_BASE + IMXRT_GPIO_CLEAR_OFFSET) +# define IMXRT_GPIO6_TOGGLE (IMXRT_GPIO6_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +# define IMXRT_GPIO7_DR (IMXRT_GPIO7_BASE + IMXRT_GPIO_DR_OFFSET) +# define IMXRT_GPIO7_GDIR (IMXRT_GPIO7_BASE + IMXRT_GPIO_GDIR_OFFSET) +# define IMXRT_GPIO7_PSR (IMXRT_GPIO7_BASE + IMXRT_GPIO_PSR_OFFSET) +# define IMXRT_GPIO7_ICR1 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR1_OFFSET) +# define IMXRT_GPIO7_ICR2 (IMXRT_GPIO7_BASE + IMXRT_GPIO_ICR2_OFFSET) +# define IMXRT_GPIO7_IMR (IMXRT_GPIO7_BASE + IMXRT_GPIO_IMR_OFFSET) +# define IMXRT_GPIO7_ISR (IMXRT_GPIO7_BASE + IMXRT_GPIO_ISR_OFFSET) +# define IMXRT_GPIO7_EDGE (IMXRT_GPIO7_BASE + IMXRT_GPIO_EDGE_OFFSET) +# define IMXRT_GPIO7_SET (IMXRT_GPIO7_BASE + IMXRT_GPIO_SET_OFFSET) +# define IMXRT_GPIO7_CLEAR (IMXRT_GPIO7_BASE + IMXRT_GPIO_CLEAR_OFFSET) +# define IMXRT_GPIO7_TOGGLE (IMXRT_GPIO7_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +# define IMXRT_GPIO8_DR (IMXRT_GPIO8_BASE + IMXRT_GPIO_DR_OFFSET) +# define IMXRT_GPIO8_GDIR (IMXRT_GPIO8_BASE + IMXRT_GPIO_GDIR_OFFSET) +# define IMXRT_GPIO8_PSR (IMXRT_GPIO8_BASE + IMXRT_GPIO_PSR_OFFSET) +# define IMXRT_GPIO8_ICR1 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR1_OFFSET) +# define IMXRT_GPIO8_ICR2 (IMXRT_GPIO8_BASE + IMXRT_GPIO_ICR2_OFFSET) +# define IMXRT_GPIO8_IMR (IMXRT_GPIO8_BASE + IMXRT_GPIO_IMR_OFFSET) +# define IMXRT_GPIO8_ISR (IMXRT_GPIO8_BASE + IMXRT_GPIO_ISR_OFFSET) +# define IMXRT_GPIO8_EDGE (IMXRT_GPIO8_BASE + IMXRT_GPIO_EDGE_OFFSET) +# define IMXRT_GPIO8_SET (IMXRT_GPIO8_BASE + IMXRT_GPIO_SET_OFFSET) +# define IMXRT_GPIO8_CLEAR (IMXRT_GPIO8_BASE + IMXRT_GPIO_CLEAR_OFFSET) +# define IMXRT_GPIO8_TOGGLE (IMXRT_GPIO8_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +# define IMXRT_GPIO9_DR (IMXRT_GPIO9_BASE + IMXRT_GPIO_DR_OFFSET) +# define IMXRT_GPIO9_GDIR (IMXRT_GPIO9_BASE + IMXRT_GPIO_GDIR_OFFSET) +# define IMXRT_GPIO9_PSR (IMXRT_GPIO9_BASE + IMXRT_GPIO_PSR_OFFSET) +# define IMXRT_GPIO9_ICR1 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR1_OFFSET) +# define IMXRT_GPIO9_ICR2 (IMXRT_GPIO9_BASE + IMXRT_GPIO_ICR2_OFFSET) +# define IMXRT_GPIO9_IMR (IMXRT_GPIO9_BASE + IMXRT_GPIO_IMR_OFFSET) +# define IMXRT_GPIO9_ISR (IMXRT_GPIO9_BASE + IMXRT_GPIO_ISR_OFFSET) +# define IMXRT_GPIO9_EDGE (IMXRT_GPIO9_BASE + IMXRT_GPIO_EDGE_OFFSET) +# define IMXRT_GPIO9_SET (IMXRT_GPIO9_BASE + IMXRT_GPIO_SET_OFFSET) +# define IMXRT_GPIO9_CLEAR (IMXRT_GPIO9_BASE + IMXRT_GPIO_CLEAR_OFFSET) +# define IMXRT_GPIO9_TOGGLE (IMXRT_GPIO9_BASE + IMXRT_GPIO_TOGGLE_OFFSET) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_GPIO_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h new file mode 100644 index 0000000000..8bc6a6e89e --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt106x_iomuxc.h @@ -0,0 +1,2543 @@ +/************************************************************************************ + * arch/arm/src/imxrt/imxrt_iomuxc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip/imxrt_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register offsets *****************************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR26_OFFSET 0x0068 /* GPR26 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR27_OFFSET 0x006C /* GPR27 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR28_OFFSET 0x0070 /* GPR28 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR29_OFFSET 0x0074 /* GPR29 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR30_OFFSET 0x0078 /* GPR30 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR31_OFFSET 0x007c /* GPR31 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR32_OFFSET 0x0080 /* GPR32 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR33_OFFSET 0x0084 /* GPR33 General Purpose Register*/ +#define IMXRT_IOMUXC_GPR_GPR34_OFFSET 0x0088 /* GPR34 General Purpose Register*/ + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ +#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ + +/* Pad Mux Registers */ +/* Pad Mux Register Indices (used by software for table lookups) */ + +#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADMUX_GPIO_B0_00_INDEX 74 +#define IMXRT_PADMUX_GPIO_B0_01_INDEX 75 +#define IMXRT_PADMUX_GPIO_B0_02_INDEX 76 +#define IMXRT_PADMUX_GPIO_B0_03_INDEX 77 +#define IMXRT_PADMUX_GPIO_B0_04_INDEX 78 +#define IMXRT_PADMUX_GPIO_B0_05_INDEX 79 +#define IMXRT_PADMUX_GPIO_B0_06_INDEX 80 +#define IMXRT_PADMUX_GPIO_B0_07_INDEX 81 +#define IMXRT_PADMUX_GPIO_B0_08_INDEX 82 +#define IMXRT_PADMUX_GPIO_B0_09_INDEX 83 +#define IMXRT_PADMUX_GPIO_B0_10_INDEX 84 +#define IMXRT_PADMUX_GPIO_B0_11_INDEX 85 +#define IMXRT_PADMUX_GPIO_B0_12_INDEX 86 +#define IMXRT_PADMUX_GPIO_B0_13_INDEX 87 +#define IMXRT_PADMUX_GPIO_B0_14_INDEX 88 +#define IMXRT_PADMUX_GPIO_B0_15_INDEX 89 +#define IMXRT_PADMUX_GPIO_B1_00_INDEX 90 +#define IMXRT_PADMUX_GPIO_B1_01_INDEX 91 +#define IMXRT_PADMUX_GPIO_B1_02_INDEX 92 +#define IMXRT_PADMUX_GPIO_B1_03_INDEX 93 +#define IMXRT_PADMUX_GPIO_B1_04_INDEX 94 +#define IMXRT_PADMUX_GPIO_B1_05_INDEX 95 +#define IMXRT_PADMUX_GPIO_B1_06_INDEX 96 +#define IMXRT_PADMUX_GPIO_B1_07_INDEX 97 +#define IMXRT_PADMUX_GPIO_B1_08_INDEX 98 +#define IMXRT_PADMUX_GPIO_B1_09_INDEX 99 +#define IMXRT_PADMUX_GPIO_B1_10_INDEX 100 +#define IMXRT_PADMUX_GPIO_B1_11_INDEX 101 +#define IMXRT_PADMUX_GPIO_B1_12_INDEX 102 +#define IMXRT_PADMUX_GPIO_B1_13_INDEX 103 +#define IMXRT_PADMUX_GPIO_B1_14_INDEX 104 +#define IMXRT_PADMUX_GPIO_B1_15_INDEX 105 +#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 106 +#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 107 +#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 108 +#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 109 +#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 110 +#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 111 +#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 112 +#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 113 +#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 114 +#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 115 +#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 116 +#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 117 +#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 118 +#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 119 +#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 120 +#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 121 +#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 +#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 + +#define IMXRT_PADMUX_WAKEUP_INDEX 124 +#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 125 +#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 126 + +#define IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX 127 +#define IMXRT_PADMUX_GPIO_SPI_B0_01_INDEX 128 +#define IMXRT_PADMUX_GPIO_SPI_B0_02_INDEX 129 +#define IMXRT_PADMUX_GPIO_SPI_B0_03_INDEX 130 +#define IMXRT_PADMUX_GPIO_SPI_B0_04_INDEX 131 +#define IMXRT_PADMUX_GPIO_SPI_B0_05_INDEX 132 +#define IMXRT_PADMUX_GPIO_SPI_B0_06_INDEX 133 +#define IMXRT_PADMUX_GPIO_SPI_B0_07_INDEX 134 +#define IMXRT_PADMUX_GPIO_SPI_B0_08_INDEX 135 +#define IMXRT_PADMUX_GPIO_SPI_B0_09_INDEX 136 +#define IMXRT_PADMUX_GPIO_SPI_B0_10_INDEX 137 +#define IMXRT_PADMUX_GPIO_SPI_B0_11_INDEX 138 +#define IMXRT_PADMUX_GPIO_SPI_B0_12_INDEX 139 +#define IMXRT_PADMUX_GPIO_SPI_B0_13_INDEX 140 +#define IMXRT_PADMUX_GPIO_SPI_B1_00_INDEX 141 +#define IMXRT_PADMUX_GPIO_SPI_B1_01_INDEX 142 +#define IMXRT_PADMUX_GPIO_SPI_B1_02_INDEX 143 +#define IMXRT_PADMUX_GPIO_SPI_B1_03_INDEX 144 +#define IMXRT_PADMUX_GPIO_SPI_B1_04_INDEX 145 +#define IMXRT_PADMUX_GPIO_SPI_B1_05_INDEX 146 +#define IMXRT_PADMUX_GPIO_SPI_B1_06_INDEX 147 +#define IMXRT_PADMUX_GPIO_SPI_B1_07_INDEX 148 + +#define IMXRT_PADMUX_NREGISTERS 149 + +/* Pad Mux Register Offsets */ + +#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) +#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) + +#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 +#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 +#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c +#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 +#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 +#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 +#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c +#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 +#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 +#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 +#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c +#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 +#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 +#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 +#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c +#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 +#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 +#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 +#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c +#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 +#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 +#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 +#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c +#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 +#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 +#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 +#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c +#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 +#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 +#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 +#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c +#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 +#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 +#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 +#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c +#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 +#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 +#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 +#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac +#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 +#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 +#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 +#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc +#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 +#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 +#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 +#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc +#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 +#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 +#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 +#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc +#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 +#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 +#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 +#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec +#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 +#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 +#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 +#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc +#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 +#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 +#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 +#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c +#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 +#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 +#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 +#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c +#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 +#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 +#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 +#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c +#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 +#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 +#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 +#define IMXRT_PADMUX_GPIO_B0_00_OFFSET 0x013c +#define IMXRT_PADMUX_GPIO_B0_01_OFFSET 0x0140 +#define IMXRT_PADMUX_GPIO_B0_02_OFFSET 0x0144 +#define IMXRT_PADMUX_GPIO_B0_03_OFFSET 0x0148 +#define IMXRT_PADMUX_GPIO_B0_04_OFFSET 0x014c +#define IMXRT_PADMUX_GPIO_B0_05_OFFSET 0x0150 +#define IMXRT_PADMUX_GPIO_B0_06_OFFSET 0x0154 +#define IMXRT_PADMUX_GPIO_B0_07_OFFSET 0x0158 +#define IMXRT_PADMUX_GPIO_B0_08_OFFSET 0x015c +#define IMXRT_PADMUX_GPIO_B0_09_OFFSET 0x0160 +#define IMXRT_PADMUX_GPIO_B0_10_OFFSET 0x0164 +#define IMXRT_PADMUX_GPIO_B0_11_OFFSET 0x0168 +#define IMXRT_PADMUX_GPIO_B0_12_OFFSET 0x016c +#define IMXRT_PADMUX_GPIO_B0_13_OFFSET 0x0170 +#define IMXRT_PADMUX_GPIO_B0_14_OFFSET 0x0174 +#define IMXRT_PADMUX_GPIO_B0_15_OFFSET 0x0178 +#define IMXRT_PADMUX_GPIO_B1_00_OFFSET 0x017c +#define IMXRT_PADMUX_GPIO_B1_01_OFFSET 0x0180 +#define IMXRT_PADMUX_GPIO_B1_02_OFFSET 0x0184 +#define IMXRT_PADMUX_GPIO_B1_03_OFFSET 0x0188 +#define IMXRT_PADMUX_GPIO_B1_04_OFFSET 0x018c +#define IMXRT_PADMUX_GPIO_B1_05_OFFSET 0x0190 +#define IMXRT_PADMUX_GPIO_B1_06_OFFSET 0x0194 +#define IMXRT_PADMUX_GPIO_B1_07_OFFSET 0x0198 +#define IMXRT_PADMUX_GPIO_B1_08_OFFSET 0x019c +#define IMXRT_PADMUX_GPIO_B1_09_OFFSET 0x01a0 +#define IMXRT_PADMUX_GPIO_B1_10_OFFSET 0x01a4 +#define IMXRT_PADMUX_GPIO_B1_11_OFFSET 0x01a8 +#define IMXRT_PADMUX_GPIO_B1_12_OFFSET 0x01ac +#define IMXRT_PADMUX_GPIO_B1_13_OFFSET 0x01b0 +#define IMXRT_PADMUX_GPIO_B1_14_OFFSET 0x01b4 +#define IMXRT_PADMUX_GPIO_B1_15_OFFSET 0x01b8 +#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x01bc +#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x01c0 +#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x01c4 +#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x01c8 +#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x01cc +#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x01d0 +#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x01d4 +#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x01d8 +#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x01dc +#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x01e0 +#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x01e4 +#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x01e8 +#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x01ec +#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x01f0 +#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x01f4 +#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x01f8 +#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x01fc +#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0200 + +/* Pad1 Mux Register Offsets */ + +#define IMXRT_PAD1MUX_OFFSET(n) (0x065c + ((unsigned int)(n) << 2)) + +#define IMXRT_PADMUX_GPIO_SPI_B0_00_OFFSET 0x065c +#define IMXRT_PADMUX_GPIO_SPI_B0_01_OFFSET 0x0660 +#define IMXRT_PADMUX_GPIO_SPI_B0_02_OFFSET 0x0664 +#define IMXRT_PADMUX_GPIO_SPI_B0_03_OFFSET 0x0668 +#define IMXRT_PADMUX_GPIO_SPI_B0_04_OFFSET 0x066c +#define IMXRT_PADMUX_GPIO_SPI_B0_05_OFFSET 0x0670 +#define IMXRT_PADMUX_GPIO_SPI_B0_06_OFFSET 0x0674 +#define IMXRT_PADMUX_GPIO_SPI_B0_07_OFFSET 0x0678 +#define IMXRT_PADMUX_GPIO_SPI_B0_08_OFFSET 0x067c +#define IMXRT_PADMUX_GPIO_SPI_B0_09_OFFSET 0x0680 +#define IMXRT_PADMUX_GPIO_SPI_B0_10_OFFSET 0x0684 +#define IMXRT_PADMUX_GPIO_SPI_B0_11_OFFSET 0x0688 +#define IMXRT_PADMUX_GPIO_SPI_B0_12_OFFSET 0x068c +#define IMXRT_PADMUX_GPIO_SPI_B0_13_OFFSET 0x0690 +#define IMXRT_PADMUX_GPIO_SPI_B1_00_OFFSET 0x0694 +#define IMXRT_PADMUX_GPIO_SPI_B1_01_OFFSET 0x0698 +#define IMXRT_PADMUX_GPIO_SPI_B1_02_OFFSET 0x069c +#define IMXRT_PADMUX_GPIO_SPI_B1_03_OFFSET 0x06a0 +#define IMXRT_PADMUX_GPIO_SPI_B1_04_OFFSET 0x06a4 +#define IMXRT_PADMUX_GPIO_SPI_B1_05_OFFSET 0x06a8 +#define IMXRT_PADMUX_GPIO_SPI_B1_06_OFFSET 0x06ac +#define IMXRT_PADMUX_GPIO_SPI_B1_07_OFFSET 0x06b0 + +/* Pad Control Registers + * Pad Control Register Indices (used by software for table lookups) + */ + +#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 +#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 +#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 +#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 +#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 +#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 +#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 +#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 +#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 +#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 +#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 +#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 +#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 +#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 +#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 +#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 +#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 +#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 +#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 +#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 +#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 +#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 +#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 +#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 +#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 +#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 +#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 +#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 +#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 +#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 +#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 +#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 +#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 +#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 +#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 +#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 +#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 +#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 +#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 +#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 +#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 +#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 +#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 +#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 +#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 +#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 +#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 +#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 +#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 +#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 +#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 +#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 +#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 +#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 +#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 +#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 +#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 +#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 +#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 +#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 +#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 +#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 +#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 +#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 +#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 +#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 +#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 +#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 +#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 +#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 +#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 +#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 +#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 +#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 +#define IMXRT_PADCTL_GPIO_B0_00_INDEX 74 +#define IMXRT_PADCTL_GPIO_B0_01_INDEX 75 +#define IMXRT_PADCTL_GPIO_B0_02_INDEX 76 +#define IMXRT_PADCTL_GPIO_B0_03_INDEX 77 +#define IMXRT_PADCTL_GPIO_B0_04_INDEX 78 +#define IMXRT_PADCTL_GPIO_B0_05_INDEX 79 +#define IMXRT_PADCTL_GPIO_B0_06_INDEX 80 +#define IMXRT_PADCTL_GPIO_B0_07_INDEX 81 +#define IMXRT_PADCTL_GPIO_B0_08_INDEX 82 +#define IMXRT_PADCTL_GPIO_B0_09_INDEX 83 +#define IMXRT_PADCTL_GPIO_B0_10_INDEX 84 +#define IMXRT_PADCTL_GPIO_B0_11_INDEX 85 +#define IMXRT_PADCTL_GPIO_B0_12_INDEX 86 +#define IMXRT_PADCTL_GPIO_B0_13_INDEX 87 +#define IMXRT_PADCTL_GPIO_B0_14_INDEX 88 +#define IMXRT_PADCTL_GPIO_B0_15_INDEX 89 +#define IMXRT_PADCTL_GPIO_B1_00_INDEX 90 +#define IMXRT_PADCTL_GPIO_B1_01_INDEX 91 +#define IMXRT_PADCTL_GPIO_B1_02_INDEX 92 +#define IMXRT_PADCTL_GPIO_B1_03_INDEX 93 +#define IMXRT_PADCTL_GPIO_B1_04_INDEX 94 +#define IMXRT_PADCTL_GPIO_B1_05_INDEX 95 +#define IMXRT_PADCTL_GPIO_B1_06_INDEX 96 +#define IMXRT_PADCTL_GPIO_B1_07_INDEX 97 +#define IMXRT_PADCTL_GPIO_B1_08_INDEX 98 +#define IMXRT_PADCTL_GPIO_B1_09_INDEX 99 +#define IMXRT_PADCTL_GPIO_B1_10_INDEX 100 +#define IMXRT_PADCTL_GPIO_B1_11_INDEX 101 +#define IMXRT_PADCTL_GPIO_B1_12_INDEX 102 +#define IMXRT_PADCTL_GPIO_B1_13_INDEX 103 +#define IMXRT_PADCTL_GPIO_B1_14_INDEX 104 +#define IMXRT_PADCTL_GPIO_B1_15_INDEX 105 +#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 106 +#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 107 +#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 108 +#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 109 +#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 110 +#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 111 +#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 112 +#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 113 +#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 114 +#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 115 +#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 116 +#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 117 +#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 118 +#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 119 +#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 120 +#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 121 +#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 +#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 + +#define IMXRT_PADCTL_WAKEUP_INDEX 124 +#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 125 +#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 126 + +#define IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX 127 +#define IMXRT_PADCTL_GPIO_SPI_B0_01_INDEX 128 +#define IMXRT_PADCTL_GPIO_SPI_B0_02_INDEX 129 +#define IMXRT_PADCTL_GPIO_SPI_B0_03_INDEX 130 +#define IMXRT_PADCTL_GPIO_SPI_B0_04_INDEX 131 +#define IMXRT_PADCTL_GPIO_SPI_B0_05_INDEX 132 +#define IMXRT_PADCTL_GPIO_SPI_B0_06_INDEX 133 +#define IMXRT_PADCTL_GPIO_SPI_B0_07_INDEX 134 +#define IMXRT_PADCTL_GPIO_SPI_B0_08_INDEX 135 +#define IMXRT_PADCTL_GPIO_SPI_B0_09_INDEX 136 +#define IMXRT_PADCTL_GPIO_SPI_B0_10_INDEX 137 +#define IMXRT_PADCTL_GPIO_SPI_B0_11_INDEX 138 +#define IMXRT_PADCTL_GPIO_SPI_B0_12_INDEX 139 +#define IMXRT_PADCTL_GPIO_SPI_B0_13_INDEX 140 +#define IMXRT_PADCTL_GPIO_SPI_B1_00_INDEX 141 +#define IMXRT_PADCTL_GPIO_SPI_B1_01_INDEX 142 +#define IMXRT_PADCTL_GPIO_SPI_B1_02_INDEX 143 +#define IMXRT_PADCTL_GPIO_SPI_B1_03_INDEX 144 +#define IMXRT_PADCTL_GPIO_SPI_B1_04_INDEX 145 +#define IMXRT_PADCTL_GPIO_SPI_B1_05_INDEX 146 +#define IMXRT_PADCTL_GPIO_SPI_B1_06_INDEX 147 +#define IMXRT_PADCTL_GPIO_SPI_B1_07_INDEX 148 + +#define IMXRT_PADCTL_NREGISTERS 149 + +/* Pad Control Register Offsets */ + +#define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) +#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n) << 2)) + +#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 +#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 +#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x020c +#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0210 +#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0214 +#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x0218 +#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x021c +#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x0220 +#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x0224 +#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x0228 +#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x022c +#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x0230 +#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x0234 +#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x0238 +#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x023c +#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x0240 +#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x0244 +#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x0248 +#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x024c +#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x0250 +#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x0254 +#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x0258 +#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x025c +#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x0260 +#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x0264 +#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x0268 +#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x026c +#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x0270 +#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x0274 +#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x0278 +#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x027c +#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0280 +#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0284 +#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x0288 +#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x028c +#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0290 +#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0294 +#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x0298 +#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x029c +#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x02a0 +#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x02a4 +#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x02a8 +#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x02ac +#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x02b0 +#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x02b4 +#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x02b8 +#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x02bc +#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x02c0 +#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x02c4 +#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x02c8 +#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x02cc +#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x02d0 +#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x02d4 +#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x02d8 +#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x02dc +#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x02e0 +#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x02e4 +#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x02e8 +#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x02ec +#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x02f0 +#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x02f4 +#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x02f8 +#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x02fc +#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0300 +#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0304 +#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x0308 +#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x030c +#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0310 +#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0314 +#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x0318 +#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x031c +#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x0320 +#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x0324 +#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x0328 +#define IMXRT_PADCTL_GPIO_B0_00_OFFSET 0x032c +#define IMXRT_PADCTL_GPIO_B0_01_OFFSET 0x0330 +#define IMXRT_PADCTL_GPIO_B0_02_OFFSET 0x0334 +#define IMXRT_PADCTL_GPIO_B0_03_OFFSET 0x0338 +#define IMXRT_PADCTL_GPIO_B0_04_OFFSET 0x033c +#define IMXRT_PADCTL_GPIO_B0_05_OFFSET 0x0340 +#define IMXRT_PADCTL_GPIO_B0_06_OFFSET 0x0344 +#define IMXRT_PADCTL_GPIO_B0_07_OFFSET 0x0348 +#define IMXRT_PADCTL_GPIO_B0_08_OFFSET 0x034c +#define IMXRT_PADCTL_GPIO_B0_09_OFFSET 0x0350 +#define IMXRT_PADCTL_GPIO_B0_10_OFFSET 0x0354 +#define IMXRT_PADCTL_GPIO_B0_11_OFFSET 0x0358 +#define IMXRT_PADCTL_GPIO_B0_12_OFFSET 0x035c +#define IMXRT_PADCTL_GPIO_B0_13_OFFSET 0x0360 +#define IMXRT_PADCTL_GPIO_B0_14_OFFSET 0x0364 +#define IMXRT_PADCTL_GPIO_B0_15_OFFSET 0x0368 +#define IMXRT_PADCTL_GPIO_B1_00_OFFSET 0x036c +#define IMXRT_PADCTL_GPIO_B1_01_OFFSET 0x0370 +#define IMXRT_PADCTL_GPIO_B1_02_OFFSET 0x0374 +#define IMXRT_PADCTL_GPIO_B1_03_OFFSET 0x0378 +#define IMXRT_PADCTL_GPIO_B1_04_OFFSET 0x037c +#define IMXRT_PADCTL_GPIO_B1_05_OFFSET 0x0380 +#define IMXRT_PADCTL_GPIO_B1_06_OFFSET 0x0384 +#define IMXRT_PADCTL_GPIO_B1_07_OFFSET 0x0388 +#define IMXRT_PADCTL_GPIO_B1_08_OFFSET 0x038c +#define IMXRT_PADCTL_GPIO_B1_09_OFFSET 0x0390 +#define IMXRT_PADCTL_GPIO_B1_10_OFFSET 0x0394 +#define IMXRT_PADCTL_GPIO_B1_11_OFFSET 0x0398 +#define IMXRT_PADCTL_GPIO_B1_12_OFFSET 0x039c +#define IMXRT_PADCTL_GPIO_B1_13_OFFSET 0x03a0 +#define IMXRT_PADCTL_GPIO_B1_14_OFFSET 0x03a4 +#define IMXRT_PADCTL_GPIO_B1_15_OFFSET 0x03a8 +#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x03ac +#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x03b0 +#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x03b4 +#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x03b8 +#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x03bc +#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x03c0 +#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x03c4 +#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x03c8 +#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x03cc +#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x03d0 +#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x03d4 +#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x03d8 +#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x03dc +#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x03e0 +#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x03e4 +#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x03e8 +#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x03ec +#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x03f0 + +/* Pad1 Control Register Offsets */ + +#define IMXRT_PAD1CTL_OFFSET(n) (0x06b4 + ((unsigned int)(n) << 2)) + +#define IMXRT_PADCTL_GPIO_SPI_B0_00_OFFSET 0x06b4 +#define IMXRT_PADCTL_GPIO_SPI_B0_01_OFFSET 0x06b8 +#define IMXRT_PADCTL_GPIO_SPI_B0_02_OFFSET 0x06bc +#define IMXRT_PADCTL_GPIO_SPI_B0_03_OFFSET 0x06c0 +#define IMXRT_PADCTL_GPIO_SPI_B0_04_OFFSET 0x06c4 +#define IMXRT_PADCTL_GPIO_SPI_B0_05_OFFSET 0x06c8 +#define IMXRT_PADCTL_GPIO_SPI_B0_06_OFFSET 0x06cc +#define IMXRT_PADCTL_GPIO_SPI_B0_07_OFFSET 0x06d0 +#define IMXRT_PADCTL_GPIO_SPI_B0_08_OFFSET 0x06d4 +#define IMXRT_PADCTL_GPIO_SPI_B0_09_OFFSET 0x06d8 +#define IMXRT_PADCTL_GPIO_SPI_B0_10_OFFSET 0x06dc +#define IMXRT_PADCTL_GPIO_SPI_B0_11_OFFSET 0x06e0 +#define IMXRT_PADCTL_GPIO_SPI_B0_12_OFFSET 0x06e4 +#define IMXRT_PADCTL_GPIO_SPI_B0_13_OFFSET 0x06e8 +#define IMXRT_PADCTL_GPIO_SPI_B1_00_OFFSET 0x06ec +#define IMXRT_PADCTL_GPIO_SPI_B1_01_OFFSET 0x06f0 +#define IMXRT_PADCTL_GPIO_SPI_B1_02_OFFSET 0x06f4 +#define IMXRT_PADCTL_GPIO_SPI_B1_03_OFFSET 0x06f8 +#define IMXRT_PADCTL_GPIO_SPI_B1_04_OFFSET 0x06fc +#define IMXRT_PADCTL_GPIO_SPI_B1_05_OFFSET 0x0700 +#define IMXRT_PADCTL_GPIO_SPI_B1_06_OFFSET 0x0704 +#define IMXRT_PADCTL_GPIO_SPI_B1_07_OFFSET 0x0708 + +/* Select Input Daisy Register Offsets */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x03f4 +#define IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET 0x03f8 +#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x03fc +#define IMXRT_INPUT_CSI_DATA02_OFFSET 0x0400 +#define IMXRT_INPUT_CSI_DATA03_OFFSET 0x0404 +#define IMXRT_INPUT_CSI_DATA04_OFFSET 0x0408 +#define IMXRT_INPUT_CSI_DATA05_OFFSET 0x040c +#define IMXRT_INPUT_CSI_DATA06_OFFSET 0x0410 +#define IMXRT_INPUT_CSI_DATA07_OFFSET 0x0414 +#define IMXRT_INPUT_CSI_DATA08_OFFSET 0x0418 +#define IMXRT_INPUT_CSI_DATA09_OFFSET 0x041c +#define IMXRT_INPUT_CSI_HSYNC_OFFSET 0x0420 +#define IMXRT_INPUT_CSI_PIXCLK_OFFSET 0x0424 +#define IMXRT_INPUT_CSI_VSYNC_OFFSET 0x0428 +#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x042c +#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0430 +#define IMXRT_INPUT_ENET0_RXDATA_OFFSET 0x0434 +#define IMXRT_INPUT_ENET1_RXDATA_OFFSET 0x0438 +#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x043c +#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0440 +#define IMXRT_INPUT_ENET0_TIMER_OFFSET 0x0444 +#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x0448 +#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x044c +#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0450 +#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0454 +#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0458 +#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x045c +#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0460 +#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0464 +#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0468 +#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x046c +#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0470 +#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0474 +#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0478 +#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x047c +#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0480 +#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0484 +#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0488 +#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x048c +#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0490 +#define IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET 0x0494 +#define IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET 0x0498 +#define IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET 0x049c +#define IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET 0x04a0 +#define IMXRT_INPUT_FLEXSPIA_DQS_OFFSET 0x04a4 +#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x04a8 +#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x04ac +#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x04b0 +#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x04b4 +#define IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET 0x04b8 +#define IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET 0x04bc +#define IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET 0x04c0 +#define IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET 0x04c4 +#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x04c8 +#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x04cc +#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x04d0 +#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x04d4 +#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x04d8 +#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x04dc +#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x04e0 +#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x04e4 +#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x04e8 +#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x04ec +#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x04f0 +#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x04f4 +#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x04f8 +#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x04fc +#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x0500 +#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x0504 +#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x0508 +#define IMXRT_INPUT_LPSPI3_PCS0_OFFSET 0x050c +#define IMXRT_INPUT_LPSPI3_SCK_OFFSET 0x0510 +#define IMXRT_INPUT_LPSPI3_SDI_OFFSET 0x0514 +#define IMXRT_INPUT_LPSPI3_SDO_OFFSET 0x0518 +#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x051c +#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x0520 +#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x0524 +#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x0528 +#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x052c +#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x0530 +#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x0534 +#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x0538 +#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x053c +#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x0540 +#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x0544 +#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x0548 +#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x054c +#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x0550 +#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x0554 +#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x0558 +#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x055c +#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0560 +#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0564 +#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x0568 +#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x056c +#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0570 +#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0574 +#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x0578 +#define IMXRT_INPUT_QTIMER3_TIMER0_OFFSET 0x057c +#define IMXRT_INPUT_QTIMER3_TIMER1_OFFSET 0x0580 +#define IMXRT_INPUT_QTIMER3_TIMER2_OFFSET 0x0584 +#define IMXRT_INPUT_QTIMER3_TIMER3_OFFSET 0x0588 +#define IMXRT_INPUT_SAI1_MCLK2_OFFSET 0x058c +#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0590 +#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0594 +#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x0598 +#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x059c +#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x05a0 +#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x05a4 +#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x05a8 +#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x05ac +#define IMXRT_INPUT_SAI2_MCLK2_OFFSET 0x05b0 +#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x05b4 +#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x05b8 +#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x05bc +#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x05c0 +#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x05c4 +#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x05c8 +#define IMXRT_INPUT_USB_OTG2_OC_OFFSET 0x05cc +#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x05d0 +#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x05d4 +#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x05d8 +#define IMXRT_INPUT_USDHC2_CLK_OFFSET 0x05dc +#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x05e0 +#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x05e4 +#define IMXRT_INPUT_USDHC2_DATA0_OFFSET 0x05e8 +#define IMXRT_INPUT_USDHC2_DATA1_OFFSET 0x05ec +#define IMXRT_INPUT_USDHC2_DATA2_OFFSET 0x05f0 +#define IMXRT_INPUT_USDHC2_DATA3_OFFSET 0x05f4 +#define IMXRT_INPUT_USDHC2_DATA4_OFFSET 0x05f8 +#define IMXRT_INPUT_USDHC2_DATA5_OFFSET 0x05fc +#define IMXRT_INPUT_USDHC2_DATA6_OFFSET 0x0600 +#define IMXRT_INPUT_USDHC2_DATA7_OFFSET 0x0604 +#define IMXRT_INPUT_USDHC2_WP_OFFSET 0x0608 +#define IMXRT_INPUT_XBAR1_IN02_OFFSET 0x060c +#define IMXRT_INPUT_XBAR1_IN03_OFFSET 0x0610 +#define IMXRT_INPUT_XBAR1_IN04_OFFSET 0x0614 +#define IMXRT_INPUT_XBAR1_IN05_OFFSET 0x0618 +#define IMXRT_INPUT_XBAR1_IN06_OFFSET 0x061c +#define IMXRT_INPUT_XBAR1_IN07_OFFSET 0x0620 +#define IMXRT_INPUT_XBAR1_IN08_OFFSET 0x0624 +#define IMXRT_INPUT_XBAR1_IN09_OFFSET 0x0628 +#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x062c +#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x0630 +#define IMXRT_INPUT_XBAR1_IN20_OFFSET 0x0634 +#define IMXRT_INPUT_XBAR1_IN22_OFFSET 0x0638 +#define IMXRT_INPUT_XBAR1_IN23_OFFSET 0x063c +#define IMXRT_INPUT_XBAR1_IN24_OFFSET 0x0640 +#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x0644 +#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x0648 +#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x064c +#define IMXRT_INPUT_XBAR1_IN25_OFFSET 0x0650 +#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 +#define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 + +/* Select1 Input Daisy Register Offsets */ + +#define IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET 0x070C +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET 0x0710 +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET 0x0714 +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET 0x0718 +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET 0x071C +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET 0x0720 +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET 0x0724 +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET 0x0728 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET 0x072C +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET 0x0730 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET 0x0734 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET 0x0738 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET 0x073C +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET 0x0740 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET 0x0744 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET 0x0748 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET 0x074C +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET 0x0750 +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET 0x0754 +#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET 0x0758 +#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET 0x075C +#define IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET 0x0760 +#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET 0x0764 +#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET 0x0768 +#define IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET 0x076C +#define IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET 0x0770 +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET 0x0774 +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET 0x0778 +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET 0x077C +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET 0x0780 +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET 0x0784 +#define IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET 0x0788 +#define IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET 0x078C + +/* Register addresses ***************************************************************/ + +#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR26 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR26_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR27 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR27_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR28 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR28_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR29 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR29_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR30 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR30_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR31 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR31_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR32 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR32_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR33 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR33_OFFSET) +#define IMXRT_IOMUXC_GPR_GPR34 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR34_OFFSET) + +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) +#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) + +#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) +#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) + +/* Pad Mux Registers */ + +#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) +#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) + +#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) +#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_14_OFFSET) +#define IMXRT_PADMUX_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_15_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_11_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_12_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_13_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_14_OFFSET) +#define IMXRT_PADMUX_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_15_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) + +/* Pad1 Mux Registers */ + +#define IMXRT_PAD1MUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PAD1MUX_OFFSET(n)) + +#define IMXRT_PADMUX_GPIO_SPI_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_07_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_08_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_09_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_10_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_11_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_12_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B0_13_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_00_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_01_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_02_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_03_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_04_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_05_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_06_OFFSET) +#define IMXRT_PADMUX_GPIO_SPI_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SPI_B1_07_OFFSET) + +/* Pad Control Registers */ + +#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) +#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) + +#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) +#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_14_OFFSET) +#define IMXRT_PADCTL_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_15_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_11_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_12_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_13_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_14_OFFSET) +#define IMXRT_PADCTL_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_15_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) +#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) + +/* Pad1 Control Registers */ + +#define IMXRT_PAD1CTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PAD1CTL_OFFSET(n)) + +#define IMXRT_PADCTL_GPIO_SPI_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_07_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_08_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_09_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_10_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_11_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_12_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B0_13_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_00_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_01_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_02_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_03_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_04_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_05_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_06_OFFSET) +#define IMXRT_PADCTL_GPIO_SPI_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SPI_B1_07_OFFSET) + +/* Select Input Registers */ + +#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) +#define IMXRT_INPUT_ANATOP_USB_OTG2_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET) +#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) +#define IMXRT_INPUT_CSI_DATA02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA02_OFFSET) +#define IMXRT_INPUT_CSI_DATA03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA03_OFFSET) +#define IMXRT_INPUT_CSI_DATA04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA04_OFFSET) +#define IMXRT_INPUT_CSI_DATA05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA05_OFFSET) +#define IMXRT_INPUT_CSI_DATA06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA06_OFFSET) +#define IMXRT_INPUT_CSI_DATA07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA07_OFFSET) +#define IMXRT_INPUT_CSI_DATA08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA08_OFFSET) +#define IMXRT_INPUT_CSI_DATA09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA09_OFFSET) +#define IMXRT_INPUT_CSI_HSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_HSYNC_OFFSET) +#define IMXRT_INPUT_CSI_PIXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_PIXCLK_OFFSET) +#define IMXRT_INPUT_CSI_VSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_VSYNC_OFFSET) +#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) +#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) +#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) +#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) +#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) +#define IMXRT_INPUT_ENET0_TIMER (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_TIMER_OFFSET) +#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) +#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) +#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) +#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET) +#define IMXRT_INPUT_FLEXPWM4_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DQS (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DQS_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET) +#define IMXRT_INPUT_FLEXSPIB_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET) +#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) +#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) +#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) +#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) +#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI3_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI3_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI3_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI3_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDO_OFFSET) +#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) +#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) +#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) +#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) +#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) +#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) +#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) +#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) +#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) +#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) +#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) +#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) +#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) +#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) +#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) +#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) +#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) +#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) +#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER0_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER1_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER2_OFFSET) +#define IMXRT_INPUT_QTIMER3_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER3_OFFSET) +#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) +#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) +#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) +#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) +#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) +#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) +#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) +#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) +#define IMXRT_INPUT_USB_OTG2_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG2_OC_OFFSET) +#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) +#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) +#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) +#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) +#define IMXRT_INPUT_USDHC2_CMD (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CMD_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA0_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA1_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA2_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA3_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA4_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA5 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA5_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA6 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA6_OFFSET) +#define IMXRT_INPUT_USDHC2_DATA7 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA7_OFFSET) +#define IMXRT_INPUT_USDHC2_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_WP_OFFSET) +#define IMXRT_INPUT_XBAR1_IN02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN02_OFFSET) +#define IMXRT_INPUT_XBAR1_IN03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN03_OFFSET) +#define IMXRT_INPUT_XBAR1_IN04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN04_OFFSET) +#define IMXRT_INPUT_XBAR1_IN05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) +#define IMXRT_INPUT_XBAR1_IN06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) +#define IMXRT_INPUT_XBAR1_IN07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN07_OFFSET) +#define IMXRT_INPUT_XBAR1_IN08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN08_OFFSET) +#define IMXRT_INPUT_XBAR1_IN09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN09_OFFSET) +#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) +#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) +#define IMXRT_INPUT_XBAR1_IN20 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN20_OFFSET) +#define IMXRT_INPUT_XBAR1_IN22 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN22_OFFSET) +#define IMXRT_INPUT_XBAR1_IN23 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN23_OFFSET) +#define IMXRT_INPUT_XBAR1_IN24 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN24_OFFSET) +#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) +#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) +#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) +#define IMXRT_INPUT_XBAR1_IN25 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN25_OFFSET) +#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) +#define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) + +/* Select1 Input Registers */ + +#define IMXRT_INPUT_ENET2_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPG_CLK_RMII_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_MDIO_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_0_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXDATA_1_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXEN_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_RXERR_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TIMER_0_OFFSET) +#define IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET2_IPP_IND_MAC0_TXCLK_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_DQS_FA_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT0_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT1_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT2_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FA_BIT3_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT0_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT1_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT2_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_IO_FB_BIT3_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FA_OFFSET) +#define IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPI2_IPP_IND_SCK_FB_OFFSET) +#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT1_IPP_IND_CAPIN1_OFFSET) +#define IMXRT_INPUT_GPT1_IPP_IND_CAPIN2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT1_IPP_IND_CAPIN2_OFFSET) +#define IMXRT_INPUT_GPT1_IPP_IND_CLKIN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT1_IPP_IND_CLKIN_OFFSET) +#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT2_IPP_IND_CAPIN1_OFFSET) +#define IMXRT_INPUT_GPT2_IPP_IND_CAPIN2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT2_IPP_IND_CAPIN2_OFFSET) +#define IMXRT_INPUT_GPT2_IPP_IND_CLKIN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_GPT2_IPP_IND_CLKIN_OFFSET) +#define IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPG_CLK_SAI_MCLK_2_OFFSET) +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXBCLK_OFFSET) +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXDATA_0_OFFSET) +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_RXSYNC_OFFSET) +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXBCLK_OFFSET) +#define IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI3_IPP_IND_SAI_TXSYNC_OFFSET) +#define IMXRT_INPUT_SEMC_I_IPP_IND_DQS4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SEMC_I_IPP_IND_DQS4_OFFSET) +#define IMXRT_INPUT_CANFD_IPP_IND_CANRX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CANFD_IPP_IND_CANRX_OFFSET) + +/* Register bit definitions *********************************************************/ + +/* General Purpose Register 0 (GPR0) - Reserved */ + +/* General Purpose Register 1 (GPR1) */ + +#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) +#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) +#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) +#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) +#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) +#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) +#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) +#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) +#define GPR_GPR1_GINT (1 << 12) +#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) +#define GPR_GPR1_ENET2_CLK_SEL (1 << 14) +#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) +#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) +#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) +#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) +#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) +#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) +#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) +#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) +#define GPR_GPR1_EXC_MON_OKAY (0 << 22) +#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) +#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) +#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) + +/* General Purpose Register 2 (GPR2) */ + +#define GPR_GPR2_AXBS_L_AHBXL_HIGH_PRIORITY (1 << 0) +#define GPR_GPR2_AXBS_L_DMA_HIGH_PRIORITY (1 << 1) +#define GPR_GPR2_AXBS_L_FORCE_ROUND_ROBIN (1 << 2) +#define GPR_GPR2_AXBS_P_M0_HIGH_PRIORITY (1 << 3) +#define GPR_GPR2_AXBS_P_M1_HIGH_PRIORITY (1 << 4) +#define GPR_GPR2_AXBS_P_FORCE_ROUND_ROBIN (1 << 5) +#define GPR_GPR2_CANFD_FILTER_BYPASS (1 << 6) +#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) +#define GPR_GPR2_RAM_AUTO_CLK_GATING_EN (1 << 13) +#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) +#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) +#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) +# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) +#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) +#define GPR_GPR2_MQS_EN (1 << 25) +#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) +#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) +#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) +#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) +#define GPR_GPR2_QTIM3_TMR_RESET (1 << 30) +#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) + +/* General Purpose Register 3 (GPR3) */ + +#define GPR_GPR3_OCRAM_CTL_SHIFT (0) +#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) +# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) +#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) +#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) +#define GPR_GPR3_OCRAM2_CTL_SHIFT (8) +#define GPR_GPR3_OCRAM2_CTL_MASK (15 << GPR_GPR3_OCRAM2_CTL_SHIFT) +# define GPR_GPR3_OCRAM2_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM2_CTL_SHIFT) +# define GPR_GPR3_OCRAM2_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM2_CTL_SHIFT) +# define GPR_GPR3_OCRAM2_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM2_CTL_SHIFT) +# define GPR_GPR3_OCRAM2_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM2_CTL_SHIFT) +#define GPR_GPR3_AXBS_L_HALT_REQ (1 << 15) +#define GPR_GPR3_OCRAM_STATUS_SHIFT (16) +#define GPR_GPR3_OCRAM_STATUS_MASK (15 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_STATUS_SHIFT) +# define GPR_GPR3_OCRAM_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_STATUS_SHIFT) +#define GPR_GPR3_OCRAM2_STATUS_SHIFT (24) +#define GPR_GPR3_OCRAM2_STATUS_MASK (15 << GPR_GPR3_OCRAM2_STATUS_SHIFT) +# define GPR_GPR3_OCRAM2_STATUS_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM2_STATUS_SHIFT) +# define GPR_GPR3_OCRAM2_STATUS_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM2_STATUS_SHIFT) +# define GPR_GPR3_OCRAM2_STATUS_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM2_STATUS_SHIFT) +# define GPR_GPR3_OCRAM2_STATUS_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM2_STATUS_SHIFT) +#define GPR_GPR3_AXBS_L_HALTED (1 << 31) + +/* General Purpose Register 4 (GPR4) */ + +#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) +#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) +#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) +#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) +#define GPR_GPR4_ENET_STOP_REQ (1 << 4) +#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) +#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) +#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) +#define GPR_GPR4_ENET2_STOP_REQ (1 << 8) +#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) +#define GPR_GPR4_PIT_STOP_REQ (1 << 10) +#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) +#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) +#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) +#define GPR_GPR4_FLEXIO3_STOP_REQ (1 << 14) +#define GPR_GPR4_FLEXSPI2_STOP_REQ (1 << 15) +#define GPR_GRP4_EDMA_STOP_ACK (1 << 16) +#define GPR_GPR4_CAN1_STOP_ACK (1 << 17) +#define GPR_GPR4_CAN2_STOP_ACK (1 << 18) +#define GPR_GPR4_TRNG_STOP_ACK (1 << 19) +#define GPR_GPR4_ENET_STOP_ACK (1 << 20) +#define GPR_GPR4_SAI1_STOP_ACK (1 << 21) +#define GPR_GPR4_SAI2_STOP_ACK (1 << 22) +#define GPR_GPR4_SAI3_STOP_ACK (1 << 23) +#define GPR_GPR4_ENET2_STOP_ACK (1 << 24) +#define GPR_GPR4_SEMC_STOP_ACK (1 << 25) +#define GPR_GPR4_PIT_STOP_ACK (1 << 26) +#define GPR_GPR4_FLEXSPI_STOP_ACK (1 << 27) +#define GPR_GPR4_FLEXIO1_STOP_ACK (1 << 28) +#define GPR_GPR4_FLEXIO2_STOP_ACK (1 << 29) +#define GPR_GPR4_FLEXIO3_STOP_ACK (1 << 30) +#define GPR_GPR4_FLEXSPI2_STOP_ACK (1 << 31) + +/* General Purpose Register 5 (GPR5) */ + +#define GPR_GPR5_WDOG1_MASK (1 << 6) +#define GPR_GPR5_WDOG2_MASK (1 << 7) +#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) +#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) +#define GPR_GPR5_GPT2_CAPIN2_SEL_PAD (0 << 24) +#define GPR_GPR5_GPT2_CAPIN2_SEL_ENET2 (1 << 24) +#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET (0 << 25) +#define GPR_GPR5_ENET_EVENT3IN_SEL_GPT2CMP1 (1 << 25) +#define GPR_GPR5_ENET2_EVENT3IN_SEL_ENET2 (0 << 26) +#define GPR_GPR5_ENET2_EVENT3IN_SEL_CPT2CMP2 (1 << 26) +#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) +#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) +#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) + +/* General Purpose Register 6 (GPR6) */ + +#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT (0) +#define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT (1) +#define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT (2) +#define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT (3) +#define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER1_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT (4) +#define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT (5) +#define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT (6) +#define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT (7) +#define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER2_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT (8) +#define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT (9) +#define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT (10) +#define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT (11) +#define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER3_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT (12) +#define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM0_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT (13) +#define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM1_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT (14) +#define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM2_INPUT_SEL_SHIFT) +#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT (15) +#define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_MASK (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_IOMUX (0 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) +# define GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_XBAR (1 << GPR_GPR6_QTIMER4_TRM3_INPUT_SEL_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT (16) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_4_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT (17) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_5_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT (18) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_6_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT (19) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_7_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT (20) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_8_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT (21) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_9_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT (22) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_10_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT (23) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_11_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT (24) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_12_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT (25) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_13_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT (26) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_14_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT (27) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_15_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT (28) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_16_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT (29) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_17_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT (30) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_18_SHIFT) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT (31) +#define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_MASK (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_IN (0 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) +# define GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_OUT (1 << GPR_GPR6_IOMUXC_XBAR_DIR_SEL_19_SHIFT) + +/* General Purpose Register 7 (GPR7) */ + +#define GPR_GPR7_LPI2C1_STOP_REQ (1 << 0) +#define GPR_GPR7_LPI2C2_STOP_REQ (1 << 1) +#define GPR_GPR7_LPI2C3_STOP_REQ (1 << 2) +#define GPR_GPR7_LPI2C4_STOP_REQ (1 << 3) +#define GPR_GPR7_LPSPI1_STOP_REQ (1 << 4) +#define GPR_GPR7_LPSPI2_STOP_REQ (1 << 5) +#define GPR_GPR7_LPSPI3_STOP_REQ (1 << 6) +#define GPR_GPR7_LPSPI4_STOP_REQ (1 << 7) +#define GPR_GPR7_LPUART1_STOP_REQ (1 << 8) +#define GPR_GPR7_LPUART2_STOP_REQ (1 << 9) +#define GPR_GPR7_LPUART3_STOP_REQ (1 << 10) +#define GPR_GPR7_LPUART4_STOP_REQ (1 << 11) +#define GPR_GPR7_LPUART5_STOP_REQ (1 << 12) +#define GPR_GPR7_LPUART6_STOP_REQ (1 << 13) +#define GPR_GPR7_LPUART7_STOP_REQ (1 << 14) +#define GPR_GPR7_LPUART8_STOP_REQ (1 << 15) +#define GPR_GPR7_LPI2C1_STOP_ACK (1 << 16) +#define GPR_GPR7_LPI2C2_STOP_ACK (1 << 17) +#define GPR_GPR7_LPI2C3_STOP_ACK (1 << 18) +#define GPR_GPR7_LPI2C4_STOP_ACK (1 << 19) +#define GPR_GPR7_LPSPI1_STOP_ACK (1 << 20) +#define GPR_GPR7_LPSPI2_STOP_ACK (1 << 21) +#define GPR_GPR7_LPSPI3_STOP_ACK (1 << 22) +#define GPR_GPR7_LPSPI4_STOP_ACK (1 << 23) +#define GPR_GPR7_LPUART1_STOP_ACK (1 << 24) +#define GPR_GPR7_LPUART2_STOP_ACK (1 << 25) +#define GPR_GPR7_LPUART3_STOP_ACK (1 << 26) +#define GPR_GPR7_LPUART4_STOP_ACK (1 << 27) +#define GPR_GPR7_LPUART5_STOP_ACK (1 << 28) +#define GPR_GPR7_LPUART6_STOP_ACK (1 << 29) +#define GPR_GPR7_LPUART7_STOP_ACK (1 << 30) +#define GPR_GPR7_LPUART8_STOP_ACK (1 << 31) + +/* General Purpose Register 8 (GPR8) */ + +#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT (0) +#define GPR_GPR8_LPI2C1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT (1) +#define GPR_GPR8_LPI2C1_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C1_IPG_DOZED (1 << GPR_GPR8_LPI2C1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT (2) +#define GPR_GPR8_LPI2C2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT (3) +#define GPR_GPR8_LPI2C2_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C2_IPG_DOZED (1 << GPR_GPR8_LPI2C2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT (4) +#define GPR_GPR8_LPI2C3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT (5) +#define GPR_GPR8_LPI2C3_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C3_IPG_DOZED (1 << GPR_GPR8_LPI2C3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT (6) +#define GPR_GPR8_LPI2C4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPI2C4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT (7) +#define GPR_GPR8_LPI2C4_IPG_DOZE_MASK (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_NOT_DOZED (0 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPI2C4_IPG_DOZED (1 << GPR_GPR8_LPI2C4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT (8) +#define GPR_GPR8_LPSPI1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT (9) +#define GPR_GPR8_LPSPI1_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI1_IPG_DOZED (1 << GPR_GPR8_LPSPI1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT (10) +#define GPR_GPR8_LPSPI2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT (11) +#define GPR_GPR8_LPSPI2_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI2_IPG_DOZED (1 << GPR_GPR8_LPSPI2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT (12) +#define GPR_GPR8_LPSPI3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT (13) +#define GPR_GPR8_LPSPI3_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI3_IPG_DOZED (1 << GPR_GPR8_LPSPI3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT (14) +#define GPR_GPR8_LPSPI4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPSPI4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT (15) +#define GPR_GPR8_LPSPI4_IPG_DOZE_MASK (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_NOT_DOZED (0 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPSPI4_IPG_DOZED (1 << GPR_GPR8_LPSPI4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT (16) +#define GPR_GPR8_LPUART1_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART1_IPG_DOZE_SHIFT (17) +#define GPR_GPR8_LPUART1_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART1_IPG_DOZED (1 << GPR_GPR8_LPUART1_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT (18) +#define GPR_GPR8_LPUART2_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART2_IPG_DOZE_SHIFT (19) +#define GPR_GPR8_LPUART2_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART2_IPG_DOZED (1 << GPR_GPR8_LPUART2_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT (20) +#define GPR_GPR8_LPUART3_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART3_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART3_IPG_DOZE_SHIFT (21) +#define GPR_GPR8_LPUART3_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART3_IPG_DOZED (1 << GPR_GPR8_LPUART3_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT (22) +#define GPR_GPR8_LPUART4_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART4_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART4_IPG_DOZE_SHIFT (23) +#define GPR_GPR8_LPUART4_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART4_IPG_DOZED (1 << GPR_GPR8_LPUART4_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT (24) +#define GPR_GPR8_LPUART5_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART5_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART5_IPG_DOZE_SHIFT (25) +#define GPR_GPR8_LPUART5_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART5_IPG_DOZED (1 << GPR_GPR8_LPUART5_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT (26) +#define GPR_GPR8_LPUART6_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART6_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART6_IPG_DOZE_SHIFT (27) +#define GPR_GPR8_LPUART6_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART6_IPG_DOZED (1 << GPR_GPR8_LPUART6_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT (28) +#define GPR_GPR8_LPUART7_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART7_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART7_IPG_DOZE_SHIFT (29) +#define GPR_GPR8_LPUART7_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART7_IPG_DOZED (1 << GPR_GPR8_LPUART7_IPG_DOZE_SHIFT) +#define GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT (30) +#define GPR_GPR8_LPUART8_IPG_STOP_MODE_MASK (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_ON_IN_STOP (0 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_OFF_IN_STOP (1 << GPR_GPR8_LPUART8_IPG_STOP_MODE_SHIFT) +#define GPR_GPR8_LPUART8_IPG_DOZE_SHIFT (31) +#define GPR_GPR8_LPUART8_IPG_DOZE_MASK (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_NOT_DOZED (0 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) +# define GPR_GPR8_LPUART8_IPG_DOZED (1 << GPR_GPR8_LPUART8_IPG_DOZE_SHIFT) + +/* General Purpose Register 9 (GPR9) - Reserved */ + +/* General Purpose Register 10 (GPR10) */ + +#define GPR_GPR10_NIDEN (1 << 0) +#define GPR_GPR10_DBG_EN (1 << 1) +#define GPR_GPR10_SEC_ERR_RESP (1 << 2) +#define GPR_GPR10_DCPKEY_OCOTP_OR_KEYMUX (1 << 4) +#define GPR_GPR10_OCRAM_TZ_EN (1 << 8) +#define GPR_GPR10_OCRAM_TZ_ADDR_SHIFT (9) +#define GPR_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) +# define GPR_GPR10_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_OCRAM_TZ_ADDR_SHIFT) +#define GPR_GPR10_LOCK_NIDEN (1 << 16) +#define GPR_GPR10_LOCK_DBG_EN (1 << 17) +#define GPR_GPR10_LOCK_SEC_ERR_RESP (1 << 18) +#define GPR_GPR10_LOCK_DCPKEY_OCOTP_OR_KEYMUX (1 << 20) +#define GPR_GPR10_LOCK_OCRAM_TZ_EN (1 << 24) +#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT (25) +#define GPR_GPR10_LOCK_OCRAM_TZ_ADDR_MASK (0x3f << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) +# define GPR_GPR10_LOCK_OCRAM_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR10_LOCK_OCRAM_TZ_ADDR_SHIFT) + +/* General Purpose Register 11 (GPR11) */ + +#define GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS (0) +#define GPR_GPR11_M7_APC_AC_R0_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R0_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R0_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS (2) +#define GPR_GPR11_M7_APC_AC_R1_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R1_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R1_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS (4) +#define GPR_GPR11_M7_APC_AC_R2_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R2_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R2_CTRL_SHIFTS) +#define GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS (6) +#define GPR_GPR11_M7_APC_AC_R3_CTRL_MASK (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_ACCESS (0 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG (1 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_FLEXSPI (2 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +# define GPR_GPR11_M7_APC_AC_R3_CTRL_NO_DEBUG_FLEXSPI (3 << GPR_GPR11_M7_APC_AC_R3_CTRL_SHIFTS) +#define GPR_GPR11_BEE_DE_RX_EN_SHIFTS (8) +#define GPR_GPR11_BEE_DE_RX_EN_MASK (0xf << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_RX_EN(n) ((uint32_t)(n) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R0_EN (1) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R1_EN (2) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R2_EN (4) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) +# define GPR_GPR11_BEE_DE_R3_EN (8) << GPR_GPR11_BEE_DE_RX_EN_SHIFTS) + +/* General Purpose Register 12 (GPR12) */ + +#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT (0) +#define GPR_GPR12_FLEXIO1_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO1_IPG_STOP_MODE_SHIFT) +#define GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT (1) +#define GPR_GPR12_FLEXIO1_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO1_IPG_DOZED (1 << GPR_GPR12_FLEXIO1_IPG_DOZE_SHIFT) +#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT (2) +#define GPR_GPR12_FLEXIO2_IPG_STOP_MODE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_ON_IN_STOP (0 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_OFF_IN_STOP (1 << GPR_GPR12_FLEXIO2_IPG_STOP_MODE_SHIFT) +#define GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT (3) +#define GPR_GPR12_FLEXIO2_IPG_DOZE_MASK (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_NOT_DOZED (0 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) +# define GPR_GPR12_FLEXIO2_IPG_DOZED (1 << GPR_GPR12_FLEXIO2_IPG_DOZE_SHIFT) +#define GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT (4) +#define GPR_GPR12_ACMP_IPG_STOP_MODE_MASK (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_ACMP_IPG_ON_IN_STOP (0 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) +# define GPR_GPR12_ACMP_IPG_OFF_IN_STOP (1 << GPR_GPR12_ACMP_IPG_STOP_MODE_SHIFT) + +/* General Purpose Register 13 (GPR13) */ + +#define GPR_GPR13_ARCACHE_USDHC_CACHEABLE (1 << 0) +#define GPR_GPR13_AWCACHE_USDHC_CACHEABLE (1 << 1) +#define GPR_GPR13_CANFD_STOP_REQ (1 << 4) +#define GPR_GPR13_CACHE_ENET_CACHEABLE (1 << 7) +#define GPR_GPR13_CACHE_USB_CACHEABLE (1 << 13) +#define GPR_GPR13_CANFD_STOP_ACK (1 << 20) + +/* General Purpose Register 14 (GPR14) */ + +#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_DN (1 << 0) +#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_DN (1 << 1) +#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_DN (1 << 2) +#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_DN (1 << 3) +#define GPR_GPR14_ACMP1_CMP_IGEN_TRIM_UP (1 << 4) +#define GPR_GPR14_ACMP2_CMP_IGEN_TRIM_UP (1 << 5) +#define GPR_GPR14_ACMP3_CMP_IGEN_TRIM_UP (1 << 6) +#define GPR_GPR14_ACMP4_CMP_IGEN_TRIM_UP (1 << 7) +#define GPR_GPR14_ACMP1_SAMPLE_SYNC_EN (1 << 8) +#define GPR_GPR14_ACMP2_SAMPLE_SYNC_EN (1 << 9) +#define GPR_GPR14_ACMP3_SAMPLE_SYNC_EN (1 << 10) +#define GPR_GPR14_ACMP4_SAMPLE_SYNC_EN (1 << 11) +#define GPR_GPR14_CM7_CFGITCMSZ_SHIFT (16) +#define GPR_GPR14_CM7_CFGITCMSZ_MASK (0x4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_0KB (0 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_4KB (3 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_8KB (4 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_16KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_32KB (6 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_64KB (7 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_128KB (8 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_256KB (9 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGITCMSZ_512KB (10 << GPR_GPR14_CM7_CFGITCMSZ_SHIFT) +#define GPR_GPR14_CM7_CFGDTCMSZ_SHIFT (20) +#define GPR_GPR14_CM7_CFGDTCMSZ_MASK (0xf << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_0KB (0 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_4KB (3 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_8KB (4 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_16KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_32KB (6 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_64KB (7 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_128KB (8 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_256KB (9 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) +# define GPR_GPR14_CM7_CFGDTCMSZ_512KB (10 << GPR_GPR14_CM7_CFGDTCMSZ_SHIFT) + +/* General Purpose Register 15 (GPR16) - Reserved */ + +/* General Purpose Register 16 (GPR16) */ + +#define GPR_GPR16_INIT_ITCM_EN (1 << 0) +#define GPR_GPR16_INIT_DTCM_EN (1 << 1) +#define GPR_GPR16_FLEXRAM_BANK_CFG_SELF (1 << 2) +#define GPR_GPR16_CM7_INIT_VTOR_SHIFT (7) +#define GPR_GPR16_CM7_INIT_VTOR_MASK (0xffffff1 << GPR_GPR16_CM7_INIT_VTOR_SHIFT) +#define GPR_GPR16_CM7_INIT_VTOR(n) (((uint32_t)(n) & 0x1ffffff)) << GPR_GPR16_CM7_INIT_VTOR_SHIFT) + +/* General Purpose Register 17 (GPR17) */ + +#define GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT (0) +#define GPR_GPR17_FLEXRAM_BANK_CFG_MASK (0xffffffff << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK_CFG(n) ((uint32_t)(n)) << GPR_GPR17_FLEXRAM_BANK_CFG_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK0_SHIFT (0) +#define GPR_GPR17_FLEXRAM_BANK0_MASK (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_DTCM (2 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK0_ITCM (3 << GPR_GPR17_FLEXRAM_BANK0_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK1_SHIFT (2) +#define GPR_GPR17_FLEXRAM_BANK1_MASK (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_DTCM (2 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK1_ITCM (3 << GPR_GPR17_FLEXRAM_BANK1_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK2_SHIFT (4) +#define GPR_GPR17_FLEXRAM_BANK2_MASK (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_DTCM (2 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK2_ITCM (3 << GPR_GPR17_FLEXRAM_BANK2_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK3_SHIFT (6) +#define GPR_GPR17_FLEXRAM_BANK3_MASK (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_DTCM (2 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK3_ITCM (3 << GPR_GPR17_FLEXRAM_BANK3_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK4_SHIFT (8) +#define GPR_GPR17_FLEXRAM_BANK4_MASK (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_DTCM (2 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK4_ITCM (3 << GPR_GPR17_FLEXRAM_BANK4_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK5_SHIFT (10) +#define GPR_GPR17_FLEXRAM_BANK5_MASK (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_DTCM (2 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK5_ITCM (3 << GPR_GPR17_FLEXRAM_BANK5_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK6_SHIFT (12) +#define GPR_GPR17_FLEXRAM_BANK6_MASK (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_DTCM (2 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK6_ITCM (3 << GPR_GPR17_FLEXRAM_BANK6_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK7_SHIFT (14) +#define GPR_GPR17_FLEXRAM_BANK7_MASK (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_DTCM (2 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK7_ITCM (3 << GPR_GPR17_FLEXRAM_BANK7_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK8_SHIFT (16) +#define GPR_GPR17_FLEXRAM_BANK8_MASK (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_DTCM (2 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK8_ITCM (3 << GPR_GPR17_FLEXRAM_BANK8_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK9_SHIFT (18) +#define GPR_GPR17_FLEXRAM_BANK9_MASK (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_DTCM (2 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK9_ITCM (3 << GPR_GPR17_FLEXRAM_BANK9_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK10_SHIFT (20) +#define GPR_GPR17_FLEXRAM_BANK10_MASK (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_DTCM (2 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK10_ITCM (3 << GPR_GPR17_FLEXRAM_BANK10_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK11_SHIFT (22) +#define GPR_GPR17_FLEXRAM_BANK11_MASK (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_DTCM (2 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK11_ITCM (3 << GPR_GPR17_FLEXRAM_BANK11_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK12_SHIFT (24) +#define GPR_GPR17_FLEXRAM_BANK12_MASK (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_DTCM (2 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK12_ITCM (3 << GPR_GPR17_FLEXRAM_BANK12_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK13_SHIFT (26) +#define GPR_GPR17_FLEXRAM_BANK13_MASK (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_DTCM (2 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK13_ITCM (3 << GPR_GPR17_FLEXRAM_BANK13_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK14_SHIFT (28) +#define GPR_GPR17_FLEXRAM_BANK14_MASK (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_DTCM (2 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK14_ITCM (3 << GPR_GPR17_FLEXRAM_BANK14_SHIFT) +#define GPR_GPR17_FLEXRAM_BANK15_SHIFT (30) +#define GPR_GPR17_FLEXRAM_BANK15_MASK (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_NOTUSED (0 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_OCRAM (1 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_DTCM (2 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) +# define GPR_GPR17_FLEXRAM_BANK15_ITCM (3 << GPR_GPR17_FLEXRAM_BANK15_SHIFT) + +/* General Purpose Register 18 (GPR18) */ + +#define GPR_GPR18_LOCK_M7_APC_AC_R0_BOT (1 << 0) +#define GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT (3) +#define GPR_GPR18_M7_APC_AC_R0_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) +#define GPR_GPR18_M7_APC_AC_R0_BOT(n) ((uint32_t)(n)) << GPR_GPR18_M7_APC_AC_R0_BOT_SHIFT) + +/* General Purpose Register 19 (GPR19) */ + +#define GPR_GPR19_LOCK_M7_APC_AC_R0_TOP (1 << 0) +#define GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT (3) +#define GPR_GPR19_M7_APC_AC_R0_TOP_MASK (0x1fffffff << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) +#define GPR_GPR19_M7_APC_AC_R0_TOP(n) ((uint32_t)(n)) << GPR_GPR19_M7_APC_AC_R0_TOP_SHIFT) + +/* General Purpose Register 20 (GPR20) */ + +#define GPR_GPR20_LOCK_M7_APC_AC_R1_BOT (1 << 0) +#define GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT (3) +#define GPR_GPR20_M7_APC_AC_R1_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R1_BOT_SHIFT) +#define GPR_GPR20_M7_APC_AC_R1_BOT(n) ((uint32_t)(n)) << GPR_GPR20_M7_APC_AC_R1_BOT_SHIFT) + +/* General Purpose Register 21 (GPR21) */ + +#define GPR_GPR21_LOCK_M7_APC_AC_R1_TOP (1 << 0) +#define GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT (3) +#define GPR_GPR21_M7_APC_AC_R1_TOP_MASK (0x1fffffff << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) +#define GPR_GPR21_M7_APC_AC_R1_TOP(n) ((uint32_t)(n)) << GPR_GPR21_M7_APC_AC_R1_TOP_SHIFT) + +/* General Purpose Register 22 (GPR22) */ + +#define GPR_GPR22_LOCK_M7_APC_AC_R2_BOT (1 << 0) +#define GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT (3) +#define GPR_GPR22_M7_APC_AC_R2_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R2_BOT_SHIFT) +#define GPR_GPR22_M7_APC_AC_R2_BOT(n) ((uint32_t)(n)) << GPR_GPR22_M7_APC_AC_R2_BOT_SHIFT) + +/* General Purpose Register 23 (GPR23) */ + +#define GPR_GPR23_LOCK_M7_APC_AC_R2_TOP (1 << 0) +#define GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT (3) +#define GPR_GPR23_M7_APC_AC_R2_TOP_MASK (0x1fffffff << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) +#define GPR_GPR23_M7_APC_AC_R2_TOP(n) ((uint32_t)(n)) << GPR_GPR23_M7_APC_AC_R2_TOP_SHIFT) + +/* General Purpose Register 24 (GPR24) */ + +#define GPR_GPR24_LOCK_M7_APC_AC_R3_BOT (1 << 0) +#define GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT (3) +#define GPR_GPR24_M7_APC_AC_R3_BOT_MASK (0x1fffffff << GPR_GPR18_M7_APC_AC_R3_BOT_SHIFT) +#define GPR_GPR24_M7_APC_AC_R3_BOT(n) ((uint32_t)(n)) << GPR_GPR24_M7_APC_AC_R3_BOT_SHIFT) + +/* General Purpose Register 25 (GPR25) */ + +#define GPR_GPR25_LOCK_M7_APC_AC_R3_TOP (1 << 0) +#define GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT (3) +#define GPR_GPR25_M7_APC_AC_R3_TOP_MASK (0x1fffffff << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) +#define GPR_GPR25_M7_APC_AC_R3_TOP(n) ((uint32_t)(n)) << GPR_GPR25_M7_APC_AC_R3_TOP_SHIFT) + +/* General Purpose Register 26 (GPR26) */ + +#define GPR_GPR26_GPIO_MUX1_GPIO0_SEL_GPIO1 (0 << 0) +#define GPR_GPR26_GPIO_MUX1_GPIO0_SEL_GPIO6 (1 << 0) +#define GPR_GPR26_GPIO_MUX1_GPIO1_SEL_GPIO1 (0 << 1) +#define GPR_GPR26_GPIO_MUX1_GPIO1_SEL_GPIO6 (1 << 1) +#define GPR_GPR26_GPIO_MUX1_GPIO2_SEL_GPIO1 (0 << 2) +#define GPR_GPR26_GPIO_MUX1_GPIO2_SEL_GPIO6 (1 << 2) +#define GPR_GPR26_GPIO_MUX1_GPIO3_SEL_GPIO1 (0 << 3) +#define GPR_GPR26_GPIO_MUX1_GPIO3_SEL_GPIO6 (1 << 3) +#define GPR_GPR26_GPIO_MUX1_GPIO4_SEL_GPIO1 (0 << 4) +#define GPR_GPR26_GPIO_MUX1_GPIO4_SEL_GPIO6 (1 << 4) +#define GPR_GPR26_GPIO_MUX1_GPIO5_SEL_GPIO1 (0 << 5) +#define GPR_GPR26_GPIO_MUX1_GPIO5_SEL_GPIO6 (1 << 5) +#define GPR_GPR26_GPIO_MUX1_GPIO6_SEL_GPIO1 (0 << 6) +#define GPR_GPR26_GPIO_MUX1_GPIO6_SEL_GPIO6 (1 << 6) +#define GPR_GPR26_GPIO_MUX1_GPIO7_SEL_GPIO1 (0 << 7) +#define GPR_GPR26_GPIO_MUX1_GPIO7_SEL_GPIO6 (1 << 7) +#define GPR_GPR26_GPIO_MUX1_GPIO8_SEL_GPIO1 (0 << 8) +#define GPR_GPR26_GPIO_MUX1_GPIO8_SEL_GPIO6 (1 << 8) +#define GPR_GPR26_GPIO_MUX1_GPIO9_SEL_GPIO1 (0 << 9) +#define GPR_GPR26_GPIO_MUX1_GPIO9_SEL_GPIO6 (1 << 9) +#define GPR_GPR26_GPIO_MUX1_GPIO10_SEL_GPIO1 (0 << 10) +#define GPR_GPR26_GPIO_MUX1_GPIO10_SEL_GPIO6 (1 << 10) +#define GPR_GPR26_GPIO_MUX1_GPIO11_SEL_GPIO1 (0 << 11) +#define GPR_GPR26_GPIO_MUX1_GPIO11_SEL_GPIO6 (1 << 11) +#define GPR_GPR26_GPIO_MUX1_GPIO12_SEL_GPIO1 (0 << 12) +#define GPR_GPR26_GPIO_MUX1_GPIO12_SEL_GPIO6 (1 << 12) +#define GPR_GPR26_GPIO_MUX1_GPIO13_SEL_GPIO1 (0 << 13) +#define GPR_GPR26_GPIO_MUX1_GPIO13_SEL_GPIO6 (1 << 13) +#define GPR_GPR26_GPIO_MUX1_GPIO14_SEL_GPIO1 (0 << 14) +#define GPR_GPR26_GPIO_MUX1_GPIO14_SEL_GPIO6 (1 << 14) +#define GPR_GPR26_GPIO_MUX1_GPIO15_SEL_GPIO1 (0 << 15) +#define GPR_GPR26_GPIO_MUX1_GPIO15_SEL_GPIO6 (1 << 15) +#define GPR_GPR26_GPIO_MUX1_GPIO16_SEL_GPIO1 (0 << 16) +#define GPR_GPR26_GPIO_MUX1_GPIO16_SEL_GPIO6 (1 << 16) +#define GPR_GPR26_GPIO_MUX1_GPIO17_SEL_GPIO1 (0 << 17) +#define GPR_GPR26_GPIO_MUX1_GPIO17_SEL_GPIO6 (1 << 17) +#define GPR_GPR26_GPIO_MUX1_GPIO18_SEL_GPIO1 (0 << 18) +#define GPR_GPR26_GPIO_MUX1_GPIO18_SEL_GPIO6 (1 << 18) +#define GPR_GPR26_GPIO_MUX1_GPIO19_SEL_GPIO1 (0 << 19) +#define GPR_GPR26_GPIO_MUX1_GPIO19_SEL_GPIO6 (1 << 19) +#define GPR_GPR26_GPIO_MUX1_GPIO20_SEL_GPIO1 (0 << 20) +#define GPR_GPR26_GPIO_MUX1_GPIO20_SEL_GPIO6 (1 << 20) +#define GPR_GPR26_GPIO_MUX1_GPIO21_SEL_GPIO1 (0 << 21) +#define GPR_GPR26_GPIO_MUX1_GPIO21_SEL_GPIO6 (1 << 21) +#define GPR_GPR26_GPIO_MUX1_GPIO22_SEL_GPIO1 (0 << 22) +#define GPR_GPR26_GPIO_MUX1_GPIO22_SEL_GPIO6 (1 << 22) +#define GPR_GPR26_GPIO_MUX1_GPIO23_SEL_GPIO1 (0 << 23) +#define GPR_GPR26_GPIO_MUX1_GPIO23_SEL_GPIO6 (1 << 23) +#define GPR_GPR26_GPIO_MUX1_GPIO24_SEL_GPIO1 (0 << 24) +#define GPR_GPR26_GPIO_MUX1_GPIO24_SEL_GPIO6 (1 << 24) +#define GPR_GPR26_GPIO_MUX1_GPIO25_SEL_GPIO1 (0 << 25) +#define GPR_GPR26_GPIO_MUX1_GPIO25_SEL_GPIO6 (1 << 25) +#define GPR_GPR26_GPIO_MUX1_GPIO26_SEL_GPIO1 (0 << 26) +#define GPR_GPR26_GPIO_MUX1_GPIO26_SEL_GPIO6 (1 << 26) +#define GPR_GPR26_GPIO_MUX1_GPIO27_SEL_GPIO1 (0 << 27) +#define GPR_GPR26_GPIO_MUX1_GPIO27_SEL_GPIO6 (1 << 27) +#define GPR_GPR26_GPIO_MUX1_GPIO28_SEL_GPIO1 (0 << 28) +#define GPR_GPR26_GPIO_MUX1_GPIO28_SEL_GPIO6 (1 << 28) +#define GPR_GPR26_GPIO_MUX1_GPIO29_SEL_GPIO1 (0 << 29) +#define GPR_GPR26_GPIO_MUX1_GPIO29_SEL_GPIO6 (1 << 29) +#define GPR_GPR26_GPIO_MUX1_GPIO30_SEL_GPIO1 (0 << 30) +#define GPR_GPR26_GPIO_MUX1_GPIO30_SEL_GPIO6 (1 << 30) +#define GPR_GPR26_GPIO_MUX1_GPIO31_SEL_GPIO1 (0 << 31) +#define GPR_GPR26_GPIO_MUX1_GPIO31_SEL_GPIO6 (1 << 31) + +/* General Purpose Register 27 (GPR27) */ + +#define GPR_GPR27_GPIO_MUX2_GPIO0_SEL_GPIO2 (0 << 0) +#define GPR_GPR27_GPIO_MUX2_GPIO0_SEL_GPIO7 (1 << 0) +#define GPR_GPR27_GPIO_MUX2_GPIO1_SEL_GPIO2 (0 << 1) +#define GPR_GPR27_GPIO_MUX2_GPIO1_SEL_GPIO7 (1 << 1) +#define GPR_GPR27_GPIO_MUX2_GPIO2_SEL_GPIO2 (0 << 2) +#define GPR_GPR27_GPIO_MUX2_GPIO2_SEL_GPIO7 (1 << 2) +#define GPR_GPR27_GPIO_MUX2_GPIO3_SEL_GPIO2 (0 << 3) +#define GPR_GPR27_GPIO_MUX2_GPIO3_SEL_GPIO7 (1 << 3) +#define GPR_GPR27_GPIO_MUX2_GPIO4_SEL_GPIO2 (0 << 4) +#define GPR_GPR27_GPIO_MUX2_GPIO4_SEL_GPIO7 (1 << 4) +#define GPR_GPR27_GPIO_MUX2_GPIO5_SEL_GPIO2 (0 << 5) +#define GPR_GPR27_GPIO_MUX2_GPIO5_SEL_GPIO7 (1 << 5) +#define GPR_GPR27_GPIO_MUX2_GPIO6_SEL_GPIO2 (0 << 6) +#define GPR_GPR27_GPIO_MUX2_GPIO6_SEL_GPIO7 (1 << 6) +#define GPR_GPR27_GPIO_MUX2_GPIO7_SEL_GPIO2 (0 << 7) +#define GPR_GPR27_GPIO_MUX2_GPIO7_SEL_GPIO7 (1 << 7) +#define GPR_GPR27_GPIO_MUX2_GPIO8_SEL_GPIO2 (0 << 8) +#define GPR_GPR27_GPIO_MUX2_GPIO8_SEL_GPIO7 (1 << 8) +#define GPR_GPR27_GPIO_MUX2_GPIO9_SEL_GPIO2 (0 << 9) +#define GPR_GPR27_GPIO_MUX2_GPIO9_SEL_GPIO7 (1 << 9) +#define GPR_GPR27_GPIO_MUX2_GPIO10_SEL_GPIO2 (0 << 10) +#define GPR_GPR27_GPIO_MUX2_GPIO10_SEL_GPIO7 (1 << 10) +#define GPR_GPR27_GPIO_MUX2_GPIO11_SEL_GPIO2 (0 << 11) +#define GPR_GPR27_GPIO_MUX2_GPIO11_SEL_GPIO7 (1 << 11) +#define GPR_GPR27_GPIO_MUX2_GPIO12_SEL_GPIO2 (0 << 12) +#define GPR_GPR27_GPIO_MUX2_GPIO12_SEL_GPIO7 (1 << 12) +#define GPR_GPR27_GPIO_MUX2_GPIO13_SEL_GPIO2 (0 << 13) +#define GPR_GPR27_GPIO_MUX2_GPIO13_SEL_GPIO7 (1 << 13) +#define GPR_GPR27_GPIO_MUX2_GPIO14_SEL_GPIO2 (0 << 14) +#define GPR_GPR27_GPIO_MUX2_GPIO14_SEL_GPIO7 (1 << 14) +#define GPR_GPR27_GPIO_MUX2_GPIO15_SEL_GPIO2 (0 << 15) +#define GPR_GPR27_GPIO_MUX2_GPIO15_SEL_GPIO7 (1 << 15) +#define GPR_GPR27_GPIO_MUX2_GPIO16_SEL_GPIO2 (0 << 16) +#define GPR_GPR27_GPIO_MUX2_GPIO16_SEL_GPIO7 (1 << 16) +#define GPR_GPR27_GPIO_MUX2_GPIO17_SEL_GPIO2 (0 << 17) +#define GPR_GPR27_GPIO_MUX2_GPIO17_SEL_GPIO7 (1 << 17) +#define GPR_GPR27_GPIO_MUX2_GPIO18_SEL_GPIO2 (0 << 18) +#define GPR_GPR27_GPIO_MUX2_GPIO18_SEL_GPIO7 (1 << 18) +#define GPR_GPR27_GPIO_MUX2_GPIO19_SEL_GPIO2 (0 << 19) +#define GPR_GPR27_GPIO_MUX2_GPIO19_SEL_GPIO7 (1 << 19) +#define GPR_GPR27_GPIO_MUX2_GPIO20_SEL_GPIO2 (0 << 20) +#define GPR_GPR27_GPIO_MUX2_GPIO20_SEL_GPIO7 (1 << 20) +#define GPR_GPR27_GPIO_MUX2_GPIO21_SEL_GPIO2 (0 << 21) +#define GPR_GPR27_GPIO_MUX2_GPIO21_SEL_GPIO7 (1 << 21) +#define GPR_GPR27_GPIO_MUX2_GPIO22_SEL_GPIO2 (0 << 22) +#define GPR_GPR27_GPIO_MUX2_GPIO22_SEL_GPIO7 (1 << 22) +#define GPR_GPR27_GPIO_MUX2_GPIO23_SEL_GPIO2 (0 << 23) +#define GPR_GPR27_GPIO_MUX2_GPIO23_SEL_GPIO7 (1 << 23) +#define GPR_GPR27_GPIO_MUX2_GPIO24_SEL_GPIO2 (0 << 24) +#define GPR_GPR27_GPIO_MUX2_GPIO24_SEL_GPIO7 (1 << 24) +#define GPR_GPR27_GPIO_MUX2_GPIO25_SEL_GPIO2 (0 << 25) +#define GPR_GPR27_GPIO_MUX2_GPIO25_SEL_GPIO7 (1 << 25) +#define GPR_GPR27_GPIO_MUX2_GPIO26_SEL_GPIO2 (0 << 26) +#define GPR_GPR27_GPIO_MUX2_GPIO26_SEL_GPIO7 (1 << 26) +#define GPR_GPR27_GPIO_MUX2_GPIO27_SEL_GPIO2 (0 << 27) +#define GPR_GPR27_GPIO_MUX2_GPIO27_SEL_GPIO7 (1 << 27) +#define GPR_GPR27_GPIO_MUX2_GPIO28_SEL_GPIO2 (0 << 28) +#define GPR_GPR27_GPIO_MUX2_GPIO28_SEL_GPIO7 (1 << 28) +#define GPR_GPR27_GPIO_MUX2_GPIO29_SEL_GPIO2 (0 << 29) +#define GPR_GPR27_GPIO_MUX2_GPIO29_SEL_GPIO7 (1 << 29) +#define GPR_GPR27_GPIO_MUX2_GPIO30_SEL_GPIO2 (0 << 30) +#define GPR_GPR27_GPIO_MUX2_GPIO30_SEL_GPIO7 (1 << 30) +#define GPR_GPR27_GPIO_MUX2_GPIO31_SEL_GPIO2 (0 << 31) +#define GPR_GPR27_GPIO_MUX2_GPIO31_SEL_GPIO7 (1 << 31) + +/* General Purpose Register 28 (GPR28) */ + +#define GPR_GPR28_GPIO_MUX3_GPIO0_SEL_GPIO3 (0 << 0) +#define GPR_GPR28_GPIO_MUX3_GPIO0_SEL_GPIO8 (1 << 0) +#define GPR_GPR28_GPIO_MUX3_GPIO1_SEL_GPIO3 (0 << 1) +#define GPR_GPR28_GPIO_MUX3_GPIO1_SEL_GPIO8 (1 << 1) +#define GPR_GPR28_GPIO_MUX3_GPIO2_SEL_GPIO3 (0 << 2) +#define GPR_GPR28_GPIO_MUX3_GPIO2_SEL_GPIO8 (1 << 2) +#define GPR_GPR28_GPIO_MUX3_GPIO3_SEL_GPIO3 (0 << 3) +#define GPR_GPR28_GPIO_MUX3_GPIO3_SEL_GPIO8 (1 << 3) +#define GPR_GPR28_GPIO_MUX3_GPIO4_SEL_GPIO3 (0 << 4) +#define GPR_GPR28_GPIO_MUX3_GPIO4_SEL_GPIO8 (1 << 4) +#define GPR_GPR28_GPIO_MUX3_GPIO5_SEL_GPIO3 (0 << 5) +#define GPR_GPR28_GPIO_MUX3_GPIO5_SEL_GPIO8 (1 << 5) +#define GPR_GPR28_GPIO_MUX3_GPIO6_SEL_GPIO3 (0 << 6) +#define GPR_GPR28_GPIO_MUX3_GPIO6_SEL_GPIO8 (1 << 6) +#define GPR_GPR28_GPIO_MUX3_GPIO7_SEL_GPIO3 (0 << 7) +#define GPR_GPR28_GPIO_MUX3_GPIO7_SEL_GPIO8 (1 << 7) +#define GPR_GPR28_GPIO_MUX3_GPIO8_SEL_GPIO3 (0 << 8) +#define GPR_GPR28_GPIO_MUX3_GPIO8_SEL_GPIO8 (1 << 8) +#define GPR_GPR28_GPIO_MUX3_GPIO9_SEL_GPIO3 (0 << 9) +#define GPR_GPR28_GPIO_MUX3_GPIO9_SEL_GPIO8 (1 << 9) +#define GPR_GPR28_GPIO_MUX3_GPIO10_SEL_GPIO3 (0 << 10) +#define GPR_GPR28_GPIO_MUX3_GPIO10_SEL_GPIO8 (1 << 10) +#define GPR_GPR28_GPIO_MUX3_GPIO11_SEL_GPIO3 (0 << 11) +#define GPR_GPR28_GPIO_MUX3_GPIO11_SEL_GPIO8 (1 << 11) +#define GPR_GPR28_GPIO_MUX3_GPIO12_SEL_GPIO3 (0 << 12) +#define GPR_GPR28_GPIO_MUX3_GPIO12_SEL_GPIO8 (1 << 12) +#define GPR_GPR28_GPIO_MUX3_GPIO13_SEL_GPIO3 (0 << 13) +#define GPR_GPR28_GPIO_MUX3_GPIO13_SEL_GPIO8 (1 << 13) +#define GPR_GPR28_GPIO_MUX3_GPIO14_SEL_GPIO3 (0 << 14) +#define GPR_GPR28_GPIO_MUX3_GPIO14_SEL_GPIO8 (1 << 14) +#define GPR_GPR28_GPIO_MUX3_GPIO15_SEL_GPIO3 (0 << 15) +#define GPR_GPR28_GPIO_MUX3_GPIO15_SEL_GPIO8 (1 << 15) +#define GPR_GPR28_GPIO_MUX3_GPIO16_SEL_GPIO3 (0 << 16) +#define GPR_GPR28_GPIO_MUX3_GPIO16_SEL_GPIO8 (1 << 16) +#define GPR_GPR28_GPIO_MUX3_GPIO17_SEL_GPIO3 (0 << 17) +#define GPR_GPR28_GPIO_MUX3_GPIO17_SEL_GPIO8 (1 << 17) +#define GPR_GPR28_GPIO_MUX3_GPIO18_SEL_GPIO3 (0 << 18) +#define GPR_GPR28_GPIO_MUX3_GPIO18_SEL_GPIO8 (1 << 18) +#define GPR_GPR28_GPIO_MUX3_GPIO19_SEL_GPIO3 (0 << 19) +#define GPR_GPR28_GPIO_MUX3_GPIO19_SEL_GPIO8 (1 << 19) +#define GPR_GPR28_GPIO_MUX3_GPIO20_SEL_GPIO3 (0 << 20) +#define GPR_GPR28_GPIO_MUX3_GPIO20_SEL_GPIO8 (1 << 20) +#define GPR_GPR28_GPIO_MUX3_GPIO21_SEL_GPIO3 (0 << 21) +#define GPR_GPR28_GPIO_MUX3_GPIO21_SEL_GPIO8 (1 << 21) +#define GPR_GPR28_GPIO_MUX3_GPIO22_SEL_GPIO3 (0 << 22) +#define GPR_GPR28_GPIO_MUX3_GPIO22_SEL_GPIO8 (1 << 22) +#define GPR_GPR28_GPIO_MUX3_GPIO23_SEL_GPIO3 (0 << 23) +#define GPR_GPR28_GPIO_MUX3_GPIO23_SEL_GPIO8 (1 << 23) +#define GPR_GPR28_GPIO_MUX3_GPIO24_SEL_GPIO3 (0 << 24) +#define GPR_GPR28_GPIO_MUX3_GPIO24_SEL_GPIO8 (1 << 24) +#define GPR_GPR28_GPIO_MUX3_GPIO25_SEL_GPIO3 (0 << 25) +#define GPR_GPR28_GPIO_MUX3_GPIO25_SEL_GPIO8 (1 << 25) +#define GPR_GPR28_GPIO_MUX3_GPIO26_SEL_GPIO3 (0 << 26) +#define GPR_GPR28_GPIO_MUX3_GPIO26_SEL_GPIO8 (1 << 26) +#define GPR_GPR28_GPIO_MUX3_GPIO27_SEL_GPIO3 (0 << 27) +#define GPR_GPR28_GPIO_MUX3_GPIO27_SEL_GPIO8 (1 << 27) +#define GPR_GPR28_GPIO_MUX3_GPIO28_SEL_GPIO3 (0 << 28) +#define GPR_GPR28_GPIO_MUX3_GPIO28_SEL_GPIO8 (1 << 28) +#define GPR_GPR28_GPIO_MUX3_GPIO29_SEL_GPIO3 (0 << 29) +#define GPR_GPR28_GPIO_MUX3_GPIO29_SEL_GPIO8 (1 << 29) +#define GPR_GPR28_GPIO_MUX3_GPIO30_SEL_GPIO3 (0 << 30) +#define GPR_GPR28_GPIO_MUX3_GPIO30_SEL_GPIO8 (1 << 30) +#define GPR_GPR28_GPIO_MUX3_GPIO31_SEL_GPIO3 (0 << 31) +#define GPR_GPR28_GPIO_MUX3_GPIO31_SEL_GPIO8 (1 << 31) + +/* General Purpose Register 29 (GPR29) */ + +#define GPR_GPR29_GPIO_MUX4_GPIO0_SEL_GPIO4 (0 << 0) +#define GPR_GPR29_GPIO_MUX4_GPIO0_SEL_GPIO9 (1 << 0) +#define GPR_GPR29_GPIO_MUX4_GPIO1_SEL_GPIO4 (0 << 1) +#define GPR_GPR29_GPIO_MUX4_GPIO1_SEL_GPIO9 (1 << 1) +#define GPR_GPR29_GPIO_MUX4_GPIO2_SEL_GPIO4 (0 << 2) +#define GPR_GPR29_GPIO_MUX4_GPIO2_SEL_GPIO9 (1 << 2) +#define GPR_GPR29_GPIO_MUX4_GPIO3_SEL_GPIO4 (0 << 3) +#define GPR_GPR29_GPIO_MUX4_GPIO3_SEL_GPIO9 (1 << 3) +#define GPR_GPR29_GPIO_MUX4_GPIO4_SEL_GPIO4 (0 << 4) +#define GPR_GPR29_GPIO_MUX4_GPIO4_SEL_GPIO9 (1 << 4) +#define GPR_GPR29_GPIO_MUX4_GPIO5_SEL_GPIO4 (0 << 5) +#define GPR_GPR29_GPIO_MUX4_GPIO5_SEL_GPIO9 (1 << 5) +#define GPR_GPR29_GPIO_MUX4_GPIO6_SEL_GPIO4 (0 << 6) +#define GPR_GPR29_GPIO_MUX4_GPIO6_SEL_GPIO9 (1 << 6) +#define GPR_GPR29_GPIO_MUX4_GPIO7_SEL_GPIO4 (0 << 7) +#define GPR_GPR29_GPIO_MUX4_GPIO7_SEL_GPIO9 (1 << 7) +#define GPR_GPR29_GPIO_MUX4_GPIO8_SEL_GPIO4 (0 << 8) +#define GPR_GPR29_GPIO_MUX4_GPIO8_SEL_GPIO9 (1 << 8) +#define GPR_GPR29_GPIO_MUX4_GPIO9_SEL_GPIO4 (0 << 9) +#define GPR_GPR29_GPIO_MUX4_GPIO9_SEL_GPIO9 (1 << 9) +#define GPR_GPR29_GPIO_MUX4_GPIO10_SEL_GPIO4 (0 << 10) +#define GPR_GPR29_GPIO_MUX4_GPIO10_SEL_GPIO9 (1 << 10) +#define GPR_GPR29_GPIO_MUX4_GPIO11_SEL_GPIO4 (0 << 11) +#define GPR_GPR29_GPIO_MUX4_GPIO11_SEL_GPIO9 (1 << 11) +#define GPR_GPR29_GPIO_MUX4_GPIO12_SEL_GPIO4 (0 << 12) +#define GPR_GPR29_GPIO_MUX4_GPIO12_SEL_GPIO9 (1 << 12) +#define GPR_GPR29_GPIO_MUX4_GPIO13_SEL_GPIO4 (0 << 13) +#define GPR_GPR29_GPIO_MUX4_GPIO13_SEL_GPIO9 (1 << 13) +#define GPR_GPR29_GPIO_MUX4_GPIO14_SEL_GPIO4 (0 << 14) +#define GPR_GPR29_GPIO_MUX4_GPIO14_SEL_GPIO9 (1 << 14) +#define GPR_GPR29_GPIO_MUX4_GPIO15_SEL_GPIO4 (0 << 15) +#define GPR_GPR29_GPIO_MUX4_GPIO15_SEL_GPIO9 (1 << 15) +#define GPR_GPR29_GPIO_MUX4_GPIO16_SEL_GPIO4 (0 << 16) +#define GPR_GPR29_GPIO_MUX4_GPIO16_SEL_GPIO9 (1 << 16) +#define GPR_GPR29_GPIO_MUX4_GPIO17_SEL_GPIO4 (0 << 17) +#define GPR_GPR29_GPIO_MUX4_GPIO17_SEL_GPIO9 (1 << 17) +#define GPR_GPR29_GPIO_MUX4_GPIO18_SEL_GPIO4 (0 << 18) +#define GPR_GPR29_GPIO_MUX4_GPIO18_SEL_GPIO9 (1 << 18) +#define GPR_GPR29_GPIO_MUX4_GPIO19_SEL_GPIO4 (0 << 19) +#define GPR_GPR29_GPIO_MUX4_GPIO19_SEL_GPIO9 (1 << 19) +#define GPR_GPR29_GPIO_MUX4_GPIO20_SEL_GPIO4 (0 << 20) +#define GPR_GPR29_GPIO_MUX4_GPIO20_SEL_GPIO9 (1 << 20) +#define GPR_GPR29_GPIO_MUX4_GPIO21_SEL_GPIO4 (0 << 21) +#define GPR_GPR29_GPIO_MUX4_GPIO21_SEL_GPIO9 (1 << 21) +#define GPR_GPR29_GPIO_MUX4_GPIO22_SEL_GPIO4 (0 << 22) +#define GPR_GPR29_GPIO_MUX4_GPIO22_SEL_GPIO9 (1 << 22) +#define GPR_GPR29_GPIO_MUX4_GPIO23_SEL_GPIO4 (0 << 23) +#define GPR_GPR29_GPIO_MUX4_GPIO23_SEL_GPIO9 (1 << 23) +#define GPR_GPR29_GPIO_MUX4_GPIO24_SEL_GPIO4 (0 << 24) +#define GPR_GPR29_GPIO_MUX4_GPIO24_SEL_GPIO9 (1 << 24) +#define GPR_GPR29_GPIO_MUX4_GPIO25_SEL_GPIO4 (0 << 25) +#define GPR_GPR29_GPIO_MUX4_GPIO25_SEL_GPIO9 (1 << 25) +#define GPR_GPR29_GPIO_MUX4_GPIO26_SEL_GPIO4 (0 << 26) +#define GPR_GPR29_GPIO_MUX4_GPIO26_SEL_GPIO9 (1 << 26) +#define GPR_GPR29_GPIO_MUX4_GPIO27_SEL_GPIO4 (0 << 27) +#define GPR_GPR29_GPIO_MUX4_GPIO27_SEL_GPIO9 (1 << 27) +#define GPR_GPR29_GPIO_MUX4_GPIO28_SEL_GPIO4 (0 << 28) +#define GPR_GPR29_GPIO_MUX4_GPIO28_SEL_GPIO9 (1 << 28) +#define GPR_GPR29_GPIO_MUX4_GPIO29_SEL_GPIO4 (0 << 29) +#define GPR_GPR29_GPIO_MUX4_GPIO29_SEL_GPIO9 (1 << 29) +#define GPR_GPR29_GPIO_MUX4_GPIO30_SEL_GPIO4 (0 << 30) +#define GPR_GPR29_GPIO_MUX4_GPIO30_SEL_GPIO9 (1 << 30) +#define GPR_GPR29_GPIO_MUX4_GPIO31_SEL_GPIO4 (0 << 31) +#define GPR_GPR29_GPIO_MUX4_GPIO31_SEL_GPIO9 (1 << 31) + +/* General Purpose Register 30 (GPR30) */ + +#define GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT (12) +#define GPR_GPR30_FLEXSPI_REMAP_ADDR_START_MASK (1 << GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT) +# define GPR_GPR30_FLEXSPI_REMAP_ADDR_START(n) ((uint32_t)(n) << GPR_GPR30_FLEXSPI_REMAP_ADDR_START_SHIFT) + +/* General Purpose Register 31 (GPR31) */ + +#define GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT (12) +#define GPR_GPR31_FLEXSPI_REMAP_ADDR_END_MASK (1 << GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT) +# define GPR_GPR31_FLEXSPI_REMAP_ADDR_END(n) ((uint32_t)(n) << GPR_GPR31_FLEXSPI_REMAP_ADDR_END_SHIFT) + +/* General Purpose Register 32 (GPR32) */ + +#define GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT (12) +#define GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_MASK (1 << GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT) +# define GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET(n) ((uint32_t)(n) << GPR_GPR32_FLEXSPI_REMAP_ADDR_OFFSET_SHIFT) + +/* General Purpose Register 33 (GPR33) */ + +#define GPR_GPR33_OCRAM2_TZ_EN (1 << 0) +#define GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT (8) +#define GPR_GPR33_OCRAM2_TZ_ADDR_MASK (0x3f << GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT) +# define GPR_GPR33_OCRAM2_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR33_OCRAM2_TZ_ADDR_SHIFT) +#define GPR_GPR33_LOCK_OCRAM2_TZ_EN (1 << 16) +#define GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT (17) +#define GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_MASK (0x3f << GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT) +# define GPR_GPR33_LOCK_OCRAM2_TZ_ADDR(n) ((uint32_t)(n) << GPR_GPR33_LOCK_OCRAM2_TZ_ADDR_SHIFT) + +/* General Purpose Register 34 (GPR34) */ + +#define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT (0) +#define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_MASK (0xff << GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT) +#define GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL(n) ((uint32_t)(n) << GPR_GPR34_SIP_TEST_MUX_BOOT_PIN_SEL_SHIFT) +#define GPR_GPR34_SIP_TEST_MUX_QSPI_SIP_EN (1 << 8) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_IOMUXC_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h b/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h new file mode 100644 index 0000000000..35cdfde5fd --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt106x_memorymap.h @@ -0,0 +1,301 @@ +/************************************************************************************ + * arch/arm/src/imxrt/chip/imxrt105x_memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* System memory map */ + +#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */ + /* 0x00080000 512KB ITCM Reserved */ + /* 0x00100000 1MB ITCM Reserved */ +#define IMXRT_ROMCP_BASE 0x00200000 /* 128KB ROMCP */ + /* 0x00220000 384KB ROMCP Reserved */ + /* 0x00280000 1536KB Reserved */ + /* 0x00400000 124MB Reserved */ +#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */ +#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */ +#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ + /* 0x20080000 512KB DTCM Reserved */ + /* 0x20100000 1MB Reserved */ +#define IMXRT_OCRAM2_BASE 0x20200000 /* 512KB OCRAM2 */ +#define IMXRT_OCRAM_BASE 0x20280000 /* 512KB OCRAM FlexRAM */ + /* 0x20300000 512KB OCRAM Reserved */ + /* 0x20400000 252MB Reserved */ + /* 0x30000000 256MB Reserved */ +#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */ +#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */ +#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */ +#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */ + /* 40400000 12MB Reserved */ +#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */ +#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */ + /* 41200000 1MB Reserved for "per" GPV */ + /* 41300000 1MB Reserved for "ems" GPV */ +#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */ + /* 0x41500000 1MB GPV Reserved */ + /* 0x41600000 1MB GPV Reserved */ + /* 0x41700000 1MB GPV Reserved */ + /* 0x41800000 8MB Reserved */ +#define IMXRT_AIPS5_BASE 0x42000000 /* 1MB AIPS-5 */ + /* 0x42100000 31MB Reserved */ + /* 0x44000000 64MB Reserved */ + /* 0x48000000 384MB Reserved */ +#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 256MB FlexSPI/ FlexSPI ciphertext */ +#define IMXRT_FLEX2CIPHER_BASE 0x70000000 /* 240MB FlexSPI2/ FlexSPI ciphertext */ +#define IMXRT_FLEXSPI2TX_BASE 0x7f000000 /* 4MB FlexSPI2 TX FIFO */ +#define IMXRT_FLEXSPI2RX_BASE 0x7f400000 /* 4MB FlexSPI2 RX FIFO */ +#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */ +#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */ +#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */ +#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */ + /* 0xe0100000 511MB Reserved */ + +/* AIPS-1 memory map */ + + /* 0x40000000 256KB Reserved */ + /* 0x40040000 240KB Reserved */ +#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */ +#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */ +#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */ + /* 0x40088000 16KB Reserved */ + /* 0x4008c000 16KB Reserved */ +#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */ +#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */ + /* 0x40098000 16KB Reserved */ + /* 0x4009c000 16KB Reserved */ + /* 0x400a0000 16KB Reserved */ +#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */ +#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */ +#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */ +#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */ +#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */ +#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */ +#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */ +#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */ +#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */ +#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */ +#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */ +#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */ +#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */ +#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */ +#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */ + /* 0x400e0000 16KB Reserved */ + /* 0x400e4000 16KB Reserved */ +#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */ +#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */ + /* 400f0000 16KB Reserved */ +#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */ +#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */ +#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */ + +/* AIPS-2 memory map */ + + /* 0x40100000 256KB Reserved */ + /* 0x40140000 240KB Reserved */ +#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */ +#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/ +#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */ +#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */ +#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */ +#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */ +#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */ +#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */ +#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */ +#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */ + /* 0x401a4000 16KB Reserved */ + /* 0x401a8000 16KB Reserved */ +#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */ +#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */ + /* 0x401b4000 16KB Reserved */ +#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */ +#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */ +#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */ +#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */ + /* 0x401c8000 16KB Reserved */ + /* 0x401cc000 16KB Reserved */ +#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */ +#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */ +#define IMXRT_CAN3_BASE 0x401d8000 /* 16KB CAN3 */ +#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */ +#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */ +#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */ +#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */ +#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */ +#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */ +#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */ +#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */ +#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */ + +/* AIPS-3 memory map */ + + /* 0x40200000 256KB Reserved */ + /* 0x40240000 240KB Reserved */ +#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */ + /* 0x40280000 16KB Reserved */ + /* 0x40284000 16KB Reserved */ + /* 0x40288000 16KB Reserved */ + /* 0x4028c000 16KB Reserved */ + /* 0x40290000 16KB Reserved */ + /* 0x40294000 16KB Reserved */ + /* 0x40298000 16KB Reserved */ + /* 0x4029c000 16KB Reserved */ + /* 0x402a0000 16KB Reserved */ +#define IMXRT_FLEXSPI2C_BASE 0x402a4000 /* 16KB FlexSPI2 */ +#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI */ + /* 0x402ac000 16KB Reserved */ + /* 0x402b0000 16KB Reserved */ +#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */ +#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */ +#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */ +#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */ +#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */ + /* 0x402c8000 16KB Reserved */ + /* 0x402cc000 16KB Reserved */ + /* 0x402d0000 16KB Reserved */ + /* 0x402d4000 16KB Reserved */ +#define IMXRT_ENET2_BASE 0x402d4000 /* 16KB ENET2 */ +#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ +#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ +#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ + /* 0x402e4000 16KB Reserved */ + /* 0x402e8000 16KB Reserved */ + /* 0x402ec000 16KB Reserved */ +#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */ + /* 0x402f4000 16KB Reserved */ + /* 0x402f8000 16KB Reserved */ +#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */ + +/* AIPS-4 memory map */ + + /* 0x40300000 256KB Reserved */ + /* 0x40340000 240KB Reserved */ +#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */ +#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */ +#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */ +#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */ +#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */ + /* 0x40390000 16KB Reserved */ +#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */ +#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */ +#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */ +#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */ + /* 0x403a4000 16KB Reserved */ + /* 0x403a8000 16KB Reserved */ + /* 0x403ac000 16KB Reserved */ +#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */ +#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */ +#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */ +#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */ +#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */ +#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */ +#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */ +#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */ +#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */ +#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */ + /* 0x403d8000 16KB Reserved */ +#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */ +#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */ +#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */ +#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */ +#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */ +#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */ +#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */ +#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */ +#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */ + +/* AIPS-5 memory map */ + +#define IMXRT_GPIO6_BASE 0x42000000 /* 16KB GPIO6 */ +#define IMXRT_GPIO7_BASE 0x42004000 /* 16KB GPIO7 */ +#define IMXRT_GPIO8_BASE 0x42008000 /* 16KB GPIO8 */ +#define IMXRT_GPIO9_BASE 0x4200c000 /* 16KB GPIO9 */ + /* 0x42010000 16KB Reserved */ + /* 0x42014000 16KB Reserved */ + /* 0x42018000 16KB Reserved */ + /* 0x4201c000 16KB Reserved */ +#define IMXRT_FLEXIO3_BASE 0x42020000 /* 16KB FlexIO3 */ + /* 0x42024000 16KB Reserved */ + /* 0x42028000 16KB Reserved */ + /* 0x4202c000 16KB Reserved */ + /* 0x42030000 16KB Reserved */ + /* 0x42034000 16KB Reserved */ + /* 0x42038000 16KB Reserved */ + /* 0x4203c000 16KB Reserved */ + /* 0x42040000 16KB Reserved */ + /* 0x42044000 16KB Reserved */ + /* 0x42048000 16KB Reserved */ + /* 0x4204c000 16KB Reserved */ + /* 0x42050000 16KB Reserved */ + /* 0x42054000 16KB Reserved */ + /* 0x42058000 16KB Reserved */ + /* 0x4205c000 16KB Reserved */ + /* 0x42060000 16KB Reserved */ + /* 0x42064000 16KB Reserved */ + /* 0x42068000 16KB Reserved */ + /* 0x4206c000 16KB Reserved */ + /* 0x42070000 16KB Reserved */ + /* 0x42074000 16KB Reserved */ + /* 0x42078000 16KB Reserved */ + /* 0x4207c000 16KB Reserved */ + /* 0x42080000 512KB Reserved Off Platform */ + +/* PPB memory map */ + +#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */ +#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */ +#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */ +#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */ +#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */ + /* 0xe0045000 236KB PPB Reserved */ +#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */ + /* 0xe0081000 444KB PPB Reserved */ + /* 0xe00f0000 52KB PPB Reserved */ +#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */ +#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */ +#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */ + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_MEMORYMAP_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h b/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h new file mode 100644 index 0000000000..e98f99acbb --- /dev/null +++ b/arch/arm/src/imxrt/chip/imxrt106x_pinmux.h @@ -0,0 +1,1088 @@ +/***************************************************************************************************** + * arch/arm/src/imxrt/chip/imxrt105x_pinmux.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H +#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H + +/***************************************************************************************************** + * Included Files + *****************************************************************************************************/ + +#include +#include "chip/imxrt_iomuxc.h" + +/***************************************************************************************************** + * Pre-processor Definitions + *****************************************************************************************************/ + +/* Alternate Pin Functions. + * + * Alternative pin selections are provided with a numeric suffix like _1, _2, etc. Drivers, however, + * will use the pin selection without the numeric suffix. Additional definitions are required in the + * board.h file. For example, if LPUART1 CTS connects via the AD_B1_04 pin, then the following + * definition should appear in the board.h header file for that board: + * + * #define GPIO_LPUART3_CTS GPIO_LPUART3_CTS_1 + * + * The driver will then automatically configure to use the AD_B1_04 pin for LPUART1 CTS. + */ + +/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific IOMUX options such as frequency, open-drain, + * push-pull, and pull-up/down! Just the basics are defined for most pins in this file. See the + * upper imxrt_gpio.h and imxrt_iomuxc.h header files for available definitions. + */ + +/* Analog Comparator (ACMP) */ + +#define GPIO_ACMP_OUT00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_ACMP_OUT01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_ACMP_OUT02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_ACMP_OUT03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) + +/* ARM */ + +#define GPIO_ARM_CM7_RXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_ARM_CM7_TXEV (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) + +/* Clock Controller Module (CCM) */ + +#define GPIO_CCM_CLKO1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_CCM_CLKO2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_CCM_PMIC_RDY (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_CCM_PMIC_READY_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_CCM_PMIC_READY_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_CCM_PMIC_READY_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_CCM_PMIC_READY_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_CCM_PMIC_VSTBY_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) +#define GPIO_CCM_REF_EN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_CCM_STOP (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_CCM_WAIT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) + +/* CMOS Sensor Interface (CSI) */ + +#define GPIO_CSI_DATA00 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) +#define GPIO_CSI_DATA01 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) +#define GPIO_CSI_DATA02_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_CSI_DATA02_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_CSI_DATA03_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_CSI_DATA03_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_CSI_DATA04_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_CSI_DATA04_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_CSI_DATA05_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_CSI_DATA05_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_CSI_DATA06_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_CSI_DATA06_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_CSI_DATA07_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_CSI_DATA07_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_CSI_DATA08_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_CSI_DATA08_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_CSI_DATA09_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_CSI_DATA09_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_CSI_DATA10 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_CSI_DATA11 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) +#define GPIO_CSI_DATA12 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) +#define GPIO_CSI_DATA13 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) +#define GPIO_CSI_DATA14 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) +#define GPIO_CSI_DATA15 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) +#define GPIO_CSI_DATA16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_CSI_DATA17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_CSI_DATA18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_CSI_DATA19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_CSI_DATA20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_CSI_DATA21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_CSI_DATA22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_CSI_DATA23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_CSI_FIELD (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_CSI_HSYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_CSI_HSYNC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_CSI_HSYNC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_CSI_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) +#define GPIO_CSI_MCLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_CSI_PIXCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) +#define GPIO_CSI_PIXCLK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_CSI_VSYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) +#define GPIO_CSI_VSYNC_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_CSI_VSYNC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) + +/* Ethernet (ENET) */ + +#define GPIO_ENET_1588_EVENT0_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_ENET_1588_EVENT0_IN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) +#define GPIO_ENET_1588_EVENT0_IN_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_ENET_1588_EVENT0_OUT_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_ENET_1588_EVENT0_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) +#define GPIO_ENET_1588_EVENT0_OUT_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_ENET_1588_EVENT1_IN (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_ENET_1588_EVENT1_OUT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_ENET_1588_EVENT2_IN (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_ENET_1588_EVENT2_OUT (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_ENET_1588_EVENT3_IN (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_ENET_1588_EVENT3_OUT (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_ENET_COL (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_ENET_CRS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_ENET_MDC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_ENET_MDC_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_ENET_MDC_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_MDIO_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) +#define GPIO_ENET_MDIO_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_ENET_MDIO_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_LOW | IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_ENET_RDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_ENET_REF_CLK_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_ENET_REF_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ + IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) +#define GPIO_ENET_RX_CLK (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_ENET_RX_DATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_DATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_DATA02 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_ENET_RX_DATA03 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_ENET_RX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_ENET_RX_ER_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_RX_ER_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_ENET_TDATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_ENET_TDATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_ENET_TX_CLK_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_SION_ENABLE | \ + GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_40OHM | IOMUX_SPEED_LOW | \ + IOMUX_PULL_DOWN_100K | IOMUX_PULL_KEEP) +#define GPIO_ENET_TX_CLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_ENET_TX_DATA00 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_DATA01 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_DATA02 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_ENET_TX_DATA03 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_ENET_TX_EN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX) | \ + IOMUX_SLEW_FAST | IOMUX_DRIVE_50OHM | IOMUX_SPEED_MAX | \ + IOMUX_PULL_UP_100K | _IOMUX_PULL_ENABLE) +#define GPIO_ENET_TX_EN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_ENET_TX_ER (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) + +/* External Watchdog Monitor (EWM) */ + +#define GPIO_EWM_OUT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_EWM_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_EWM_OUT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) + +/* Flexible Controller Area Network (FLEXCAN) */ + +#define GPIO_FLEXCAN1_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_FLEXCAN1_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define GPIO_FLEXCAN1_RX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_FLEXCAN1_RX_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_FLEXCAN1_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_FLEXCAN1_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) +#define GPIO_FLEXCAN1_TX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_FLEXCAN1_TX_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) + +#define GPIO_FLEXCAN2_RX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_FLEXCAN2_RX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_FLEXCAN2_RX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_FLEXCAN2_RX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_FLEXCAN2_TX_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_FLEXCAN2_TX_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_FLEXCAN2_TX_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_FLEXCAN2_TX_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) + +/* Flexible I/O (FlexIO) */ + +#define GPIO_FLEXIO1_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_FLEXIO1_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_FLEXIO1_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_FLEXIO1_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_FLEXIO1_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_FLEXIO1_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_FLEXIO1_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_FLEXIO1_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_FLEXIO1_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_FLEXIO1_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_FLEXIO1_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_FLEXIO1_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_FLEXIO1_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_FLEXIO1_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_FLEXIO1_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_FLEXIO1_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) + +#define GPIO_FLEXIO2_FLEXIO00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_FLEXIO2_FLEXIO01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_FLEXIO2_FLEXIO02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) +#define GPIO_FLEXIO2_FLEXIO03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define GPIO_FLEXIO2_FLEXIO04 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_FLEXIO2_FLEXIO05 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_FLEXIO2_FLEXIO06 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_FLEXIO2_FLEXIO07 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_FLEXIO2_FLEXIO08 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) +#define GPIO_FLEXIO2_FLEXIO09 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_FLEXIO2_FLEXIO10 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_FLEXIO2_FLEXIO11 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_FLEXIO2_FLEXIO12 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_FLEXIO2_FLEXIO13 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_FLEXIO2_FLEXIO14 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_FLEXIO2_FLEXIO15 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_FLEXIO2_FLEXIO16 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_FLEXIO2_FLEXIO17 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_FLEXIO2_FLEXIO18 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_FLEXIO2_FLEXIO19 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) +#define GPIO_FLEXIO2_FLEXIO20 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) +#define GPIO_FLEXIO2_FLEXIO21 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) +#define GPIO_FLEXIO2_FLEXIO22 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) +#define GPIO_FLEXIO2_FLEXIO23 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) +#define GPIO_FLEXIO2_FLEXIO24 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) +#define GPIO_FLEXIO2_FLEXIO25 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_FLEXIO2_FLEXIO26 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) +#define GPIO_FLEXIO2_FLEXIO27 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) +#define GPIO_FLEXIO2_FLEXIO28 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) +#define GPIO_FLEXIO2_FLEXIO29 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) +#define GPIO_FLEXIO2_FLEXIO30 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_FLEXIO2_FLEXIO31 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) + +/* Enhanced Flex Pulse Width Modulator (eFlexPWM) */ + +#define GPIO_FLEXPWM1_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_FLEXPWM1_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_FLEXPWM1_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_FLEXPWM1_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_FLEXPWM1_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_FLEXPWM1_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_FLEXPWM1_PWMA03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_FLEXPWM1_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_FLEXPWM1_PWMB00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_FLEXPWM1_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_FLEXPWM1_PWMB01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_FLEXPWM1_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_FLEXPWM1_PWMB02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_4 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_FLEXPWM1_PWMB03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_FLEXPWM1_PWMX00 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_FLEXPWM1_PWMX01 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_FLEXPWM1_PWMX02 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_FLEXPWM1_PWMX03 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) + +#define GPIO_FLEXPWM2_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_FLEXPWM2_PWMA00_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_FLEXPWM2_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_FLEXPWM2_PWMA01_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) +#define GPIO_FLEXPWM2_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_FLEXPWM2_PWMA02_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_4 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_FLEXPWM2_PWMA03_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_FLEXPWM2_PWMB00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_FLEXPWM2_PWMB00_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_FLEXPWM2_PWMB01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_FLEXPWM2_PWMB01_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_FLEXPWM2_PWMB02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_FLEXPWM2_PWMB02_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_FLEXPWM2_PWMB03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_FLEXPWM2_PWMB03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_FLEXPWM2_PWMB03_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_FLEXPWM2_PWMB03_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) + +#define GPIO_FLEXPWM3_PWMA00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_FLEXPWM3_PWMA01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_FLEXPWM3_PWMA02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_FLEXPWM3_PWMA03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_FLEXPWM3_PWMB00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_FLEXPWM3_PWMB01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_FLEXPWM3_PWMB02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_FLEXPWM3_PWMB03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) + +#define GPIO_FLEXPWM4_PWMA00_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_FLEXPWM4_PWMA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_FLEXPWM4_PWMA01_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_FLEXPWM4_PWMA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_FLEXPWM4_PWMA02_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_FLEXPWM4_PWMA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_FLEXPWM4_PWMA03_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) +#define GPIO_FLEXPWM4_PWMA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_FLEXPWM4_PWMB00 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_FLEXPWM4_PWMB01 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_FLEXPWM4_PWMB02 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_FLEXPWM4_PWMB03 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) + +/* Flexible SPI (FlexSPI) */ + +#define GPIO_FLEXSPIA_DATA00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_FLEXSPIA_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_FLEXSPIA_DATA01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_FLEXSPIA_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_FLEXSPIA_DATA02_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_FLEXSPIA_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_FLEXSPIA_DATA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_FLEXSPIA_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_FLEXSPIA_DQS_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_FLEXSPIA_DQS_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_FLEXSPIA_SCLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_FLEXSPIA_SCLK_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_FLEXSPIA_SS0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_FLEXSPIA_SS0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_FLEXSPIA_SS1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_FLEXSPIA_SS1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_FLEXSPIA_SS1_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) + +#define GPIO_FLEXSPIB_DATA00_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_FLEXSPIB_DATA00_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_FLEXSPIB_DATA01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_FLEXSPIB_DATA01_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_FLEXSPIB_DATA02_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_FLEXSPIB_DATA02_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_FLEXSPIB_DATA03_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_FLEXSPIB_DATA03_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_FLEXSPIB_DQS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_FLEXSPIB_SCLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_FLEXSPIB_SS0_1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_FLEXSPIB_SS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_FLEXSPIB_SS1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) + +/* GPIO */ + +#define GPIO_GPIO1_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_GPIO1_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_GPIO1_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_GPIO1_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_GPIO1_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_GPIO1_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_GPIO1_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_GPIO1_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_GPIO1_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_GPIO1_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_GPIO1_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_GPIO1_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_GPIO1_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_GPIO1_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_GPIO1_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_GPIO1_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_GPIO1_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_GPIO1_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_GPIO1_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_GPIO1_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_GPIO1_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_GPIO1_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_GPIO1_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_GPIO1_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_GPIO1_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_GPIO1_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_GPIO1_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_GPIO1_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_GPIO1_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_GPIO1_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_GPIO1_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_GPIO1_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) + +#define GPIO_GPIO2_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_GPIO2_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_GPIO2_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) +#define GPIO_GPIO2_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define GPIO_GPIO2_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_GPIO2_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_GPIO2_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_GPIO2_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_GPIO2_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) +#define GPIO_GPIO2_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_GPIO2_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_GPIO2_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_GPIO2_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_GPIO2_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_GPIO2_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_GPIO2_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_GPIO2_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_GPIO2_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_GPIO2_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_GPIO2_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) +#define GPIO_GPIO2_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) +#define GPIO_GPIO2_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) +#define GPIO_GPIO2_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) +#define GPIO_GPIO2_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) +#define GPIO_GPIO2_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) +#define GPIO_GPIO2_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_GPIO2_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) +#define GPIO_GPIO2_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) +#define GPIO_GPIO2_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) +#define GPIO_GPIO2_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) +#define GPIO_GPIO2_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_GPIO2_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) + +#define GPIO_GPIO3_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_GPIO3_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_GPIO3_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_GPIO3_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_GPIO3_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_GPIO3_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_GPIO3_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_GPIO3_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_GPIO3_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_GPIO3_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_GPIO3_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_GPIO3_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_GPIO3_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_GPIO3_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_GPIO3_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_GPIO3_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_GPIO3_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_GPIO3_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_GPIO3_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_GPIO3_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_GPIO3_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_GPIO3_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_GPIO3_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_GPIO3_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_GPIO3_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_GPIO3_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_GPIO3_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_GPIO3_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) + +#define GPIO_GPIO4_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_GPIO4_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_GPIO4_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_GPIO4_IO03 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_GPIO4_IO04 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_GPIO4_IO05 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_GPIO4_IO06 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_GPIO4_IO07 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_GPIO4_IO08 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_GPIO4_IO09 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_GPIO4_IO10 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_GPIO4_IO11 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_GPIO4_IO12 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_GPIO4_IO13 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_GPIO4_IO14 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_GPIO4_IO15 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_GPIO4_IO16 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_GPIO4_IO17 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_GPIO4_IO18 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_GPIO4_IO19 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_GPIO4_IO20 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_GPIO4_IO21 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_GPIO4_IO22 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_GPIO4_IO23 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_GPIO4_IO24 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_GPIO4_IO25 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_GPIO4_IO26 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_GPIO4_IO27 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_GPIO4_IO28 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_GPIO4_IO29 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_GPIO4_IO30 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_GPIO4_IO31 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) + +#define GPIO_GPIO5_IO00 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) +#define GPIO_GPIO5_IO01 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) +#define GPIO_GPIO5_IO02 (GPIO_PERIPH | GPIO_ALT5 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_STBY_REQ_INDEX)) + +/* General Purpose Timer (GPT) */ + +#define GPIO_GPT1_CAPTURE1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_GPT1_CAPTURE2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_GPT1_CLK (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_GPT1_COMPARE1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_GPT1_COMPARE2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_GPT1_COMPARE3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) + +#define GPIO_GPT2_CAPTURE1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_GPT2_CAPTURE2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_GPT2_CLK (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_GPT2_COMPARE2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_GPT2_COMPARE3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) + +/* JTAG */ + +#define GPIO_JTAG_ACTIVE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_JTAG_DE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_JTAG_DONE (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_JTAG_FAIL (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_JTAG_MOD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_JTAG_TCK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_JTAG_TDI (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_JTAG_TDO (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_JTAG_TRSTB (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) + +/* Keypad Port (KPP) */ + +#define GPIO_KPP_COL00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_KPP_COL01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_KPP_COL02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_KPP_COL03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_KPP_COL04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_KPP_COL05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_KPP_COL06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_KPP_COL07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_KPP_ROW00 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_KPP_ROW01 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_KPP_ROW02 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_KPP_ROW03 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_KPP_ROW04 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_KPP_ROW05 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_KPP_ROW06 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_KPP_ROW07 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) + +/* LCD */ + +#define GPIO_LCD_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_LCD_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_LCD_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_LCD_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_LCD_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_LCD_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) +#define GPIO_LCD_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_LCD_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_LCD_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_LCD_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_LCD_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_LCD_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_LCD_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_LCD_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_LCD_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_LCD_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_LCD_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) +#define GPIO_LCD_DATA16 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX)) +#define GPIO_LCD_DATA17 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX)) +#define GPIO_LCD_DATA18 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX)) +#define GPIO_LCD_DATA19 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX)) +#define GPIO_LCD_DATA20 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) +#define GPIO_LCD_DATA21 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_LCD_DATA22 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) +#define GPIO_LCD_DATA23 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) +#define GPIO_LCD_ENABLE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_LCD_HSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) +#define GPIO_LCD_VSYNC (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) + +/* Low Power Inter-Integrated Circuit (LPI2C) */ + +#define GPIO_LPI2C1_HREQ (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_LPI2C1_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_LPI2C1_SCL_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C1_SCLS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_LPI2C1_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_LPI2C1_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_PULL_UP_22K | IOMUX_OPENDRAIN | \ + IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C1_SDAS (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) + +#define GPIO_LPI2C2_SCL_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_LPI2C2_SCL_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_LPI2C2_SDA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_LPI2C2_SDA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) + +#define GPIO_LPI2C3_SCL_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_LPI2C3_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C3_SCL_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_LPI2C3_SDA_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_LPI2C3_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C3_SDA_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) + +#define GPIO_LPI2C4_SCL_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) +#define GPIO_LPI2C4_SCL_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) +#define GPIO_LPI2C4_SDA_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_LPI2C4_SDA_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX) | \ + GPIO_SION_ENABLE | IOMUX_OPENDRAIN | IOMUX_SPEED_MEDIUM | IOMUX_DRIVE_33OHM) + +/* Low Power Serial Peripheral Interface (LPSPI) */ + +#define IOMUX_LPSPI (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ + IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM) + +#define GPIO_LPSPI1_PCS0_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_PCS3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SCK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDI_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDO_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI1_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX) | IOMUX_LPSPI) + +#define GPIO_LPSPI2_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS1 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_PCS3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SCK_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDI_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI2_SDO_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX) | IOMUX_LPSPI) + +#define GPIO_LPSPI3_PCS0_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS0_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS1 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_PCS3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SCK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SCK_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SDI_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SDI_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SDO_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI3_SDO_2 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX) | IOMUX_LPSPI) + +#define GPIO_LPSPI4_PCS0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_04_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS0_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_PCS3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SCK_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_07_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SCK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDI_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_05_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDI_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDO_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_06_INDEX) | IOMUX_LPSPI) +#define GPIO_LPSPI4_SDO_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX) | IOMUX_LPSPI) + +/* Low Power Universal Asynchronous Receiver/Transmitter (LPUART) */ + +#define IOMUX_UART (IOMUX_PULL_UP_100K | IOMUX_CMOS_OUTPUT | IOMUX_DRIVE_40OHM | \ + IOMUX_SLEW_FAST | IOMUX_SPEED_MEDIUM | IOMUX_SCHMITT_TRIGGER) + +#define GPIO_LPUART1_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_LPUART1_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_LPUART1_RX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX) | IOMUX_UART) +#define GPIO_LPUART1_TX (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX) | IOMUX_UART) + +#define GPIO_LPUART2_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_LPUART2_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_LPUART2_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX) | IOMUX_UART) +#define GPIO_LPUART2_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX) | IOMUX_UART) +#define GPIO_LPUART2_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX) | IOMUX_UART) +#define GPIO_LPUART2_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX) | IOMUX_UART) + +#define GPIO_LPUART3_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_LPUART3_CTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_LPUART3_RTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_LPUART3_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_LPUART3_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_RX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX) | IOMUX_UART) +#define GPIO_LPUART3_TX_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX) | IOMUX_UART) + +#define GPIO_LPUART4_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_LPUART4_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_LPUART4_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_RX_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX) | IOMUX_UART) +#define GPIO_LPUART4_TX_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX) | IOMUX_UART) + +#define GPIO_LPUART5_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) +#define GPIO_LPUART5_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_LPUART5_RX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX) | IOMUX_UART) +#define GPIO_LPUART5_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_LPUART5_TX_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX) | IOMUX_UART) +#define GPIO_LPUART5_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) + +#define GPIO_LPUART6_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_LPUART6_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_LPUART6_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX) | IOMUX_UART) +#define GPIO_LPUART6_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX) | IOMUX_UART) + +#define GPIO_LPUART7_CTS_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_LPUART7_RTS_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_LPUART7_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_LPUART7_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_LPUART7_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_LPUART7_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) + +#define GPIO_LPUART8_CTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_LPUART8_RTS (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_LPUART8_RX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_RX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_RX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_TX_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_TX_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX) | IOMUX_UART) +#define GPIO_LPUART8_TX_3 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX) | IOMUX_UART) + +/* Medium Quality Sound (MQS) */ + +#define GPIO_MQS_LEFT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_MQS_LEFT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_MQS_LEFT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_MQS_RIGHT_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_MQS_RIGHT_2 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_MQS_RIGHT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) + +/* NMI */ + +#define GPIO_NMI_GLUE_NMI (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_WAKEUP_INDEX)) + +/* Periodic Interrupt Timer (PIT) */ + +#define GPIO_PIT_TRIGGER00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) + +/* Quad Timer (QTimer) */ + +#define GPIO_QTIMER1_TIMER0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_QTIMER1_TIMER1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_QTIMER1_TIMER2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) +#define GPIO_QTIMER1_TIMER3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_08_INDEX)) + +#define GPIO_QTIMER2_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define GPIO_QTIMER2_TIMER0_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_QTIMER2_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_QTIMER2_TIMER1_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_QTIMER2_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_QTIMER2_TIMER2_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_QTIMER2_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_09_INDEX)) +#define GPIO_QTIMER2_TIMER3_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) + +#define GPIO_QTIMER3_TIMER0_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_QTIMER3_TIMER0_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_QTIMER3_TIMER0_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_QTIMER3_TIMER1_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_QTIMER3_TIMER1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_QTIMER3_TIMER1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_QTIMER3_TIMER2_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_QTIMER3_TIMER2_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) +#define GPIO_QTIMER3_TIMER2_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_QTIMER3_TIMER3_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_QTIMER3_TIMER3_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_10_INDEX)) +#define GPIO_QTIMER3_TIMER3_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) + +#define GPIO_QTIMER4_TIMER0 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_QTIMER4_TIMER1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_QTIMER4_TIMER2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_QTIMER4_TIMER3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_11_INDEX)) + +/* XTALOSC Reference Clock */ + +#define GPIO_REF_CLK_24M_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_REF_CLK_24M_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_REF_CLK_24M_3 (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_13_INDEX)) +#define GPIO_REF_CLK_32K (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) + +/* Synchronous Audio Interface (SAI) */ + +#define GPIO_SAI1_MCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_SAI1_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_SAI1_MCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_SAI1_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_SAI1_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_SAI1_RX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_SAI1_RX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_SAI1_RX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_SAI1_RX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_SAI1_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_SAI1_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_SAI1_RX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_SAI1_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_SAI1_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_SAI1_TX_BCLK_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_SAI1_TX_DATA00_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_SAI1_TX_DATA00_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_SAI1_TX_DATA00_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_SAI1_TX_DATA01_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_SAI1_TX_DATA01_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_SAI1_TX_DATA02_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_SAI1_TX_DATA02_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_SAI1_TX_DATA03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_SAI1_TX_DATA03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_SAI1_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_SAI1_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) +#define GPIO_SAI1_TX_SYNC_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) + +#define GPIO_SAI2_MCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_SAI2_MCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_SAI2_RX_BCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_SAI2_RX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_SAI2_RX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_SAI2_RX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_SAI2_RX_SYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_SAI2_RX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_SAI2_TX_BCLK_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_SAI2_TX_BCLK_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_SAI2_TX_DATA_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_SAI2_TX_DATA_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_SAI2_TX_SYNC_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_SAI2_TX_SYNC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) + +#define GPIO_SAI3_MCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_SAI3_RX_BCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_SAI3_RX_DATA (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_SAI3_RX_SYNC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_SAI3_TX_BCLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_SAI3_TX_DATA (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_SAI3_TX_SYNC (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) + +/* Smart External Memory Controller (SEMC) */ + +#define GPIO_SEMC_ADDR00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_09_INDEX)) +#define GPIO_SEMC_ADDR01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_10_INDEX)) +#define GPIO_SEMC_ADDR02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_SEMC_ADDR03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_SEMC_ADDR04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_SEMC_ADDR05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_SEMC_ADDR06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_SEMC_ADDR07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_SEMC_ADDR08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_17_INDEX)) +#define GPIO_SEMC_ADDR09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) +#define GPIO_SEMC_ADDR10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_23_INDEX)) +#define GPIO_SEMC_ADDR11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_SEMC_ADDR12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_20_INDEX)) +#define GPIO_SEMC_BA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_21_INDEX)) +#define GPIO_SEMC_BA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_22_INDEX)) +#define GPIO_SEMC_CAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_24_INDEX)) +#define GPIO_SEMC_CKE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_27_INDEX)) +#define GPIO_SEMC_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_26_INDEX)) +#define GPIO_SEMC_CS0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_29_INDEX)) +#define GPIO_SEMC_CSX00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_SEMC_CSX01_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_07_INDEX)) +#define GPIO_SEMC_CSX01_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_00_INDEX)) +#define GPIO_SEMC_CSX02_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_01_INDEX)) +#define GPIO_SEMC_CSX02_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_SEMC_CSX03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_02_INDEX)) +#define GPIO_SEMC_DATA00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) +#define GPIO_SEMC_DATA01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_SEMC_DATA02 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_SEMC_DATA03 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_SEMC_DATA04 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_SEMC_DATA05 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_SEMC_DATA06 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_SEMC_DATA07 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_SEMC_DATA08 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_30_INDEX)) +#define GPIO_SEMC_DATA09 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_31_INDEX)) +#define GPIO_SEMC_DATA10 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_32_INDEX)) +#define GPIO_SEMC_DATA11 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_SEMC_DATA12 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_SEMC_DATA13 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_SEMC_DATA14 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_SEMC_DATA15 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_SEMC_DM00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_SEMC_DM01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_SEMC_DQS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_SEMC_RAS (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_25_INDEX)) +#define GPIO_SEMC_RDY (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_SEMC_WE (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_28_INDEX)) + +/* Secure Non-Volatile Storage (SNVS) */ + +#define GPIO_SNVS_LP_PMIC_ON_REQ (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_PMIC_ON_REQ_INDEX)) +#define GPIO_SNVS_VIO_5 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_19_INDEX)) +#define GPIO_SNVS_VIO_5_CTL (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_18_INDEX)) + +/* Sony/Philips Digital Interface (SPDIF) */ + +#define GPIO_SPDIF_EXT_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_SPDIF_IN_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_SPDIF_IN_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_SPDIF_LOCK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_SPDIF_OUT_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_SPDIF_OUT_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_SPDIF_OUT_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_SPDIF_SR_CLK (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) + +/* Boot Configuration */ + +#define GPIO_SRC_BOOT_CFG00 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_04_INDEX)) +#define GPIO_SRC_BOOT_CFG01 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_05_INDEX)) +#define GPIO_SRC_BOOT_CFG02 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_06_INDEX)) +#define GPIO_SRC_BOOT_CFG03 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_07_INDEX)) +#define GPIO_SRC_BOOT_CFG04 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_08_INDEX)) +#define GPIO_SRC_BOOT_CFG05 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_09_INDEX)) +#define GPIO_SRC_BOOT_CFG06 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_10_INDEX)) +#define GPIO_SRC_BOOT_CFG07 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_11_INDEX)) +#define GPIO_SRC_BOOT_CFG08 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_SRC_BOOT_CFG09 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_SRC_BOOT_CFG10 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_SRC_BOOT_CFG11 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_SRC_BOOT_MODE00 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_04_INDEX)) +#define GPIO_SRC_BOOT_MODE01 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) + +/* USB OTG */ + +#define GPIO_USB_OTG1_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_USB_OTG1_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_USB_OTG1_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_USB_OTG1_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_USB_OTG1_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_USB_OTG1_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) + +#define GPIO_USB_OTG2_ID_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_USB_OTG2_ID_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_USB_OTG2_OC_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_USB_OTG2_OC_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_USB_OTG2_PWR_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_USB_OTG2_PWR_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) + +/* Ultra Secured Digital Host Controller (uSDHC) */ + +#define GPIO_USDHC1_CD_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_02_INDEX)) +#define GPIO_USDHC1_CD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_12_INDEX)) +#define GPIO_USDHC1_CD_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_USDHC1_CLK (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_USDHC1_CMD (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_USDHC1_DATA0 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_USDHC1_DATA1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_USDHC1_DATA2 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_USDHC1_DATA3 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_USDHC1_RESET_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_33_INDEX)) +#define GPIO_USDHC1_RESET_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_USDHC1_RESET_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) +#define GPIO_USDHC1_VSELECT_1 (GPIO_PERIPH | GPIO_ALT2 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_34_INDEX)) +#define GPIO_USDHC1_VSELECT_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_01_INDEX)) +#define GPIO_USDHC1_VSELECT_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_USDHC1_VSELECT_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_41_INDEX)) +#define GPIO_USDHC1_WP_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_USDHC1_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_USDHC1_WP_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) +#define GPIO_USDHC1_WP_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) + +#define GPIO_USDHC2_CD_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_03_INDEX)) +#define GPIO_USDHC2_CD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_USDHC2_CLK_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_04_INDEX)) +#define GPIO_USDHC2_CLK_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_09_INDEX)) +#define GPIO_USDHC2_CMD_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_05_INDEX)) +#define GPIO_USDHC2_CMD_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_08_INDEX)) +#define GPIO_USDHC2_DATA0_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_03_INDEX)) +#define GPIO_USDHC2_DATA0_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_04_INDEX)) +#define GPIO_USDHC2_DATA1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_02_INDEX)) +#define GPIO_USDHC2_DATA1_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_05_INDEX)) +#define GPIO_USDHC2_DATA2_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_01_INDEX)) +#define GPIO_USDHC2_DATA2_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_06_INDEX)) +#define GPIO_USDHC2_DATA3_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_00_INDEX)) +#define GPIO_USDHC2_DATA3_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_07_INDEX)) +#define GPIO_USDHC2_DATA4_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_08_INDEX)) +#define GPIO_USDHC2_DATA4_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_12_INDEX)) +#define GPIO_USDHC2_DATA5_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_09_INDEX)) +#define GPIO_USDHC2_DATA5_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_13_INDEX)) +#define GPIO_USDHC2_DATA6_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_10_INDEX)) +#define GPIO_USDHC2_DATA6_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_14_INDEX)) +#define GPIO_USDHC2_DATA7_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_11_INDEX)) +#define GPIO_USDHC2_DATA7_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_15_INDEX)) +#define GPIO_USDHC2_RESET_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B1_06_INDEX)) +#define GPIO_USDHC2_RESET_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_11_INDEX)) +#define GPIO_USDHC2_RESET_3 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_11_INDEX)) +#define GPIO_USDHC2_RESET_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_40_INDEX)) +#define GPIO_USDHC2_VSELECT (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_38_INDEX)) +#define GPIO_USDHC2_WP_1 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_USDHC2_WP_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) + +/* Watchdog Timer (WDOG1-2) */ + +#define GPIO_WDOG1_1 (GPIO_PERIPH | GPIO_ALT0 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_13_INDEX)) +#define GPIO_WDOG1_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_10_INDEX)) +#define GPIO_WDOG1_3 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B1_00_INDEX)) +#define GPIO_WDOG1_WDOG_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_WDOG1_WDOG_2 (GPIO_PERIPH | GPIO_ALT4 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_39_INDEX)) +#define GPIO_WDOG1_WDOG_RST_DEB (GPIO_PERIPH | GPIO_ALT7 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) + +#define GPIO_WDOG2_RESET_DEB (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_03_INDEX)) +#define GPIO_WDOG2_WDOG (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_12_INDEX)) + +/* Inter-Peripheral Crossbar Switch A (XBARA) */ + +#define GPIO_XBAR1_IN02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_14_INDEX)) +#define GPIO_XBAR1_IN03_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_15_INDEX)) +#define GPIO_XBAR1_IN03_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_01_INDEX)) +#define GPIO_XBAR1_IN20_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_15_INDEX)) +#define GPIO_XBAR1_IN20_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_08_INDEX)) +#define GPIO_XBAR1_IN21_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_16_INDEX)) +#define GPIO_XBAR1_IN21_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_09_INDEX)) +#define GPIO_XBAR1_IN22_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_36_INDEX)) +#define GPIO_XBAR1_IN22_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_10_INDEX)) +#define GPIO_XBAR1_IN23_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_37_INDEX)) +#define GPIO_XBAR1_IN23_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_11_INDEX)) +#define GPIO_XBAR1_IN24_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_14_INDEX)) +#define GPIO_XBAR1_IN24_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_12_INDEX)) +#define GPIO_XBAR1_IN25_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_15_INDEX)) +#define GPIO_XBAR1_IN25_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_13_INDEX)) +#define GPIO_XBAR1_INOUT04_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_02_INDEX)) +#define GPIO_XBAR1_INOUT04_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_00_INDEX)) +#define GPIO_XBAR1_INOUT05_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_03_INDEX)) +#define GPIO_XBAR1_INOUT05_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_01_INDEX)) +#define GPIO_XBAR1_INOUT06_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_04_INDEX)) +#define GPIO_XBAR1_INOUT06_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_02_INDEX)) +#define GPIO_XBAR1_INOUT07_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_05_INDEX)) +#define GPIO_XBAR1_INOUT07_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_03_INDEX)) +#define GPIO_XBAR1_INOUT08_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_06_INDEX)) +#define GPIO_XBAR1_INOUT08_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_04_INDEX)) +#define GPIO_XBAR1_INOUT09_1 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_07_INDEX)) +#define GPIO_XBAR1_INOUT09_2 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_SD_B0_05_INDEX)) +#define GPIO_XBAR1_INOUT10 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_12_INDEX)) +#define GPIO_XBAR1_INOUT11 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_13_INDEX)) +#define GPIO_XBAR1_INOUT12 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_14_INDEX)) +#define GPIO_XBAR1_INOUT13 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B0_15_INDEX)) +#define GPIO_XBAR1_INOUT14_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_00_INDEX)) +#define GPIO_XBAR1_INOUT14_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_00_INDEX)) +#define GPIO_XBAR1_INOUT15_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_01_INDEX)) +#define GPIO_XBAR1_INOUT15_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_01_INDEX)) +#define GPIO_XBAR1_INOUT16_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_02_INDEX)) +#define GPIO_XBAR1_INOUT16_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_02_INDEX)) +#define GPIO_XBAR1_INOUT17_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_03_INDEX)) +#define GPIO_XBAR1_INOUT17_2 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_B1_03_INDEX)) +#define GPIO_XBAR1_INOUT17_3 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_08_INDEX)) +#define GPIO_XBAR1_INOUT17_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_05_INDEX)) +#define GPIO_XBAR1_INOUT18_1 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_35_INDEX)) +#define GPIO_XBAR1_INOUT18_2 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_06_INDEX)) +#define GPIO_XBAR1_INOUT19_3 (GPIO_PERIPH | GPIO_ALT1 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_14_INDEX)) +#define GPIO_XBAR1_INOUT19_4 (GPIO_PERIPH | GPIO_ALT6 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_AD_B0_07_INDEX)) +#define GPIO_XBAR1_XBAR_IN02 (GPIO_PERIPH | GPIO_ALT3 | GPIO_PADMUX(IMXRT_PADMUX_GPIO_EMC_00_INDEX)) + +#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT106X_PINMUX_H */ diff --git a/arch/arm/src/imxrt/chip/imxrt_dmamux.h b/arch/arm/src/imxrt/chip/imxrt_dmamux.h index df1695043b..ff58300b67 100644 --- a/arch/arm/src/imxrt/chip/imxrt_dmamux.h +++ b/arch/arm/src/imxrt/chip/imxrt_dmamux.h @@ -2,7 +2,8 @@ * arch/arm/src/imxrt/chip/imxrt_dmamux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,8 @@ #if defined(CONFIG_ARCH_FAMILY_IMXRT105x) # include "chip/imxrt105x_dmamux.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/imxrt106x_dmamux.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/chip/imxrt_gpio.h b/arch/arm/src/imxrt/chip/imxrt_gpio.h index f91790ee88..9b030ad97d 100644 --- a/arch/arm/src/imxrt/chip/imxrt_gpio.h +++ b/arch/arm/src/imxrt/chip/imxrt_gpio.h @@ -2,7 +2,8 @@ * arch/arm/src/imxrt/imxrt_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,7 +42,14 @@ ********************************************************************************************/ #include -#include "chip/imxrt_memorymap.h" + +#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/imxrt105x_gpio.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/imxrt106x_gpio.h" +#else +# error Unrecognized i.MX RT architecture +#endif /******************************************************************************************** * Pre-processor Definitions @@ -52,68 +60,14 @@ #define GPIO3 2 /* Port 3 index */ #define GPIO4 3 /* Port 4 index */ #define GPIO5 4 /* Port 5 index */ - -#define IMXRT_GPIO_NPORTS 5 /* Five total ports */ +#if IMXRT_GPIO_NPORTS > 5 +#define GPIO6 5 /* Port 6 index */ +#define GPIO7 6 /* Port 7 index */ +#define GPIO8 7 /* Port 8 index */ +#define GPIO9 8 /* Port 9 index */ +#endif #define IMXRT_GPIO_NPINS 32 /* Up to 32 pins per port */ -/* Register offsets *************************************************************************/ - -#define IMXRT_GPIO_DR_OFFSET 0x0000 /* GPIO data register */ -#define IMXRT_GPIO_GDIR_OFFSET 0x0004 /* GPIO direction register */ -#define IMXRT_GPIO_PSR_OFFSET 0x0008 /* GPIO pad status register */ -#define IMXRT_GPIO_ICR1_OFFSET 0x000c /* GPIO interrupt configuration register1 */ -#define IMXRT_GPIO_ICR2_OFFSET 0x0010 /* GPIO interrupt configuration register2 */ -#define IMXRT_GPIO_IMR_OFFSET 0x0014 /* GPIO interrupt mask register */ -#define IMXRT_GPIO_ISR_OFFSET 0x0018 /* GPIO interrupt status register */ -#define IMXRT_GPIO_EDGE_OFFSET 0x001c /* GPIO edge select register */ - -/* Register addresses ***********************************************************************/ - -#define IMXRT_GPIO1_DR (IMXRT_GPIO1_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO1_GDIR (IMXRT_GPIO1_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO1_PSR (IMXRT_GPIO1_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO1_ICR1 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO1_ICR2 (IMXRT_GPIO1_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO1_IMR (IMXRT_GPIO1_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO1_ISR (IMXRT_GPIO1_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO1_EDGE (IMXRT_GPIO1_BASE + IMXRT_GPIO_EDGE_OFFSET) - -#define IMXRT_GPIO2_DR (IMXRT_GPIO2_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO2_GDIR (IMXRT_GPIO2_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO2_PSR (IMXRT_GPIO2_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO2_ICR1 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO2_ICR2 (IMXRT_GPIO2_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO2_IMR (IMXRT_GPIO2_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO2_ISR (IMXRT_GPIO2_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO2_EDGE (IMXRT_GPIO2_BASE + IMXRT_GPIO_EDGE_OFFSET) - -#define IMXRT_GPIO3_DR (IMXRT_GPIO3_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO3_GDIR (IMXRT_GPIO3_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO3_PSR (IMXRT_GPIO3_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO3_ICR1 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO3_ICR2 (IMXRT_GPIO3_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO3_IMR (IMXRT_GPIO3_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO3_ISR (IMXRT_GPIO3_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO3_EDGE (IMXRT_GPIO3_BASE + IMXRT_GPIO_EDGE_OFFSET) - -#define IMXRT_GPIO4_DR (IMXRT_GPIO4_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO4_GDIR (IMXRT_GPIO4_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO4_PSR (IMXRT_GPIO4_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO4_ICR1 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO4_ICR2 (IMXRT_GPIO4_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO4_IMR (IMXRT_GPIO4_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO4_ISR (IMXRT_GPIO4_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO4_EDGE (IMXRT_GPIO4_BASE + IMXRT_GPIO_EDGE_OFFSET) - -#define IMXRT_GPIO5_DR (IMXRT_GPIO5_BASE + IMXRT_GPIO_DR_OFFSET) -#define IMXRT_GPIO5_GDIR (IMXRT_GPIO5_BASE + IMXRT_GPIO_GDIR_OFFSET) -#define IMXRT_GPIO5_PSR (IMXRT_GPIO5_BASE + IMXRT_GPIO_PSR_OFFSET) -#define IMXRT_GPIO5_ICR1 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR1_OFFSET) -#define IMXRT_GPIO5_ICR2 (IMXRT_GPIO5_BASE + IMXRT_GPIO_ICR2_OFFSET) -#define IMXRT_GPIO5_IMR (IMXRT_GPIO5_BASE + IMXRT_GPIO_IMR_OFFSET) -#define IMXRT_GPIO5_ISR (IMXRT_GPIO5_BASE + IMXRT_GPIO_ISR_OFFSET) -#define IMXRT_GPIO5_EDGE (IMXRT_GPIO5_BASE + IMXRT_GPIO_EDGE_OFFSET) - /* Register bit definitions *****************************************************************/ /* Most registers are laid out simply with one bit per pin */ diff --git a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h index 6f8c7d92fc..6d3aa45427 100644 --- a/arch/arm/src/imxrt/chip/imxrt_iomuxc.h +++ b/arch/arm/src/imxrt/chip/imxrt_iomuxc.h @@ -3,6 +3,7 @@ * * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -41,1313 +42,19 @@ ************************************************************************************/ #include -#include "chip/imxrt_memorymap.h" + +#if defined(CONFIG_ARCH_FAMILY_IMXRT105x) +# include "chip/imxrt105x_iomuxc.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/imxrt106x_iomuxc.h" +#else +# error Unrecognized i.MX RT architecture +#endif /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* Register offsets *****************************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0_OFFSET 0x0000 /* GPR0 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR1_OFFSET 0x0004 /* GPR1 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR2_OFFSET 0x0008 /* GPR2 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR3_OFFSET 0x000c /* GPR3 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR4_OFFSET 0x0010 /* GPR4 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR5_OFFSET 0x0014 /* GPR5 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR6_OFFSET 0x0018 /* GPR6 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR7_OFFSET 0x001c /* GPR7 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR8_OFFSET 0x0020 /* GPR8 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR9_OFFSET 0x0024 /* GPR9 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR10_OFFSET 0x0028 /* GPR10 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR11_OFFSET 0x002c /* GPR11 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR12_OFFSET 0x0030 /* GPR12 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR13_OFFSET 0x0034 /* GPR13 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR14_OFFSET 0x0038 /* GPR14 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR15_OFFSET 0x003c /* GPR15 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR16_OFFSET 0x0040 /* GPR16 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR17_OFFSET 0x0044 /* GPR17 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR18_OFFSET 0x0048 /* GPR18 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR19_OFFSET 0x004c /* GPR19 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR20_OFFSET 0x0050 /* GPR20 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR21_OFFSET 0x0054 /* GPR21 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR22_OFFSET 0x0058 /* GPR22 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR23_OFFSET 0x005c /* GPR23 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR24_OFFSET 0x0060 /* GPR24 General Purpose Register*/ -#define IMXRT_IOMUXC_GPR_GPR25_OFFSET 0x0064 /* GPR25 General Purpose Register*/ - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET 0x0000 /* SW_MUX_CTL_PAD_WAKEUP SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET 0x0004 /* SW_MUX_CTL_PAD_PMIC_ON_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0008 /* SW_MUX_CTL_PAD_PMIC_STBY_REQ SW MUX Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET 0x000c /* SW_PAD_CTL_PAD_TEST_MODE SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET 0x0010 /* SW_PAD_CTL_PAD_POR_B SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET 0x0014 /* SW_PAD_CTL_PAD_ONOFF SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET 0x0018 /* SW_PAD_CTL_PAD_WAKEUP SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET 0x001c /* SW_PAD_CTL_PAD_PMIC_ON_REQ SW PAD Control Register */ -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET 0x0020 /* SW_PAD_CTL_PAD_PMIC_STBY_REQ SW PAD Control Register */ - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET 0x0000 /* SNVC GPR0 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET 0x0004 /* SNVC GPR1 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET 0x0008 /* SNVC GPR2 General Purpose Register */ -#define IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET 0x000c /* SNVC GPR3 General Purpose Register */ - -/* Pad Mux Registers */ -/* Pad Mux Register Indices (used by software for table lookups) */ - -#define IMXRT_PADMUX_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADMUX_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADMUX_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADMUX_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADMUX_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADMUX_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADMUX_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADMUX_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADMUX_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADMUX_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADMUX_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADMUX_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADMUX_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADMUX_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADMUX_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADMUX_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADMUX_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADMUX_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADMUX_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADMUX_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADMUX_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADMUX_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADMUX_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADMUX_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADMUX_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADMUX_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADMUX_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADMUX_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADMUX_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADMUX_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADMUX_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADMUX_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADMUX_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADMUX_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADMUX_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADMUX_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADMUX_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADMUX_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADMUX_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADMUX_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADMUX_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADMUX_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADMUX_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADMUX_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADMUX_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADMUX_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADMUX_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADMUX_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADMUX_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADMUX_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADMUX_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADMUX_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADMUX_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADMUX_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADMUX_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADMUX_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADMUX_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADMUX_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADMUX_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADMUX_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADMUX_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADMUX_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADMUX_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADMUX_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADMUX_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADMUX_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADMUX_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADMUX_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADMUX_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADMUX_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADMUX_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADMUX_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADMUX_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADMUX_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADMUX_GPIO_B0_00_INDEX 74 -#define IMXRT_PADMUX_GPIO_B0_01_INDEX 75 -#define IMXRT_PADMUX_GPIO_B0_02_INDEX 76 -#define IMXRT_PADMUX_GPIO_B0_03_INDEX 77 -#define IMXRT_PADMUX_GPIO_B0_04_INDEX 78 -#define IMXRT_PADMUX_GPIO_B0_05_INDEX 79 -#define IMXRT_PADMUX_GPIO_B0_06_INDEX 80 -#define IMXRT_PADMUX_GPIO_B0_07_INDEX 81 -#define IMXRT_PADMUX_GPIO_B0_08_INDEX 82 -#define IMXRT_PADMUX_GPIO_B0_09_INDEX 83 -#define IMXRT_PADMUX_GPIO_B0_10_INDEX 84 -#define IMXRT_PADMUX_GPIO_B0_11_INDEX 85 -#define IMXRT_PADMUX_GPIO_B0_12_INDEX 86 -#define IMXRT_PADMUX_GPIO_B0_13_INDEX 87 -#define IMXRT_PADMUX_GPIO_B0_14_INDEX 88 -#define IMXRT_PADMUX_GPIO_B0_15_INDEX 89 -#define IMXRT_PADMUX_GPIO_B1_00_INDEX 90 -#define IMXRT_PADMUX_GPIO_B1_01_INDEX 91 -#define IMXRT_PADMUX_GPIO_B1_02_INDEX 92 -#define IMXRT_PADMUX_GPIO_B1_03_INDEX 93 -#define IMXRT_PADMUX_GPIO_B1_04_INDEX 94 -#define IMXRT_PADMUX_GPIO_B1_05_INDEX 95 -#define IMXRT_PADMUX_GPIO_B1_06_INDEX 96 -#define IMXRT_PADMUX_GPIO_B1_07_INDEX 97 -#define IMXRT_PADMUX_GPIO_B1_08_INDEX 98 -#define IMXRT_PADMUX_GPIO_B1_09_INDEX 99 -#define IMXRT_PADMUX_GPIO_B1_10_INDEX 100 -#define IMXRT_PADMUX_GPIO_B1_11_INDEX 101 -#define IMXRT_PADMUX_GPIO_B1_12_INDEX 102 -#define IMXRT_PADMUX_GPIO_B1_13_INDEX 103 -#define IMXRT_PADMUX_GPIO_B1_14_INDEX 104 -#define IMXRT_PADMUX_GPIO_B1_15_INDEX 105 -#define IMXRT_PADMUX_GPIO_SD_B0_00_INDEX 106 -#define IMXRT_PADMUX_GPIO_SD_B0_01_INDEX 107 -#define IMXRT_PADMUX_GPIO_SD_B0_02_INDEX 108 -#define IMXRT_PADMUX_GPIO_SD_B0_03_INDEX 109 -#define IMXRT_PADMUX_GPIO_SD_B0_04_INDEX 110 -#define IMXRT_PADMUX_GPIO_SD_B0_05_INDEX 111 -#define IMXRT_PADMUX_GPIO_SD_B1_00_INDEX 112 -#define IMXRT_PADMUX_GPIO_SD_B1_01_INDEX 113 -#define IMXRT_PADMUX_GPIO_SD_B1_02_INDEX 114 -#define IMXRT_PADMUX_GPIO_SD_B1_03_INDEX 115 -#define IMXRT_PADMUX_GPIO_SD_B1_04_INDEX 116 -#define IMXRT_PADMUX_GPIO_SD_B1_05_INDEX 117 -#define IMXRT_PADMUX_GPIO_SD_B1_06_INDEX 118 -#define IMXRT_PADMUX_GPIO_SD_B1_07_INDEX 119 -#define IMXRT_PADMUX_GPIO_SD_B1_08_INDEX 120 -#define IMXRT_PADMUX_GPIO_SD_B1_09_INDEX 121 -#define IMXRT_PADMUX_GPIO_SD_B1_10_INDEX 122 -#define IMXRT_PADMUX_GPIO_SD_B1_11_INDEX 123 - -#define IMXRT_PADMUX_WAKEUP_INDEX 124 -#define IMXRT_PADMUX_PMIC_ON_REQ_INDEX 125 -#define IMXRT_PADMUX_PMIC_STBY_REQ_INDEX 126 - -#define IMXRT_PADMUX_NREGISTERS 127 - -/* Pad Mux Register Offsets */ - -#define IMXRT_PADMUX_OFFSET(n) (0x0014 + ((unsigned int)(n) << 2)) -#define IMXRT_PADMUX_OFFSET_SNVS(n) ((unsigned int)(n) << 2) - -#define IMXRT_PADMUX_GPIO_EMC_00_OFFSET 0x0014 -#define IMXRT_PADMUX_GPIO_EMC_01_OFFSET 0x0018 -#define IMXRT_PADMUX_GPIO_EMC_02_OFFSET 0x001c -#define IMXRT_PADMUX_GPIO_EMC_03_OFFSET 0x0020 -#define IMXRT_PADMUX_GPIO_EMC_04_OFFSET 0x0024 -#define IMXRT_PADMUX_GPIO_EMC_05_OFFSET 0x0028 -#define IMXRT_PADMUX_GPIO_EMC_06_OFFSET 0x002c -#define IMXRT_PADMUX_GPIO_EMC_07_OFFSET 0x0030 -#define IMXRT_PADMUX_GPIO_EMC_08_OFFSET 0x0034 -#define IMXRT_PADMUX_GPIO_EMC_09_OFFSET 0x0038 -#define IMXRT_PADMUX_GPIO_EMC_10_OFFSET 0x003c -#define IMXRT_PADMUX_GPIO_EMC_11_OFFSET 0x0040 -#define IMXRT_PADMUX_GPIO_EMC_12_OFFSET 0x0044 -#define IMXRT_PADMUX_GPIO_EMC_13_OFFSET 0x0048 -#define IMXRT_PADMUX_GPIO_EMC_14_OFFSET 0x004c -#define IMXRT_PADMUX_GPIO_EMC_15_OFFSET 0x0050 -#define IMXRT_PADMUX_GPIO_EMC_16_OFFSET 0x0054 -#define IMXRT_PADMUX_GPIO_EMC_17_OFFSET 0x0058 -#define IMXRT_PADMUX_GPIO_EMC_18_OFFSET 0x005c -#define IMXRT_PADMUX_GPIO_EMC_19_OFFSET 0x0060 -#define IMXRT_PADMUX_GPIO_EMC_20_OFFSET 0x0064 -#define IMXRT_PADMUX_GPIO_EMC_21_OFFSET 0x0068 -#define IMXRT_PADMUX_GPIO_EMC_22_OFFSET 0x006c -#define IMXRT_PADMUX_GPIO_EMC_23_OFFSET 0x0070 -#define IMXRT_PADMUX_GPIO_EMC_24_OFFSET 0x0074 -#define IMXRT_PADMUX_GPIO_EMC_25_OFFSET 0x0078 -#define IMXRT_PADMUX_GPIO_EMC_26_OFFSET 0x007c -#define IMXRT_PADMUX_GPIO_EMC_27_OFFSET 0x0080 -#define IMXRT_PADMUX_GPIO_EMC_28_OFFSET 0x0084 -#define IMXRT_PADMUX_GPIO_EMC_29_OFFSET 0x0088 -#define IMXRT_PADMUX_GPIO_EMC_30_OFFSET 0x008c -#define IMXRT_PADMUX_GPIO_EMC_31_OFFSET 0x0090 -#define IMXRT_PADMUX_GPIO_EMC_32_OFFSET 0x0094 -#define IMXRT_PADMUX_GPIO_EMC_33_OFFSET 0x0098 -#define IMXRT_PADMUX_GPIO_EMC_34_OFFSET 0x009c -#define IMXRT_PADMUX_GPIO_EMC_35_OFFSET 0x00a0 -#define IMXRT_PADMUX_GPIO_EMC_36_OFFSET 0x00a4 -#define IMXRT_PADMUX_GPIO_EMC_37_OFFSET 0x00a8 -#define IMXRT_PADMUX_GPIO_EMC_38_OFFSET 0x00ac -#define IMXRT_PADMUX_GPIO_EMC_39_OFFSET 0x00b0 -#define IMXRT_PADMUX_GPIO_EMC_40_OFFSET 0x00b4 -#define IMXRT_PADMUX_GPIO_EMC_41_OFFSET 0x00b8 -#define IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET 0x00bc -#define IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET 0x00c0 -#define IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET 0x00c4 -#define IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET 0x00c8 -#define IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET 0x00cc -#define IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET 0x00d0 -#define IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET 0x00d4 -#define IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET 0x00d8 -#define IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET 0x00dc -#define IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET 0x00e0 -#define IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET 0x00e4 -#define IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET 0x00e8 -#define IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET 0x00ec -#define IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET 0x00f0 -#define IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET 0x00f4 -#define IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET 0x00f8 -#define IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET 0x00fc -#define IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET 0x0100 -#define IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET 0x0104 -#define IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET 0x0108 -#define IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET 0x010c -#define IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET 0x0110 -#define IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET 0x0114 -#define IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET 0x0118 -#define IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET 0x011c -#define IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET 0x0120 -#define IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET 0x0124 -#define IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET 0x0128 -#define IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET 0x012c -#define IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET 0x0130 -#define IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET 0x0134 -#define IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET 0x0138 -#define IMXRT_PADMUX_GPIO_B0_00_OFFSET 0x013c -#define IMXRT_PADMUX_GPIO_B0_01_OFFSET 0x0140 -#define IMXRT_PADMUX_GPIO_B0_02_OFFSET 0x0144 -#define IMXRT_PADMUX_GPIO_B0_03_OFFSET 0x0148 -#define IMXRT_PADMUX_GPIO_B0_04_OFFSET 0x014c -#define IMXRT_PADMUX_GPIO_B0_05_OFFSET 0x0150 -#define IMXRT_PADMUX_GPIO_B0_06_OFFSET 0x0154 -#define IMXRT_PADMUX_GPIO_B0_07_OFFSET 0x0158 -#define IMXRT_PADMUX_GPIO_B0_08_OFFSET 0x015c -#define IMXRT_PADMUX_GPIO_B0_09_OFFSET 0x0160 -#define IMXRT_PADMUX_GPIO_B0_10_OFFSET 0x0164 -#define IMXRT_PADMUX_GPIO_B0_11_OFFSET 0x0168 -#define IMXRT_PADMUX_GPIO_B0_12_OFFSET 0x016c -#define IMXRT_PADMUX_GPIO_B0_13_OFFSET 0x0170 -#define IMXRT_PADMUX_GPIO_B0_14_OFFSET 0x0174 -#define IMXRT_PADMUX_GPIO_B0_15_OFFSET 0x0178 -#define IMXRT_PADMUX_GPIO_B1_00_OFFSET 0x017c -#define IMXRT_PADMUX_GPIO_B1_01_OFFSET 0x0180 -#define IMXRT_PADMUX_GPIO_B1_02_OFFSET 0x0184 -#define IMXRT_PADMUX_GPIO_B1_03_OFFSET 0x0188 -#define IMXRT_PADMUX_GPIO_B1_04_OFFSET 0x018c -#define IMXRT_PADMUX_GPIO_B1_05_OFFSET 0x0190 -#define IMXRT_PADMUX_GPIO_B1_06_OFFSET 0x0194 -#define IMXRT_PADMUX_GPIO_B1_07_OFFSET 0x0198 -#define IMXRT_PADMUX_GPIO_B1_08_OFFSET 0x019c -#define IMXRT_PADMUX_GPIO_B1_09_OFFSET 0x01a0 -#define IMXRT_PADMUX_GPIO_B1_10_OFFSET 0x01a4 -#define IMXRT_PADMUX_GPIO_B1_11_OFFSET 0x01a8 -#define IMXRT_PADMUX_GPIO_B1_12_OFFSET 0x01ac -#define IMXRT_PADMUX_GPIO_B1_13_OFFSET 0x01b0 -#define IMXRT_PADMUX_GPIO_B1_14_OFFSET 0x01b4 -#define IMXRT_PADMUX_GPIO_B1_15_OFFSET 0x01b8 -#define IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET 0x01bc -#define IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET 0x01c0 -#define IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET 0x01c4 -#define IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET 0x01c8 -#define IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET 0x01cc -#define IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET 0x01d0 -#define IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET 0x01d4 -#define IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET 0x01d8 -#define IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET 0x01dc -#define IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET 0x01e0 -#define IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET 0x01e4 -#define IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET 0x01e8 -#define IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET 0x01ec -#define IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET 0x01f0 -#define IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET 0x01f4 -#define IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET 0x01f8 -#define IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET 0x01fc -#define IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET 0x0200 - - -/* Pad Control Registers */ -/* Pad Mux Register Indices (used by software for table lookups) */ - -#define IMXRT_PADCTL_GPIO_EMC_00_INDEX 0 -#define IMXRT_PADCTL_GPIO_EMC_01_INDEX 1 -#define IMXRT_PADCTL_GPIO_EMC_02_INDEX 2 -#define IMXRT_PADCTL_GPIO_EMC_03_INDEX 3 -#define IMXRT_PADCTL_GPIO_EMC_04_INDEX 4 -#define IMXRT_PADCTL_GPIO_EMC_05_INDEX 5 -#define IMXRT_PADCTL_GPIO_EMC_06_INDEX 6 -#define IMXRT_PADCTL_GPIO_EMC_07_INDEX 7 -#define IMXRT_PADCTL_GPIO_EMC_08_INDEX 8 -#define IMXRT_PADCTL_GPIO_EMC_09_INDEX 9 -#define IMXRT_PADCTL_GPIO_EMC_10_INDEX 10 -#define IMXRT_PADCTL_GPIO_EMC_11_INDEX 11 -#define IMXRT_PADCTL_GPIO_EMC_12_INDEX 12 -#define IMXRT_PADCTL_GPIO_EMC_13_INDEX 13 -#define IMXRT_PADCTL_GPIO_EMC_14_INDEX 14 -#define IMXRT_PADCTL_GPIO_EMC_15_INDEX 15 -#define IMXRT_PADCTL_GPIO_EMC_16_INDEX 16 -#define IMXRT_PADCTL_GPIO_EMC_17_INDEX 17 -#define IMXRT_PADCTL_GPIO_EMC_18_INDEX 18 -#define IMXRT_PADCTL_GPIO_EMC_19_INDEX 19 -#define IMXRT_PADCTL_GPIO_EMC_20_INDEX 20 -#define IMXRT_PADCTL_GPIO_EMC_21_INDEX 21 -#define IMXRT_PADCTL_GPIO_EMC_22_INDEX 22 -#define IMXRT_PADCTL_GPIO_EMC_23_INDEX 23 -#define IMXRT_PADCTL_GPIO_EMC_24_INDEX 24 -#define IMXRT_PADCTL_GPIO_EMC_25_INDEX 25 -#define IMXRT_PADCTL_GPIO_EMC_26_INDEX 26 -#define IMXRT_PADCTL_GPIO_EMC_27_INDEX 27 -#define IMXRT_PADCTL_GPIO_EMC_28_INDEX 28 -#define IMXRT_PADCTL_GPIO_EMC_29_INDEX 29 -#define IMXRT_PADCTL_GPIO_EMC_30_INDEX 30 -#define IMXRT_PADCTL_GPIO_EMC_31_INDEX 31 -#define IMXRT_PADCTL_GPIO_EMC_32_INDEX 32 -#define IMXRT_PADCTL_GPIO_EMC_33_INDEX 33 -#define IMXRT_PADCTL_GPIO_EMC_34_INDEX 34 -#define IMXRT_PADCTL_GPIO_EMC_35_INDEX 35 -#define IMXRT_PADCTL_GPIO_EMC_36_INDEX 36 -#define IMXRT_PADCTL_GPIO_EMC_37_INDEX 37 -#define IMXRT_PADCTL_GPIO_EMC_38_INDEX 38 -#define IMXRT_PADCTL_GPIO_EMC_39_INDEX 39 -#define IMXRT_PADCTL_GPIO_EMC_40_INDEX 40 -#define IMXRT_PADCTL_GPIO_EMC_41_INDEX 41 -#define IMXRT_PADCTL_GPIO_AD_B0_00_INDEX 42 -#define IMXRT_PADCTL_GPIO_AD_B0_01_INDEX 43 -#define IMXRT_PADCTL_GPIO_AD_B0_02_INDEX 44 -#define IMXRT_PADCTL_GPIO_AD_B0_03_INDEX 45 -#define IMXRT_PADCTL_GPIO_AD_B0_04_INDEX 46 -#define IMXRT_PADCTL_GPIO_AD_B0_05_INDEX 47 -#define IMXRT_PADCTL_GPIO_AD_B0_06_INDEX 48 -#define IMXRT_PADCTL_GPIO_AD_B0_07_INDEX 49 -#define IMXRT_PADCTL_GPIO_AD_B0_08_INDEX 50 -#define IMXRT_PADCTL_GPIO_AD_B0_09_INDEX 51 -#define IMXRT_PADCTL_GPIO_AD_B0_10_INDEX 52 -#define IMXRT_PADCTL_GPIO_AD_B0_11_INDEX 53 -#define IMXRT_PADCTL_GPIO_AD_B0_12_INDEX 54 -#define IMXRT_PADCTL_GPIO_AD_B0_13_INDEX 55 -#define IMXRT_PADCTL_GPIO_AD_B0_14_INDEX 56 -#define IMXRT_PADCTL_GPIO_AD_B0_15_INDEX 57 -#define IMXRT_PADCTL_GPIO_AD_B1_00_INDEX 58 -#define IMXRT_PADCTL_GPIO_AD_B1_01_INDEX 59 -#define IMXRT_PADCTL_GPIO_AD_B1_02_INDEX 60 -#define IMXRT_PADCTL_GPIO_AD_B1_03_INDEX 61 -#define IMXRT_PADCTL_GPIO_AD_B1_04_INDEX 62 -#define IMXRT_PADCTL_GPIO_AD_B1_05_INDEX 63 -#define IMXRT_PADCTL_GPIO_AD_B1_06_INDEX 64 -#define IMXRT_PADCTL_GPIO_AD_B1_07_INDEX 65 -#define IMXRT_PADCTL_GPIO_AD_B1_08_INDEX 66 -#define IMXRT_PADCTL_GPIO_AD_B1_09_INDEX 67 -#define IMXRT_PADCTL_GPIO_AD_B1_10_INDEX 68 -#define IMXRT_PADCTL_GPIO_AD_B1_11_INDEX 69 -#define IMXRT_PADCTL_GPIO_AD_B1_12_INDEX 70 -#define IMXRT_PADCTL_GPIO_AD_B1_13_INDEX 71 -#define IMXRT_PADCTL_GPIO_AD_B1_14_INDEX 72 -#define IMXRT_PADCTL_GPIO_AD_B1_15_INDEX 73 -#define IMXRT_PADCTL_GPIO_B0_00_INDEX 74 -#define IMXRT_PADCTL_GPIO_B0_01_INDEX 75 -#define IMXRT_PADCTL_GPIO_B0_02_INDEX 76 -#define IMXRT_PADCTL_GPIO_B0_03_INDEX 77 -#define IMXRT_PADCTL_GPIO_B0_04_INDEX 78 -#define IMXRT_PADCTL_GPIO_B0_05_INDEX 79 -#define IMXRT_PADCTL_GPIO_B0_06_INDEX 80 -#define IMXRT_PADCTL_GPIO_B0_07_INDEX 81 -#define IMXRT_PADCTL_GPIO_B0_08_INDEX 82 -#define IMXRT_PADCTL_GPIO_B0_09_INDEX 83 -#define IMXRT_PADCTL_GPIO_B0_10_INDEX 84 -#define IMXRT_PADCTL_GPIO_B0_11_INDEX 85 -#define IMXRT_PADCTL_GPIO_B0_12_INDEX 86 -#define IMXRT_PADCTL_GPIO_B0_13_INDEX 87 -#define IMXRT_PADCTL_GPIO_B0_14_INDEX 88 -#define IMXRT_PADCTL_GPIO_B0_15_INDEX 89 -#define IMXRT_PADCTL_GPIO_B1_00_INDEX 90 -#define IMXRT_PADCTL_GPIO_B1_01_INDEX 91 -#define IMXRT_PADCTL_GPIO_B1_02_INDEX 92 -#define IMXRT_PADCTL_GPIO_B1_03_INDEX 93 -#define IMXRT_PADCTL_GPIO_B1_04_INDEX 94 -#define IMXRT_PADCTL_GPIO_B1_05_INDEX 95 -#define IMXRT_PADCTL_GPIO_B1_06_INDEX 96 -#define IMXRT_PADCTL_GPIO_B1_07_INDEX 97 -#define IMXRT_PADCTL_GPIO_B1_08_INDEX 98 -#define IMXRT_PADCTL_GPIO_B1_09_INDEX 99 -#define IMXRT_PADCTL_GPIO_B1_10_INDEX 100 -#define IMXRT_PADCTL_GPIO_B1_11_INDEX 101 -#define IMXRT_PADCTL_GPIO_B1_12_INDEX 102 -#define IMXRT_PADCTL_GPIO_B1_13_INDEX 103 -#define IMXRT_PADCTL_GPIO_B1_14_INDEX 104 -#define IMXRT_PADCTL_GPIO_B1_15_INDEX 105 -#define IMXRT_PADCTL_GPIO_SD_B0_00_INDEX 106 -#define IMXRT_PADCTL_GPIO_SD_B0_01_INDEX 107 -#define IMXRT_PADCTL_GPIO_SD_B0_02_INDEX 108 -#define IMXRT_PADCTL_GPIO_SD_B0_03_INDEX 109 -#define IMXRT_PADCTL_GPIO_SD_B0_04_INDEX 110 -#define IMXRT_PADCTL_GPIO_SD_B0_05_INDEX 111 -#define IMXRT_PADCTL_GPIO_SD_B1_00_INDEX 112 -#define IMXRT_PADCTL_GPIO_SD_B1_01_INDEX 113 -#define IMXRT_PADCTL_GPIO_SD_B1_02_INDEX 114 -#define IMXRT_PADCTL_GPIO_SD_B1_03_INDEX 115 -#define IMXRT_PADCTL_GPIO_SD_B1_04_INDEX 116 -#define IMXRT_PADCTL_GPIO_SD_B1_05_INDEX 117 -#define IMXRT_PADCTL_GPIO_SD_B1_06_INDEX 118 -#define IMXRT_PADCTL_GPIO_SD_B1_07_INDEX 119 -#define IMXRT_PADCTL_GPIO_SD_B1_08_INDEX 120 -#define IMXRT_PADCTL_GPIO_SD_B1_09_INDEX 121 -#define IMXRT_PADCTL_GPIO_SD_B1_10_INDEX 122 -#define IMXRT_PADCTL_GPIO_SD_B1_11_INDEX 123 - -#define IMXRT_PADCTL_WAKEUP_INDEX 124 -#define IMXRT_PADCTL_PMIC_ON_REQ_INDEX 125 -#define IMXRT_PADCTL_PMIC_STBY_REQ_INDEX 126 - -#define IMXRT_PADCTL_NREGISTERS 127 - -/* Pad Mux Register Offsets */ - -#define IMXRT_PADCTL_OFFSET(n) (0x0204 + ((unsigned int)(n) << 2)) -#define IMXRT_PADCTL_OFFSET_SNVS(n) (0x18 + ((unsigned int)(n) << 2)) - -#define IMXRT_PADCTL_GPIO_EMC_00_OFFSET 0x0204 -#define IMXRT_PADCTL_GPIO_EMC_01_OFFSET 0x0208 -#define IMXRT_PADCTL_GPIO_EMC_02_OFFSET 0x020c -#define IMXRT_PADCTL_GPIO_EMC_03_OFFSET 0x0210 -#define IMXRT_PADCTL_GPIO_EMC_04_OFFSET 0x0214 -#define IMXRT_PADCTL_GPIO_EMC_05_OFFSET 0x0218 -#define IMXRT_PADCTL_GPIO_EMC_06_OFFSET 0x021c -#define IMXRT_PADCTL_GPIO_EMC_07_OFFSET 0x0220 -#define IMXRT_PADCTL_GPIO_EMC_08_OFFSET 0x0224 -#define IMXRT_PADCTL_GPIO_EMC_09_OFFSET 0x0228 -#define IMXRT_PADCTL_GPIO_EMC_10_OFFSET 0x022c -#define IMXRT_PADCTL_GPIO_EMC_11_OFFSET 0x0230 -#define IMXRT_PADCTL_GPIO_EMC_12_OFFSET 0x0234 -#define IMXRT_PADCTL_GPIO_EMC_13_OFFSET 0x0238 -#define IMXRT_PADCTL_GPIO_EMC_14_OFFSET 0x023c -#define IMXRT_PADCTL_GPIO_EMC_15_OFFSET 0x0240 -#define IMXRT_PADCTL_GPIO_EMC_16_OFFSET 0x0244 -#define IMXRT_PADCTL_GPIO_EMC_17_OFFSET 0x0248 -#define IMXRT_PADCTL_GPIO_EMC_18_OFFSET 0x024c -#define IMXRT_PADCTL_GPIO_EMC_19_OFFSET 0x0250 -#define IMXRT_PADCTL_GPIO_EMC_20_OFFSET 0x0254 -#define IMXRT_PADCTL_GPIO_EMC_21_OFFSET 0x0258 -#define IMXRT_PADCTL_GPIO_EMC_22_OFFSET 0x025c -#define IMXRT_PADCTL_GPIO_EMC_23_OFFSET 0x0260 -#define IMXRT_PADCTL_GPIO_EMC_24_OFFSET 0x0264 -#define IMXRT_PADCTL_GPIO_EMC_25_OFFSET 0x0268 -#define IMXRT_PADCTL_GPIO_EMC_26_OFFSET 0x026c -#define IMXRT_PADCTL_GPIO_EMC_27_OFFSET 0x0270 -#define IMXRT_PADCTL_GPIO_EMC_28_OFFSET 0x0274 -#define IMXRT_PADCTL_GPIO_EMC_29_OFFSET 0x0278 -#define IMXRT_PADCTL_GPIO_EMC_30_OFFSET 0x027c -#define IMXRT_PADCTL_GPIO_EMC_31_OFFSET 0x0280 -#define IMXRT_PADCTL_GPIO_EMC_32_OFFSET 0x0284 -#define IMXRT_PADCTL_GPIO_EMC_33_OFFSET 0x0288 -#define IMXRT_PADCTL_GPIO_EMC_34_OFFSET 0x028c -#define IMXRT_PADCTL_GPIO_EMC_35_OFFSET 0x0290 -#define IMXRT_PADCTL_GPIO_EMC_36_OFFSET 0x0294 -#define IMXRT_PADCTL_GPIO_EMC_37_OFFSET 0x0298 -#define IMXRT_PADCTL_GPIO_EMC_38_OFFSET 0x029c -#define IMXRT_PADCTL_GPIO_EMC_39_OFFSET 0x02a0 -#define IMXRT_PADCTL_GPIO_EMC_40_OFFSET 0x02a4 -#define IMXRT_PADCTL_GPIO_EMC_41_OFFSET 0x02a8 -#define IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET 0x02ac -#define IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET 0x02b0 -#define IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET 0x02b4 -#define IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET 0x02b8 -#define IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET 0x02bc -#define IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET 0x02c0 -#define IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET 0x02c4 -#define IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET 0x02c8 -#define IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET 0x02cc -#define IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET 0x02d0 -#define IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET 0x02d4 -#define IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET 0x02d8 -#define IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET 0x02dc -#define IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET 0x02e0 -#define IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET 0x02e4 -#define IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET 0x02e8 -#define IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET 0x02ec -#define IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET 0x02f0 -#define IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET 0x02f4 -#define IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET 0x02f8 -#define IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET 0x02fc -#define IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET 0x0300 -#define IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET 0x0304 -#define IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET 0x0308 -#define IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET 0x030c -#define IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET 0x0310 -#define IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET 0x0314 -#define IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET 0x0318 -#define IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET 0x031c -#define IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET 0x0320 -#define IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET 0x0324 -#define IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET 0x0328 -#define IMXRT_PADCTL_GPIO_B0_00_OFFSET 0x032c -#define IMXRT_PADCTL_GPIO_B0_01_OFFSET 0x0330 -#define IMXRT_PADCTL_GPIO_B0_02_OFFSET 0x0334 -#define IMXRT_PADCTL_GPIO_B0_03_OFFSET 0x0338 -#define IMXRT_PADCTL_GPIO_B0_04_OFFSET 0x033c -#define IMXRT_PADCTL_GPIO_B0_05_OFFSET 0x0340 -#define IMXRT_PADCTL_GPIO_B0_06_OFFSET 0x0344 -#define IMXRT_PADCTL_GPIO_B0_07_OFFSET 0x0348 -#define IMXRT_PADCTL_GPIO_B0_08_OFFSET 0x034c -#define IMXRT_PADCTL_GPIO_B0_09_OFFSET 0x0350 -#define IMXRT_PADCTL_GPIO_B0_10_OFFSET 0x0354 -#define IMXRT_PADCTL_GPIO_B0_11_OFFSET 0x0358 -#define IMXRT_PADCTL_GPIO_B0_12_OFFSET 0x035c -#define IMXRT_PADCTL_GPIO_B0_13_OFFSET 0x0360 -#define IMXRT_PADCTL_GPIO_B0_14_OFFSET 0x0364 -#define IMXRT_PADCTL_GPIO_B0_15_OFFSET 0x0368 -#define IMXRT_PADCTL_GPIO_B1_00_OFFSET 0x036c -#define IMXRT_PADCTL_GPIO_B1_01_OFFSET 0x0370 -#define IMXRT_PADCTL_GPIO_B1_02_OFFSET 0x0374 -#define IMXRT_PADCTL_GPIO_B1_03_OFFSET 0x0378 -#define IMXRT_PADCTL_GPIO_B1_04_OFFSET 0x037c -#define IMXRT_PADCTL_GPIO_B1_05_OFFSET 0x0380 -#define IMXRT_PADCTL_GPIO_B1_06_OFFSET 0x0384 -#define IMXRT_PADCTL_GPIO_B1_07_OFFSET 0x0388 -#define IMXRT_PADCTL_GPIO_B1_08_OFFSET 0x038c -#define IMXRT_PADCTL_GPIO_B1_09_OFFSET 0x0390 -#define IMXRT_PADCTL_GPIO_B1_10_OFFSET 0x0394 -#define IMXRT_PADCTL_GPIO_B1_11_OFFSET 0x0398 -#define IMXRT_PADCTL_GPIO_B1_12_OFFSET 0x039c -#define IMXRT_PADCTL_GPIO_B1_13_OFFSET 0x03a0 -#define IMXRT_PADCTL_GPIO_B1_14_OFFSET 0x03a4 -#define IMXRT_PADCTL_GPIO_B1_15_OFFSET 0x03a8 -#define IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET 0x03ac -#define IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET 0x03b0 -#define IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET 0x03b4 -#define IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET 0x03b8 -#define IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET 0x03bc -#define IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET 0x03c0 -#define IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET 0x03c4 -#define IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET 0x03c8 -#define IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET 0x03cc -#define IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET 0x03d0 -#define IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET 0x03d4 -#define IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET 0x03d8 -#define IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET 0x03dc -#define IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET 0x03e0 -#define IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET 0x03e4 -#define IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET 0x03e8 -#define IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET 0x03ec -#define IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET 0x03f0 - -/* Select Input Register Offsets */ - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET 0x03f4 -#define IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET 0x03f8 -#define IMXRT_INPUT_CCM_PMIC_READY_OFFSET 0x03fc -#define IMXRT_INPUT_CSI_DATA02_OFFSET 0x0400 -#define IMXRT_INPUT_CSI_DATA03_OFFSET 0x0404 -#define IMXRT_INPUT_CSI_DATA04_OFFSET 0x0408 -#define IMXRT_INPUT_CSI_DATA05_OFFSET 0x040c -#define IMXRT_INPUT_CSI_DATA06_OFFSET 0x0410 -#define IMXRT_INPUT_CSI_DATA07_OFFSET 0x0414 -#define IMXRT_INPUT_CSI_DATA08_OFFSET 0x0418 -#define IMXRT_INPUT_CSI_DATA09_OFFSET 0x041c -#define IMXRT_INPUT_CSI_HSYNC_OFFSET 0x0420 -#define IMXRT_INPUT_CSI_PIXCLK_OFFSET 0x0424 -#define IMXRT_INPUT_CSI_VSYNC_OFFSET 0x0428 -#define IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET 0x042c -#define IMXRT_INPUT_ENET_MDIO_OFFSET 0x0430 -#define IMXRT_INPUT_ENET0_RXDATA_OFFSET 0x0434 -#define IMXRT_INPUT_ENET1_RXDATA_OFFSET 0x0438 -#define IMXRT_INPUT_ENET_RXEN_OFFSET 0x043c -#define IMXRT_INPUT_ENET_RXERR_OFFSET 0x0440 -#define IMXRT_INPUT_ENET0_TIMER_OFFSET 0x0444 -#define IMXRT_INPUT_ENET_TXCLK_OFFSET 0x0448 -#define IMXRT_INPUT_FLEXCAN1_RX_OFFSET 0x044c -#define IMXRT_INPUT_FLEXCAN2_RX_OFFSET 0x0450 -#define IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET 0x0454 -#define IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET 0x0458 -#define IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET 0x045c -#define IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET 0x0460 -#define IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET 0x0464 -#define IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET 0x0468 -#define IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET 0x046c -#define IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET 0x0470 -#define IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET 0x0474 -#define IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET 0x0478 -#define IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET 0x047c -#define IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET 0x0480 -#define IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET 0x0484 -#define IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET 0x0488 -#define IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET 0x048c -#define IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET 0x0490 -#define IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET 0x0494 -#define IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET 0x0498 -#define IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET 0x049c -#define IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET 0x04a0 -#define IMXRT_INPUT_FLEXSPIA_DQS_OFFSET 0x04a4 -#define IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET 0x04a8 -#define IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET 0x04ac -#define IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET 0x04b0 -#define IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET 0x04b4 -#define IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET 0x04b8 -#define IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET 0x04bc -#define IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET 0x04c0 -#define IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET 0x04c4 -#define IMXRT_INPUT_FLEXSPIA_SCK_OFFSET 0x04c8 -#define IMXRT_INPUT_LPI2C1_SCL_OFFSET 0x04cc -#define IMXRT_INPUT_LPI2C1_SDA_OFFSET 0x04d0 -#define IMXRT_INPUT_LPI2C2_SCL_OFFSET 0x04d4 -#define IMXRT_INPUT_LPI2C2_SDA_OFFSET 0x04d8 -#define IMXRT_INPUT_LPI2C3_SCL_OFFSET 0x04dc -#define IMXRT_INPUT_LPI2C3_SDA_OFFSET 0x04e0 -#define IMXRT_INPUT_LPI2C4_SCL_OFFSET 0x04e4 -#define IMXRT_INPUT_LPI2C4_SDA_OFFSET 0x04e8 -#define IMXRT_INPUT_LPSPI1_PCS0_OFFSET 0x04ec -#define IMXRT_INPUT_LPSPI1_SCK_OFFSET 0x04f0 -#define IMXRT_INPUT_LPSPI1_SDI_OFFSET 0x04f4 -#define IMXRT_INPUT_LPSPI1_SDO_OFFSET 0x04f8 -#define IMXRT_INPUT_LPSPI2_PCS0_OFFSET 0x04fc -#define IMXRT_INPUT_LPSPI2_SCK_OFFSET 0x0500 -#define IMXRT_INPUT_LPSPI2_SDI_OFFSET 0x0504 -#define IMXRT_INPUT_LPSPI2_SDO_OFFSET 0x0508 -#define IMXRT_INPUT_LPSPI3_PCS0_OFFSET 0x050c -#define IMXRT_INPUT_LPSPI3_SCK_OFFSET 0x0510 -#define IMXRT_INPUT_LPSPI3_SDI_OFFSET 0x0514 -#define IMXRT_INPUT_LPSPI3_SDO_OFFSET 0x0518 -#define IMXRT_INPUT_LPSPI4_PCS0_OFFSET 0x051c -#define IMXRT_INPUT_LPSPI4_SCK_OFFSET 0x0520 -#define IMXRT_INPUT_LPSPI4_SDI_OFFSET 0x0524 -#define IMXRT_INPUT_LPSPI4_SDO_OFFSET 0x0528 -#define IMXRT_INPUT_LPUART2_RX_OFFSET 0x052c -#define IMXRT_INPUT_LPUART2_TX_OFFSET 0x0530 -#define IMXRT_INPUT_LPUART3_CTS_B_OFFSET 0x0534 -#define IMXRT_INPUT_LPUART3_RX_OFFSET 0x0538 -#define IMXRT_INPUT_LPUART3_TX_OFFSET 0x053c -#define IMXRT_INPUT_LPUART4_RX_OFFSET 0x0540 -#define IMXRT_INPUT_LPUART4_TX_OFFSET 0x0544 -#define IMXRT_INPUT_LPUART5_RX_OFFSET 0x0548 -#define IMXRT_INPUT_LPUART5_TX_OFFSET 0x054c -#define IMXRT_INPUT_LPUART6_RX_OFFSET 0x0550 -#define IMXRT_INPUT_LPUART6_TX_OFFSET 0x0554 -#define IMXRT_INPUT_LPUART7_RX_OFFSET 0x0558 -#define IMXRT_INPUT_LPUART7_TX_OFFSET 0x055c -#define IMXRT_INPUT_LPUART8_RX_OFFSET 0x0560 -#define IMXRT_INPUT_LPUART8_TX_OFFSET 0x0564 -#define IMXRT_INPUT_NMI_GLUE_NMI_OFFSET 0x0568 -#define IMXRT_INPUT_QTIMER2_TIMER0_OFFSET 0x056c -#define IMXRT_INPUT_QTIMER2_TIMER1_OFFSET 0x0570 -#define IMXRT_INPUT_QTIMER2_TIMER2_OFFSET 0x0574 -#define IMXRT_INPUT_QTIMER2_TIMER3_OFFSET 0x0578 -#define IMXRT_INPUT_QTIMER3_TIMER0_OFFSET 0x057c -#define IMXRT_INPUT_QTIMER3_TIMER1_OFFSET 0x0580 -#define IMXRT_INPUT_QTIMER3_TIMER2_OFFSET 0x0584 -#define IMXRT_INPUT_QTIMER3_TIMER3_OFFSET 0x0588 -#define IMXRT_INPUT_SAI1_MCLK2_OFFSET 0x058c -#define IMXRT_INPUT_SAI1_RX_BCLK_OFFSET 0x0590 -#define IMXRT_INPUT_SAI1_RX_DATA0_OFFSET 0x0594 -#define IMXRT_INPUT_SAI1_RX_DATA1_OFFSET 0x0598 -#define IMXRT_INPUT_SAI1_RX_DATA2_OFFSET 0x059c -#define IMXRT_INPUT_SAI1_RX_DATA3_OFFSET 0x05a0 -#define IMXRT_INPUT_SAI1_RX_SYNC_OFFSET 0x05a4 -#define IMXRT_INPUT_SAI1_TX_BCLK_OFFSET 0x05a8 -#define IMXRT_INPUT_SAI1_TX_SYNC_OFFSET 0x05ac -#define IMXRT_INPUT_SAI2_MCLK2_OFFSET 0x05b0 -#define IMXRT_INPUT_SAI2_RX_BCLK_OFFSET 0x05b4 -#define IMXRT_INPUT_SAI2_RX_DATA0_OFFSET 0x05b8 -#define IMXRT_INPUT_SAI2_RX_SYNC_OFFSET 0x05bc -#define IMXRT_INPUT_SAI2_TX_BCLK_OFFSET 0x05c0 -#define IMXRT_INPUT_SAI2_TX_SYNC_OFFSET 0x05c4 -#define IMXRT_INPUT_SPDIF_IN_OFFSET 0x05c8 -#define IMXRT_INPUT_USB_OTG2_OC_OFFSET 0x05cc -#define IMXRT_INPUT_USB_OTG1_OC_OFFSET 0x05d0 -#define IMXRT_INPUT_USDHC1_CD_B_OFFSET 0x05d4 -#define IMXRT_INPUT_USDHC1_WP_OFFSET 0x05d8 -#define IMXRT_INPUT_USDHC2_CLK_OFFSET 0x05dc -#define IMXRT_INPUT_USDHC2_CD_B_OFFSET 0x05e0 -#define IMXRT_INPUT_USDHC2_CMD_OFFSET 0x05e4 -#define IMXRT_INPUT_USDHC2_DATA0_OFFSET 0x05e8 -#define IMXRT_INPUT_USDHC2_DATA1_OFFSET 0x05ec -#define IMXRT_INPUT_USDHC2_DATA2_OFFSET 0x05f0 -#define IMXRT_INPUT_USDHC2_DATA3_OFFSET 0x05f4 -#define IMXRT_INPUT_USDHC2_DATA4_OFFSET 0x05f8 -#define IMXRT_INPUT_USDHC2_DATA5_OFFSET 0x05fc -#define IMXRT_INPUT_USDHC2_DATA6_OFFSET 0x0600 -#define IMXRT_INPUT_USDHC2_DATA7_OFFSET 0x0604 -#define IMXRT_INPUT_USDHC2_WP_OFFSET 0x0608 -#define IMXRT_INPUT_XBAR1_IN02_OFFSET 0x060c -#define IMXRT_INPUT_XBAR1_IN03_OFFSET 0x0610 -#define IMXRT_INPUT_XBAR1_IN04_OFFSET 0x0614 -#define IMXRT_INPUT_XBAR1_IN05_OFFSET 0x0618 -#define IMXRT_INPUT_XBAR1_IN06_OFFSET 0x061c -#define IMXRT_INPUT_XBAR1_IN07_OFFSET 0x0620 -#define IMXRT_INPUT_XBAR1_IN08_OFFSET 0x0624 -#define IMXRT_INPUT_XBAR1_IN09_OFFSET 0x0628 -#define IMXRT_INPUT_XBAR1_IN17_OFFSET 0x062c -#define IMXRT_INPUT_XBAR1_IN18_OFFSET 0x0630 -#define IMXRT_INPUT_XBAR1_IN20_OFFSET 0x0634 -#define IMXRT_INPUT_XBAR1_IN22_OFFSET 0x0638 -#define IMXRT_INPUT_XBAR1_IN23_OFFSET 0x063c -#define IMXRT_INPUT_XBAR1_IN24_OFFSET 0x0640 -#define IMXRT_INPUT_XBAR1_IN14_OFFSET 0x0644 -#define IMXRT_INPUT_XBAR1_IN15_OFFSET 0x0648 -#define IMXRT_INPUT_XBAR1_IN16_OFFSET 0x064c -#define IMXRT_INPUT_XBAR1_IN25_OFFSET 0x0650 -#define IMXRT_INPUT_XBAR1_IN19_OFFSET 0x0654 -#define IMXRT_INPUT_XBAR1_IN21_OFFSET 0x0658 - -/* Register addresses ***************************************************************/ - -#define IMXRT_IOMUXC_GPR_GPR0 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR1 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR2 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR3 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR3_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR4 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR4_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR5 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR5_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR6 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR6_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR7 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR7_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR8 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR8_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR9 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR9_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR10 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR10_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR11 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR11_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR12 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR12_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR13 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR13_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR14 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR14_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR15 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR15_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR16 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR16_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR17 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR17_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR18 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR18_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR19 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR19_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR20 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR20_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR21 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR21_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR22 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR22_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR23 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR23_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR24 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR24_OFFSET) -#define IMXRT_IOMUXC_GPR_GPR25 (IMXRT_IOMUXCGPR_BASE + IMXRT_IOMUXC_GPR_GPR25_OFFSET) - -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_OFFSET) -#define IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ (IMXRT_IOMUXCSNVS_BASE + IMXRT_IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_OFFSET) - -#define IMXRT_IOMUXC_SNVS_GPR_GPR0 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR0_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR1 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR1_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR2 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR2_OFFSET) -#define IMXRT_IOMUXC_SNVS_GPR_GPR3 (IMXRT_IOMUXCSNVSGPR_BASE + IMXRT_IOMUXC_SNVS_GPR_GPR3_OFFSET) - -/* Pad Mux Registers */ - -#define IMXRT_PADMUX_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_OFFSET(n)) -#define IMXRT_PADMUX_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADMUX_OFFSET_SNVS(n)) - -#define IMXRT_PADMUX_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_00_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_01_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_02_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_03_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_04_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_05_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_06_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_07_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_08_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_09_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_10_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_11_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_12_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_13_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_14_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_15_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_16_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_17_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_18_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_19_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_20_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_21_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_22_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_23_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_24_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_25_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_26_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_27_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_28_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_29_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_30_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_31_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_32_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_33_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_34_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_35_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_36_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_37_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_38_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_39_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_40_OFFSET) -#define IMXRT_PADMUX_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_EMC_41_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_06_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_07_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_08_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_09_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_10_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_11_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_12_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_13_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_14_OFFSET) -#define IMXRT_PADMUX_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B0_15_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_11_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_12_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_13_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_14_OFFSET) -#define IMXRT_PADMUX_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_B1_15_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADMUX_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADMUX_GPIO_SD_B1_11_OFFSET) - -/* Pad Control Registers */ - -#define IMXRT_PADCTL_ADDRESS(n) (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_OFFSET(n)) -#define IMXRT_PADCTL_ADDRESS_SNVS(n) (IMXRT_IOMUXCSNVS_BASE + IMXRT_PADCTL_OFFSET_SNVS(n)) - -#define IMXRT_PADCTL_GPIO_EMC_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_00_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_01_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_02_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_03_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_04_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_05_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_06_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_07_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_08_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_09_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_10_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_11_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_12_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_13_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_14_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_15_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_16 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_16_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_17 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_17_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_18 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_18_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_19 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_19_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_20 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_20_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_21 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_21_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_22 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_22_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_23 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_23_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_24 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_24_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_25 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_25_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_26 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_26_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_27 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_27_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_28 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_28_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_29 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_29_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_30 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_30_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_31 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_31_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_32 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_32_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_33 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_33_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_34 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_34_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_35 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_35_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_36 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_36_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_37 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_37_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_38 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_38_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_39 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_39_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_40 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_40_OFFSET) -#define IMXRT_PADCTL_GPIO_EMC_41 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_EMC_41_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_AD_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_AD_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_06_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_07_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_08_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_09_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_10_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_11_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_12_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_13_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_14_OFFSET) -#define IMXRT_PADCTL_GPIO_B0_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B0_15_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_11_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_12 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_12_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_13 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_13_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_14 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_14_OFFSET) -#define IMXRT_PADCTL_GPIO_B1_15 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_B1_15_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B0_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B0_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_00 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_00_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_01 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_01_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_02 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_02_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_03 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_03_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_04 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_04_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_05 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_05_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_06 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_06_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_07 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_07_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_08 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_08_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_09 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_09_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_10 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_10_OFFSET) -#define IMXRT_PADCTL_GPIO_SD_B1_11 (IMXRT_IOMUXC_BASE + IMXRT_PADCTL_GPIO_SD_B1_11_OFFSET) - -/* Select Input Registers */ - -#define IMXRT_INPUT_ANATOP_USB_OTG1_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG1_ID_OFFSET) -#define IMXRT_INPUT_ANATOP_USB_OTG2_ID (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ANATOP_USB_OTG2_ID_OFFSET) -#define IMXRT_INPUT_CCM_PMIC_READY (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CCM_PMIC_READY_OFFSET) -#define IMXRT_INPUT_CSI_DATA02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA02_OFFSET) -#define IMXRT_INPUT_CSI_DATA03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA03_OFFSET) -#define IMXRT_INPUT_CSI_DATA04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA04_OFFSET) -#define IMXRT_INPUT_CSI_DATA05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA05_OFFSET) -#define IMXRT_INPUT_CSI_DATA06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA06_OFFSET) -#define IMXRT_INPUT_CSI_DATA07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA07_OFFSET) -#define IMXRT_INPUT_CSI_DATA08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA08_OFFSET) -#define IMXRT_INPUT_CSI_DATA09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_DATA09_OFFSET) -#define IMXRT_INPUT_CSI_HSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_HSYNC_OFFSET) -#define IMXRT_INPUT_CSI_PIXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_PIXCLK_OFFSET) -#define IMXRT_INPUT_CSI_VSYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_CSI_VSYNC_OFFSET) -#define IMXRT_INPUT_ENET_IPG_CLK_RMII (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_IPG_CLK_RMII_OFFSET) -#define IMXRT_INPUT_ENET_MDIO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_MDIO_OFFSET) -#define IMXRT_INPUT_ENET0_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET1_RXDATA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET1_RXDATA_OFFSET) -#define IMXRT_INPUT_ENET_RXEN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXEN_OFFSET) -#define IMXRT_INPUT_ENET_RXERR (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_RXERR_OFFSET) -#define IMXRT_INPUT_ENET0_TIMER (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET0_TIMER_OFFSET) -#define IMXRT_INPUT_ENET_TXCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_ENET_TXCLK_OFFSET) -#define IMXRT_INPUT_FLEXCAN1_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN1_RX_OFFSET) -#define IMXRT_INPUT_FLEXCAN2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXCAN2_RX_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM1_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM1_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB3_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB0_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB1_OFFSET) -#define IMXRT_INPUT_FLEXPWM2_PWMB2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM2_PWMB2_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA0_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA1_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA2_OFFSET) -#define IMXRT_INPUT_FLEXPWM4_PWMA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXPWM4_PWMA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DQS (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DQS_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA0_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA1_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA2_OFFSET) -#define IMXRT_INPUT_FLEXSPIB_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIB_DATA3_OFFSET) -#define IMXRT_INPUT_FLEXSPIA_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_FLEXSPIA_SCK_OFFSET) -#define IMXRT_INPUT_LPI2C1_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C1_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C1_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C2_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C2_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C2_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C3_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C3_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C3_SDA_OFFSET) -#define IMXRT_INPUT_LPI2C4_SCL (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SCL_OFFSET) -#define IMXRT_INPUT_LPI2C4_SDA (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPI2C4_SDA_OFFSET) -#define IMXRT_INPUT_LPSPI1_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI1_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI1_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI1_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI2_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI2_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI2_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI2_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI3_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI3_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI3_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI3_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI3_SDO_OFFSET) -#define IMXRT_INPUT_LPSPI4_PCS0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_PCS0_OFFSET) -#define IMXRT_INPUT_LPSPI4_SCK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SCK_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDI_OFFSET) -#define IMXRT_INPUT_LPSPI4_SDO (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPSPI4_SDO_OFFSET) -#define IMXRT_INPUT_LPUART2_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_RX_OFFSET) -#define IMXRT_INPUT_LPUART2_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART2_TX_OFFSET) -#define IMXRT_INPUT_LPUART3_CTS_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_CTS_B_OFFSET) -#define IMXRT_INPUT_LPUART3_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_RX_OFFSET) -#define IMXRT_INPUT_LPUART3_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART3_TX_OFFSET) -#define IMXRT_INPUT_LPUART4_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_RX_OFFSET) -#define IMXRT_INPUT_LPUART4_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART4_TX_OFFSET) -#define IMXRT_INPUT_LPUART5_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_RX_OFFSET) -#define IMXRT_INPUT_LPUART5_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART5_TX_OFFSET) -#define IMXRT_INPUT_LPUART6_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_RX_OFFSET) -#define IMXRT_INPUT_LPUART6_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART6_TX_OFFSET) -#define IMXRT_INPUT_LPUART7_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_RX_OFFSET) -#define IMXRT_INPUT_LPUART7_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART7_TX_OFFSET) -#define IMXRT_INPUT_LPUART8_RX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_RX_OFFSET) -#define IMXRT_INPUT_LPUART8_TX (IMXRT_IOMUXC_BASE + IMXRT_INPUT_LPUART8_TX_OFFSET) -#define IMXRT_INPUT_NMI_GLUE_NMI (IMXRT_IOMUXC_BASE + IMXRT_INPUT_NMI_GLUE_NMI_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER2_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER2_TIMER3_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER0_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER1_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER2_OFFSET) -#define IMXRT_INPUT_QTIMER3_TIMER3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_QTIMER3_TIMER3_OFFSET) -#define IMXRT_INPUT_SAI1_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA1_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA2_OFFSET) -#define IMXRT_INPUT_SAI1_RX_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_DATA3_OFFSET) -#define IMXRT_INPUT_SAI1_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI1_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI1_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI1_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_MCLK2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_MCLK2_OFFSET) -#define IMXRT_INPUT_SAI2_RX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_RX_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_DATA0_OFFSET) -#define IMXRT_INPUT_SAI2_RX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_RX_SYNC_OFFSET) -#define IMXRT_INPUT_SAI2_TX_BCLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_BCLK_OFFSET) -#define IMXRT_INPUT_SAI2_TX_SYNC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SAI2_TX_SYNC_OFFSET) -#define IMXRT_INPUT_SPDIF_IN (IMXRT_IOMUXC_BASE + IMXRT_INPUT_SPDIF_IN_OFFSET) -#define IMXRT_INPUT_USB_OTG2_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG2_OC_OFFSET) -#define IMXRT_INPUT_USB_OTG1_OC (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USB_OTG1_OC_OFFSET) -#define IMXRT_INPUT_USDHC1_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC1_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC1_WP_OFFSET) -#define IMXRT_INPUT_USDHC2_CLK (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CLK_OFFSET) -#define IMXRT_INPUT_USDHC2_CD_B (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CD_B_OFFSET) -#define IMXRT_INPUT_USDHC2_CMD (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_CMD_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA0 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA0_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA1 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA1_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA2 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA2_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA3 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA3_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA4 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA4_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA5 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA5_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA6 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA6_OFFSET) -#define IMXRT_INPUT_USDHC2_DATA7 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_DATA7_OFFSET) -#define IMXRT_INPUT_USDHC2_WP (IMXRT_IOMUXC_BASE + IMXRT_INPUT_USDHC2_WP_OFFSET) -#define IMXRT_INPUT_XBAR1_IN02 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN02_OFFSET) -#define IMXRT_INPUT_XBAR1_IN03 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN03_OFFSET) -#define IMXRT_INPUT_XBAR1_IN04 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN04_OFFSET) -#define IMXRT_INPUT_XBAR1_IN05 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) -#define IMXRT_INPUT_XBAR1_IN06 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN05_OFFSET) -#define IMXRT_INPUT_XBAR1_IN07 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN07_OFFSET) -#define IMXRT_INPUT_XBAR1_IN08 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN08_OFFSET) -#define IMXRT_INPUT_XBAR1_IN09 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN09_OFFSET) -#define IMXRT_INPUT_XBAR1_IN17 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN17_OFFSET) -#define IMXRT_INPUT_XBAR1_IN18 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN18_OFFSET) -#define IMXRT_INPUT_XBAR1_IN20 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN20_OFFSET) -#define IMXRT_INPUT_XBAR1_IN22 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN22_OFFSET) -#define IMXRT_INPUT_XBAR1_IN23 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN23_OFFSET) -#define IMXRT_INPUT_XBAR1_IN24 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN24_OFFSET) -#define IMXRT_INPUT_XBAR1_IN14 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN14_OFFSET) -#define IMXRT_INPUT_XBAR1_IN15 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN15_OFFSET) -#define IMXRT_INPUT_XBAR1_IN16 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN16_OFFSET) -#define IMXRT_INPUT_XBAR1_IN25 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN25_OFFSET) -#define IMXRT_INPUT_XBAR1_IN19 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN19_OFFSET) -#define IMXRT_INPUT_XBAR1_IN21 (IMXRT_IOMUXC_BASE + IMXRT_INPUT_XBAR1_IN21_OFFSET) - -/* Register bit definitions *********************************************************/ - -/* General Purpose Register 1 (GPR1) */ - -#define GPR_GPR1_SAI1_MCLK1_SEL_SHIFT (0) -#define GPR_GPR1_SAI1_MCLK1_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK1_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK1_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK2_SEL_SHIFT (3) -#define GPR_GPR1_SAI1_MCLK2_SEL_MASK (7 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI1_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI2_CLK_ROOT (1 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_CCM_SSI3_CLK_ROOT (2 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI1_IPG_CLK_SAI_MCLK2 (3 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI2_IPG_CLK_SAI_MCLK2 (4 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK2_SEL_IOMUX_SAI3_IPG_CLK_SAI_MCLK2 (5 << GPR_GPR1_SAI1_MCLK2_SEL_SHIFT) -#define GPR_GPR1_SAI1_MCLK3_SEL_SHIFT (6) -#define GPR_GPR1_SAI1_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI1_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI1_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (8) -#define GPR_GPR1_SAI2_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI2_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI2_MCLK3_SEL_SHIFT) -#define GPR_GPR1_SAI3_MCLK3_SEL_SHIFT (10) -#define GPR_GPR1_SAI3_MCLK3_SEL_MASK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_CCM_SPDIF0_CLK_ROOT (0 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_IOMUX_SPDIF_TX_CLK2 (1 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_SRCLK (2 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -# define GPR_GPR1_SAI3_MCLK3_SEL_SPDIF_SPDIF_OUTCLOCK (3 << GPR_GPR1_SAI3_MCLK3_SEL_SHIFT) -#define GPR_GPR1_GINT (1 << 12) -#define GPR_GPR1_ENET1_CLK_SEL (1 << 13) -#define GPR_GPR1_USB_EXP_MODE_EN (1 << 15) -#define GPR_GPR1_ENET1_TX_CLK_OUT_EN (1 << 17) -#define GPR_GPR1_SAI1_MCLK_DIR_IN (0 << 19) -#define GPR_GPR1_SAI1_MCLK_DIR_OUT (1 << 19) -#define GPR_GPR1_SAI2_MCLK_DIR_IN (0 << 20) -#define GPR_GPR1_SAI2_MCLK_DIR_OUT (1 << 20) -#define GPR_GPR1_SAI3_MCLK_DIR_IN (0 << 21) -#define GPR_GPR1_SAI3_MCLK_DIR_OUT (1 << 21) -#define GPR_GPR1_EXC_MON_OKAY (0 << 22) -#define GPR_GPR1_EXC_MON_SLVERR (1 << 22) -#define GPR_GPR1_ENET_IMG_CLS_S_EN (1 << 23) -#define GPR_GPR1_CM7_FORCE_HCLK_EN (1 << 31) - -/* General Purpose Register 2 (GPR2) */ - -#define GPR_GPR2_L2_MEM_POWERSAVE_EN (1 << 12) -#define GPR_GPR2_L2_MEM_FORCE_DEEPSLEEP (1 << 14) -#define GPR_GPR2_MQS_CLK_DIV_SHIFT (16) -#define GPR_GPR2_MQS_CLK_DIV_MASK (255 << GPR_GPR2_MQS_CLK_DIV_SHIFT) -# define GPR_GPR2_MQS_CLK_DIV(n) ((n - 1) << GPR_GPR2_MQS_CLK_DIV_SHIFT) -#define GPR_GPR2_MQS_SW_RST_EN (1 << 24) -#define GPR_GPR2_MQS_EN (1 << 25) -#define GPR_GPR2_MQS_OVERSAMPLE32 (0 << 26) -#define GPR_GPR2_MQS_OVERSAMPLE64 (1 << 26) -#define GPR_GPR2_QTIM1_TMR_RESET (1 << 28) -#define GPR_GPR2_QTIM2_TMR_RESET (1 << 29) -#define GPR_GPR2_QTIM3_TMR_RESET (1 << 30) -#define GPR_GPR2_QTIM4_TMR_RESET (1 << 31) - -/* General Purpose Register 3 (GPR3) */ - -#define GPR_GPR3_OCRAM_CTL_SHIFT (0) -#define GPR_GPR3_OCRAM_CTL_MASK (15 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_DATA_PIPELINE_EN (1 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_READ_ADDR_PIPELINE_EN (2 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_DATA_PIPELINE_EN (4 << GPR_GPR3_OCRAM_CTL_SHIFT) -# define GPR_GPR3_OCRAM_CTL_WRITE_ADDR_PIPELINE_EN (8 << GPR_GPR3_OCRAM_CTL_SHIFT) -#define GPR_GPR3_DCP_KEY_SEL_128 (0 << 4) -#define GPR_GPR3_DCP_KEY_SEL_256 (1 << 4) - -/* General Purpose Register 4 (GPR4) */ -#define GPR_GRP4_EDMA_STOP_REQ (1 << 0) -#define GPR_GPR4_CAN1_STOP_REQ (1 << 1) -#define GPR_GPR4_CAN2_STOP_REQ (1 << 2) -#define GPR_GPR4_TRNG_STOP_REQ (1 << 3) -#define GPR_GPR4_ENET_STOP_REQ (1 << 4) -#define GPR_GPR4_SAI1_STOP_REQ (1 << 5) -#define GPR_GPR4_SAI2_STOP_REQ (1 << 6) -#define GPR_GPR4_SAI3_STOP_REQ (1 << 7) -#define GPR_GPR4_SEMC_STOP_REQ (1 << 9) -#define GPR_GPR4_PIT_STOP_REQ (1 << 10) -#define GPR_GPR4_FLEXSPI_STOP_REQ (1 << 11) -#define GPR_GPR4_FLEXIO1_STOP_REQ (1 << 12) -#define GPR_GPR4_FLEXIO2_STOP_REQ (1 << 13) - -/* General Purpose Register 5 (GPR5) */ - -#define GPR_GPR5_WDOG1_MASK (1 << 6) -#define GPR_GPR5_WDOG2_MASK (1 << 7) -#define GPR_GPR5_GPT2_CAPIN1_SEL_PAD (0 << 23) -#define GPR_GPR5_GPT2_CAPIN1_SEL_ENET1 (1 << 23) -#define GPR_GPR5_GPT2_CAPIN2_SEL_PAD (0 << 24) -#define GPR_GPR5_GPT2_CAPIN2_SEL_ENET2 (1 << 24) -#define GPR_GPR5_ENET_EVENT3IN_SEL_PAD (0 << 25) -#define GPR_GPR5_ENET_EVENT3IN_SEL_ENET2 (1 << 25) -#define GPR_GPR5_VREF_1M_CLK_GPT1_IPG_PERCLK (0 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT1_ANATOP (1 << 28) -#define GPR_GPR5_VREF_1M_CLK_GPT2_IPG_PERCLK (0 << 29) -#define GPR_GPR5_VREF_1M_CLK_GPT2_ANATOP (1 << 29) - /* Pad Mux Registers */ #define PADMUX_MUXMODE_SHIFT (0) /* Bit 0-2: Software Input On Field */ diff --git a/arch/arm/src/imxrt/chip/imxrt_memorymap.h b/arch/arm/src/imxrt/chip/imxrt_memorymap.h index b528d9beb9..e6352da0a1 100644 --- a/arch/arm/src/imxrt/chip/imxrt_memorymap.h +++ b/arch/arm/src/imxrt/chip/imxrt_memorymap.h @@ -44,6 +44,8 @@ #if defined(CONFIG_ARCH_FAMILY_IMXRT105x) # include "chip/imxrt105x_memorymap.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/imxrt106x_memorymap.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/chip/imxrt_pinmux.h b/arch/arm/src/imxrt/chip/imxrt_pinmux.h index 71a64133c8..c92b3d8cb8 100644 --- a/arch/arm/src/imxrt/chip/imxrt_pinmux.h +++ b/arch/arm/src/imxrt/chip/imxrt_pinmux.h @@ -2,7 +2,8 @@ * arch/arm/src/imxrt/chip/imxrt_pinmux.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -44,6 +45,8 @@ #if defined(CONFIG_ARCH_FAMILY_IMXRT105x) # include "chip/imxrt105x_pinmux.h" +#elif defined(CONFIG_ARCH_FAMILY_IMXRT106x) +# include "chip/imxrt106x_pinmux.h" #else # error Unrecognized i.MX RT architecture #endif diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index a320c51465..8404f2d58c 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -96,13 +96,19 @@ * banks. This logic assumes that there is at most one of each (or at least * only one contiguous block of addresses for each). This would need to * be exceed considerably to support multiple SDRAM or SRAM memory regions. + * + * SOC with 512KiB + * + * IMXRT_DTCM_BASE 0x20000000 512KB DTCM + * 0x20080000 512KB DTCM Reserved + * 0x20100000 1MB Reserved + * IMXRT_OCRAM_BASE 0x20200000 512KB OCRAM + * + * SOC with 1MiB + * IMXRT_OCRAM2_BASE 0x20200000 512KB OCRAM2 + * IMXRT_OCRAM_BASE 0x20280000 512KB OCRAM FlexRAM */ -#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */ - /* 0x20080000 512KB DTCM Reserved */ - /* 0x20100000 1MB Reserved */ -#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */ - /* There there then several memory configurations with a one primary memory * region and up to two additional memory regions which may be OCRAM, * external SDRAM, or external SRAM. @@ -114,10 +120,21 @@ /* REVISIT: Assume that if OCRAM is the primary RAM, then DTCM and ITCM are * not being used. + * When configured DTCM and ITCM consume OCRAM from the address space + * labeled IMXRT_OCRAM_BASE that uses the FlexRAM controller to allocate + * the function of OCRAM. + * + * The 1 MB version of the SOC have a second 512Kib of OCRAM that can not + * be consumed by the DTCM or ITCM. */ +#if defined(IMXRT_OCRAM2_BASE) +# define _IMXRT_OCRAM_BASE IMXRT_OCRAM2_BASE +#else +# define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE +#endif #if defined(CONFIG_IMXRT_OCRAM_PRIMARY) -# define PRIMARY_RAM_START IMXRT_OCRAM_BASE /* CONFIG_RAM_START */ +# define PRIMARY_RAM_START _IMXRT_OCRAM_BASE /* CONFIG_RAM_START */ # define PRIMARY_RAM_SIZE IMXRT_OCRAM_SIZE /* CONFIG_RAM_SIZE */ # define IMXRT_OCRAM_ASSIGNED 1 #elif defined(CONFIG_IMXRT_SDRAM_PRIMARY) @@ -137,12 +154,16 @@ /* REVISIT: I am not sure how this works. But I am assuming that if DTCM * is enabled, then ITCM is not and we can just use the DTCM base address to * access OCRAM. + * + * The FlexRAM controller manages the allocation of DTCM and ITCM from the + * OCRAM. The amount allocated it 2^n KiB where n is 2-9 and is configured in + * the GPR register space. */ #ifdef CONFIG_IMXRT_DTCM # define IMXRT_OCRAM_START IMXRT_DTCM_BASE #else -# define IMXRT_OCRAM_START IMXRT_OCRAM_BASE +# define IMXRT_OCRAM_START _IMXRT_OCRAM_BASE #endif #if CONFIG_MM_REGIONS > 1 diff --git a/arch/arm/src/imxrt/imxrt_clockconfig.c b/arch/arm/src/imxrt/imxrt_clockconfig.c index 9ef734652d..a3a9852ac5 100644 --- a/arch/arm/src/imxrt/imxrt_clockconfig.c +++ b/arch/arm/src/imxrt/imxrt_clockconfig.c @@ -46,7 +46,7 @@ #include "chip/imxrt_ccm.h" #include "chip/imxrt_dcdc.h" #include "imxrt_clockconfig.h" -#include "chip/imxrt105x_memorymap.h" +#include "chip/imxrt_memorymap.h" /**************************************************************************** * Public Functions diff --git a/arch/arm/src/imxrt/imxrt_gpio.c b/arch/arm/src/imxrt/imxrt_gpio.c index e88dcf302b..8c4d7d9022 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.c +++ b/arch/arm/src/imxrt/imxrt_gpio.c @@ -263,6 +263,12 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = g_gpio3_padmux, /* GPIO3 */ g_gpio4_padmux, /* GPIO4 */ g_gpio5_padmux, /* GPIO5 */ +#if IMXRT_GPIO_NPORTS > 5 + g_gpio1_padmux, /* GPIO6 */ + g_gpio2_padmux, /* GPIO7 */ + g_gpio3_padmux, /* GPIO8 */ + g_gpio4_padmux, /* GPIO9 */ +#endif NULL /* End of list */ }; @@ -270,7 +276,7 @@ static FAR const uint8_t *g_gpio_padmux[IMXRT_GPIO_NPORTS + 1] = * Public Data ************************************************************************************/ -/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */ +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base addresses */ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = { @@ -287,6 +293,18 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = #if IMXRT_GPIO_NPORTS > 4 , IMXRT_GPIO5_BASE #endif +#if IMXRT_GPIO_NPORTS > 5 + , IMXRT_GPIO6_BASE +#endif +#if IMXRT_GPIO_NPORTS > 6 + , IMXRT_GPIO7_BASE +#endif +#if IMXRT_GPIO_NPORTS > 7 + , IMXRT_GPIO8_BASE +#endif +#if IMXRT_GPIO_NPORTS > 8 + , IMXRT_GPIO9_BASE +#endif }; /**************************************************************************** @@ -299,6 +317,12 @@ uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS] = static uintptr_t imxrt_padmux_address(unsigned int index) { +#if defined(IMXRT_PAD1MUX_OFFSET) + if (index >= IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX) + { + return (IMXRT_PAD1MUX_OFFSET(index - IMXRT_PADMUX_GPIO_SPI_B0_00_INDEX)); + } +#endif if (index >= IMXRT_PADMUX_WAKEUP_INDEX) { return (IMXRT_PADMUX_ADDRESS_SNVS(index - IMXRT_PADMUX_WAKEUP_INDEX)); @@ -313,6 +337,12 @@ static uintptr_t imxrt_padmux_address(unsigned int index) static uintptr_t imxrt_padctl_address(unsigned int index) { +#if defined(IMXRT_PAD1CTL_OFFSET) + if (index >= IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX) + { + return (IMXRT_PAD1CTL_OFFSET(index - IMXRT_PADCTL_GPIO_SPI_B0_00_INDEX)); + } +#endif if (index >= IMXRT_PADCTL_WAKEUP_INDEX) { return (IMXRT_PADCTL_ADDRESS_SNVS(index - IMXRT_PADCTL_WAKEUP_INDEX)); @@ -378,6 +408,51 @@ static inline bool imxrt_gpio_getinput(int port, int pin) return ((regval & GPIO_PIN(pin)) != 0); } +/**************************************************************************** + * Name: imxrt_gpio_select + * GPIO{1234}(l) and GPIO{6789}(h) share same IO MUX function, GPIO_MUXn + * selects one GPIO function. + * 0: GPIOl[n] is selected + * 1: GPIOh[n] is selected + ****************************************************************************/ + +static inline int imxrt_gpio_select(int port, int pin) +{ +#if IMXRT_GPIO_NPORTS > 5 + uint32_t gpr = port; + uint32_t setbits = 1 << pin; + uint32_t clearbits = 1 << pin; + uintptr_t regaddr = (uintptr_t) IMXRT_IOMUXC_GPR_GPR26; + + if (port != GPIO5) + { + /* Uses GPR26 as the base */ + + if (port >= GPIO6) + { + /* Map port to correct gpr index and set the GPIO_MUX3_GPIO[b]_SEL + * bit + */ + + gpr = port - GPIO6; + clearbits = 0; + } + else + { + /* The port is correct gpr index, so just clear the + * GPIO_MUX3_GPIO[b]_SEL bit. + */ + + setbits = 0; + } + + regaddr |= gpr * sizeof(uint32_t); + modifyreg32(regaddr, clearbits, setbits); + } +#endif + return OK; +} + /**************************************************************************** * Name: imxrt_gpio_configinput ****************************************************************************/ @@ -410,10 +485,11 @@ static int imxrt_gpio_configinput(gpio_pinset_t pinset) { return -EINVAL; } - regaddr = imxrt_padmux_address(index); putreg32(PADMUX_MUXMODE_ALT5, regaddr); + imxrt_gpio_select(port, pin); + /* Configure pin pad settings */ index = imxrt_padmux_map(index); diff --git a/arch/arm/src/imxrt/imxrt_gpio.h b/arch/arm/src/imxrt/imxrt_gpio.h index 647b125b70..5afb822939 100644 --- a/arch/arm/src/imxrt/imxrt_gpio.h +++ b/arch/arm/src/imxrt/imxrt_gpio.h @@ -2,7 +2,8 @@ * arch/arm/src/imxrt/imxrt_gpio.h * * Copyright (C) 2018 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -45,6 +46,7 @@ #include #include +#include "chip.h" #include "chip/imxrt_gpio.h" /************************************************************************************ @@ -53,14 +55,19 @@ /* 32-bit Encoding: * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 * ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM - * GPIO INPUT 00.. ..EE .GGP PPPP MMMM MMMM MMMM MMMM - * GPIO OUTPUT 01V. .S.. .GGP PPPP MMMM MMMM MMMM MMMM - * PERIPHERAL 10AA AS.. IIII IIII MMMM MMMM MMMM MMMM + * GPIO INPUT 00.. .EEG GGGP PPPP MMMM MMMM MMMM MMMM + * INT INPUT 11.. .EEG GGGP PPPP MMMM MMMM MMMM MMMM + * GPIO OUTPUT 01V. ..SG GGGP PPPP MMMM MMMM MMMM MMMM + * PERIPHERAL 10AA AAS. IIII IIII MMMM MMMM MMMM MMMM */ /* Input/Output Selection: * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 * ENCODING II.. .... .... .... .... .... .... .... */ @@ -81,20 +88,29 @@ /* GPIO Port Number * - * GPIO INPUT 00.. .... .GG. .... .... .... .... .... - * GPIO OUTPUT 01.. .... .GG. .... .... .... .... .... + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * GPIO INPUT 00.. ...G GGG. .... .... .... .... .... + * GPIO OUTPUT 01.. ...G GGG. .... .... .... .... .... */ #define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */ -#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) # define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */ # define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */ # define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */ # define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */ -# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO4 */ - +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */ +#if IMXRT_GPIO_NPORTS > 5 +# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */ +# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */ +# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */ +# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */ +#endif /* GPIO Pin Number: * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 * GPIO INPUT 00.. .... ...P PPPP .... .... .... .... * GPIO OUTPUT 01.. .... ...P PPPP .... .... .... .... */ @@ -136,11 +152,13 @@ /* Peripheral Alternate Function: * - * PERIPHERAL ..AA A... .... .... .... .... .... .... + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * PERIPHERAL ..AA AA.. .... .... .... .... .... .... */ -#define GPIO_ALT_SHIFT (27) /* Bits 27-29: Peripheral alternate function */ -#define GPIO_ALT_MASK (7 << GPIO_ALT_SHIFT) +#define GPIO_ALT_SHIFT (26) /* Bits 26-29: Peripheral alternate function */ +#define GPIO_ALT_MASK (0xf << GPIO_ALT_SHIFT) # define GPIO_ALT0 (0 << GPIO_ALT_SHIFT) /* Alternate function 0 */ # define GPIO_ALT1 (1 << GPIO_ALT_SHIFT) /* Alternate function 1 */ # define GPIO_ALT2 (2 << GPIO_ALT_SHIFT) /* Alternate function 2 */ @@ -149,22 +167,28 @@ /* Alternate function 5 is GPIO */ # define GPIO_ALT6 (6 << GPIO_ALT_SHIFT) /* Alternate function 6 */ # define GPIO_ALT7 (7 << GPIO_ALT_SHIFT) /* Alternate function 7 */ +# define GPIO_ALT8 (8 << GPIO_ALT_SHIFT) /* Alternate function 8 */ +# define GPIO_ALT9 (9 << GPIO_ALT_SHIFT) /* Alternate function 9 */ /* Peripheral Software Input On Field: * - * PERIPHERAL .... .S.. .... .... .... .... .... .... + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * PERIPHERAL .... ..S. .... .... .... .... .... .... */ -#define GPIO_SION_SHIFT (26) /* Bits 26: Peripheral SION function */ +#define GPIO_SION_SHIFT (25) /* Bits 25: Peripheral SION function */ #define GPIO_SION_MASK (1 << GPIO_SION_SHIFT) # define GPIO_SION_ENABLE (1 << GPIO_SION_SHIFT) /* enable SION */ /* Interrupt edge/level configuration * - * GPIO INPUT ... ..EE .... .... .... .... .... .... + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * INT INPUT 11.. .EE. .... .... .... .... .... .... */ -#define GPIO_INTCFG_SHIFT (24) /* Bits 24-25: Interrupt edge/level configuration */ +#define GPIO_INTCFG_SHIFT (25) /* Bits 25-26: Interrupt edge/level configuration */ #define GPIO_INTCFG_MASK (3 << GPIO_INTCFG_SHIFT) # define GPIO_INT_LOWLEVEL (GPIO_ICR_LOWLEVEL << GPIO_INTCFG_SHIFT) # define GPIO_INT_HIGHLEVEL (GPIO_ICR_HIGHLEVEL << GPIO_INTCFG_SHIFT) @@ -173,6 +197,8 @@ /* Pad Mux Register Index: * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 * PERIPHERAL .... .... IIII IIII .... .... .... .... */ @@ -182,6 +208,8 @@ /* IOMUX Pin Configuration: * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 * ENCODING .... .... .... .... MMMM MMMM MMMM MMMM * * See imxrt_iomuxc.h for detailed content. @@ -192,7 +220,7 @@ /* Helper addressing macros */ -#define IMXRT_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIO5 macros as indices */ +#define IMXRT_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */ #define IMXRT_GPIO_DR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_DR_OFFSET) #define IMXRT_GPIO_GDIR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_GDIR_OFFSET) @@ -202,6 +230,9 @@ #define IMXRT_GPIO_IMR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_IMR_OFFSET) #define IMXRT_GPIO_ISR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_ISR_OFFSET) #define IMXRT_GPIO_EDGE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_EDGE_OFFSET) +#define IMXRT_GPIO_SET(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_SET_OFFSET) +#define IMXRT_GPIO_CLEAR(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_CLEAR_OFFSET) +#define IMXRT_GPIO_TOGGLE(n) (IMXRT_GPIO_BASE(n) + IMXRT_GPIO_TOGGLE_OFFSET) /************************************************************************************ * Public Types @@ -224,7 +255,7 @@ extern "C" #define EXTERN extern #endif -/* Look-up table that maps GPIO1..GPIO5 indexes into GPIO register base addresses */ +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base addresses */ EXTERN uintptr_t g_gpio_base[IMXRT_GPIO_NPORTS]; diff --git a/arch/arm/src/imxrt/imxrt_gpioirq.c b/arch/arm/src/imxrt/imxrt_gpioirq.c index 9615b93ef6..fb1de38793 100644 --- a/arch/arm/src/imxrt/imxrt_gpioirq.c +++ b/arch/arm/src/imxrt/imxrt_gpioirq.c @@ -55,6 +55,16 @@ #ifdef CONFIG_IMXRT_GPIO_IRQ +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(_IMXRT_GPIO6_0_15_BASE) +# define _IMXRT_FOLLOWS_GPIO6_16_31 _IMXRT_GPIO6_0_15_BASE +#else +# define _IMXRT_FOLLOWS_GPIO6_16_31 IMXRT_GPIO_IRQ_LAST +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -131,8 +141,8 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin) } else #endif -#ifdef CONFIG_IMXRT_GPIO4_0_15_IRQ - if (irq < IMXRT_GPIO_IRQ_LAST) +#ifdef CONFIG_IMXRT_GPIO4_16_31_IRQ + if (irq < _IMXRT_GPIO5_0_15_BASE) { *regaddr = IMXRT_GPIO4_IMR; *pin = irq - _IMXRT_GPIO4_16_31_BASE + 16; @@ -148,14 +158,82 @@ static int imxrt_gpio_info(int irq, uintptr_t *regaddr, unsigned int *pin) } else #endif -#ifdef CONFIG_IMXRT_GPIO5_0_15_IRQ - if (irq < IMXRT_GPIO_IRQ_LAST) +#ifdef CONFIG_IMXRT_GPIO5_16_31_IRQ + if (irq < _IMXRT_FOLLOWS_GPIO6_16_31) { *regaddr = IMXRT_GPIO5_IMR; *pin = irq - _IMXRT_GPIO5_16_31_BASE + 16; } else #endif + +# ifdef CONFIG_IMXRT_GPIO6_0_15_IRQ + if (irq < _IMXRT_GPIO6_16_31_BASE) + { + *regaddr = IMXRT_GPIO6_IMR; + *pin = irq - _IMXRT_GPIO6_0_15_BASE; + } + else +# endif +# ifdef CONFIG_IMXRT_GPIO6_16_31_IRQ + if (irq < _IMXRT_GPIO7_0_15_BASE) + { + *regaddr = IMXRT_GPIO6_IMR; + *pin = irq - _IMXRT_GPIO6_16_31_BASE + 16; + } + else +# endif + +# ifdef CONFIG_IMXRT_GPIO7_0_15_IRQ + if (irq < _IMXRT_GPIO7_16_31_BASE) + { + *regaddr = IMXRT_GPIO7_IMR; + *pin = irq - _IMXRT_GPIO7_0_15_BASE; + } + else +# endif +# ifdef CONFIG_IMXRT_GPIO7_16_31_IRQ + if (irq < _IMXRT_GPIO8_0_15_BASE) + { + *regaddr = IMXRT_GPIO7_IMR; + *pin = irq - _IMXRT_GPIO7_16_31_BASE + 16; + } + else +# endif + +# ifdef CONFIG_IMXRT_GPIO8_0_15_IRQ + if (irq < _IMXRT_GPIO8_16_31_BASE) + { + *regaddr = IMXRT_GPIO8_IMR; + *pin = irq - _IMXRT_GPIO8_0_15_BASE; + } + else +# endif +# ifdef CONFIG_IMXRT_GPIO8_16_31_IRQ + if (irq < _IMXRT_GPIO9_0_15_BASE) + { + *regaddr = IMXRT_GPIO8_IMR; + *pin = irq - _IMXRT_GPIO8_16_31_BASE + 16; + } + else +# endif + +# ifdef CONFIG_IMXRT_GPIO9_0_15_IRQ + if (irq < _IMXRT_GPIO9_16_31_BASE) + { + *regaddr = IMXRT_GPIO9_IMR; + *pin = irq - _IMXRT_GPIO9_0_15_BASE; + } + else +# endif +# ifdef CONFIG_IMXRT_GPIO9_16_31_IRQ + if (irq < IMXRT_GPIO_IRQ_LAST) + { + *regaddr = IMXRT_GPIO9_IMR; + *pin = irq - _IMXRT_GPIO9_16_31_BASE + 16; + } + else +# endif { return -EINVAL; }