Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #81)
STMF7xxx RTC
This commit is contained in:
Gregory Nutt
commit
a0a082fc03
@ -149,6 +149,10 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c
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endif
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endif
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ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y)
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CHIP_CSRCS += stm32_lsi.c
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endif
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ifeq ($(CONFIG_STM32F7_I2C),y)
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CHIP_CSRCS += stm32_i2c.c
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endif
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101
arch/arm/src/stm32f7/stm32_lsi.c
Normal file
101
arch/arm/src/stm32f7/stm32_lsi.c
Normal file
@ -0,0 +1,101 @@
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/****************************************************************************
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* arch/arm/src/stm32f/stm32_lsi.c
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*
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* Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "up_arch.h"
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#include "stm32_rcc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_rcc_enablelsi
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*
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* Description:
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* Enable the Internal Low-Speed (LSI) RC Oscillator.
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*
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****************************************************************************/
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void stm32_rcc_enablelsi(void)
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{
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/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION bit
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* the RCC CSR register.
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*/
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modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION);
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/* Wait for the internal RC 40 kHz oscillator to be stable. */
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while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0);
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}
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/****************************************************************************
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* Name: stm32_rcc_disablelsi
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*
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* Description:
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* Disable the Internal Low-Speed (LSI) RC Oscillator.
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*
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****************************************************************************/
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void stm32_rcc_disablelsi(void)
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{
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/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION bit
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* the RCC CSR register.
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*/
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modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0);
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/* LSIRDY should go low after 3 LSI clock cycles */
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}
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@ -84,19 +84,19 @@
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/* Constants ************************************************************************/
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#if defined(CONFIG_STM32F7_RTC_HSECLOCK)
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# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE
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#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
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# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI
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#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
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# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE
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#else
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# warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count"
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#endif
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#define SYNCHRO_TIMEOUT (0x00020000)
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#define INITMODE_TIMEOUT (0x00010000)
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/* Proxy definitions to make the same code work for all the STM32 series ************/
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# define STM32_RCC_XXX STM32_RCC_BDCR
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# define RCC_XXX_YYYRST RCC_BDCR_BDRST
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# define RCC_XXX_RTCEN RCC_BDCR_RTCEN
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# define RCC_XXX_RTCSEL_MASK RCC_BDCR_RTCSEL_MASK
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# define RCC_XXX_RTCSEL_LSE RCC_BDCR_RTCSEL_LSE
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# define RCC_XXX_RTCSEL_LSI RCC_BDCR_RTCSEL_LSI
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# define RCC_XXX_RTCSEL_HSE RCC_BDCR_RTCSEL_HSE
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/* Time conversions */
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#define MINUTES_IN_HOUR 60
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@ -844,7 +844,7 @@ int up_rtc_initialize(void)
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int nretry = 0;
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/* Clocking for the PWR block must be provided. However, this is done
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* unconditionally in stm32f40xxx_rcc.c on power up. This done unconditionally
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* unconditionally in stm32f7xxx_rcc.c on power up. This done unconditionally
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* because the PWR block is also needed to set the internal voltage regulator for
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* maximum performance.
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*/
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@ -858,79 +858,91 @@ int up_rtc_initialize(void)
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if (regval != RTC_MAGIC)
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{
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/* Some boards do not have the external 32khz oscillator installed, for those
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* boards we must fallback to the crummy internal RC clock or the external high
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* rate clock
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/* Issue the Backup domain Reset Per Section 5.3.20 DocID028270 Rev 2
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* The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC backup domain control
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* register (RCC_BDCR) are in the Backup domain. As a result, after Reset,
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* these bits are write-protected and the DBP bit in the PWR power control
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* register (PWR_CR1) has to be set before these can be modified.
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* Refer to Section 5.1.1: System reset on page 148 for further information.
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* These bits are only reset after a Backup domain Reset
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* (see Section 5.1.3: Backup domain reset).
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*
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* This has to be done here so that PWR is already enabled
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*/
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modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
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modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
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#if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE
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/* Because of the Backup domain Reset - we must re enable the LSE */
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stm32_rcc_enablelse();
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#endif
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/* Some boards do not have the external 32khz oscillator installed, for those
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* boards we must fallback to the crummy internal RC clock or the external high
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* rate clock
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*/
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#ifdef CONFIG_STM32F7_RTC_HSECLOCK
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/* Use the HSE clock as the input to the RTC block */
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rtc_dumpregs("On reset HSE");
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
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#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
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/* Use the LSI clock as the input to the RTC block */
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rtc_dumpregs("On reset LSI");
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
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#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
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/* Use the LSE clock as the input to the RTC block */
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rtc_dumpregs("On reset LSE");
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
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#endif
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modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL);
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/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
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modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
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modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
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}
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else /* The RTC is already in use: check if the clock source is changed */
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else
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{
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#if defined(CONFIG_STM32F7_RTC_HSECLOCK) || defined(CONFIG_RTC_LSICLOCK) || \
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defined(CONFIG_STM32F7_RTC_LSECLOCK)
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uint32_t clksrc = getreg32(STM32_RCC_XXX);
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uint32_t clksrc = getreg32(STM32_RCC_BDCR);
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rtc_dumpregs("On reset warm");
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#if defined(CONFIG_STM32F7_RTC_HSECLOCK)
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if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE)
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#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
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if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSI)
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#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
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if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSE)
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#endif
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#endif
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/* The RTC is already in use: check if the clock source has changed */
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if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL)
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{
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tr_bkp = getreg32(STM32_RTC_TR);
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dr_bkp = getreg32(STM32_RTC_DR);
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modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
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modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
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modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
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modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
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#if defined(CONFIG_STM32F7_RTC_HSECLOCK)
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# if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE
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/* Because of the Backup domain Reset - we must re enable the LSE
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* if it is used
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*/
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stm32_rcc_enablelse();
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#endif
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/* Change to the new clock as the input to the RTC block */
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
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#elif defined(CONFIG_STM32F7_RTC_LSICLOCK)
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
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#elif defined(CONFIG_STM32F7_RTC_LSECLOCK)
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modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
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#endif
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modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL);
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putreg32(tr_bkp, STM32_RTC_TR);
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putreg32(dr_bkp, STM32_RTC_DR);
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/* Remember that the RTC is initialized */
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/* Keep the fact that the RTC is initialized */
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putreg32(RTC_MAGIC, RTC_MAGIC_REG);
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/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
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modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
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modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
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}
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}
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