Add I2C trace capability; Fix another STM32 I2C/FSMC bug; add verify command to the I2C tool
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3961 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
79a73a8e9d
commit
a0c935e699
@ -122,29 +122,30 @@
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(SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS))
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/* Debug ****************************************************************************/
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/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output.
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*
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* If CONFIG_I2C_POLLED and CONFIG_DEBUG_VERBOSE are also defined, then some
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* additinal detailed output is generated. If CONFIG_I2C_POLLED is not defined and
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* CONFIG_DEBUG_I2CINTS, then output will ge generated from the interrupt handler
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* as well.
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*/
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/* CONFIG_DEBUG_I2C + CONFIG_DEBUG enables general I2C debug output. */
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#ifdef CONFIG_DEBUG_I2C
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# define i2cdbg dbg
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# ifdef CONFIG_I2C_POLLED
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# define intdbg vdbg
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# else
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# ifdef CONFIG_DEBUG_I2CINTS
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# define intdbg lldbg
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# else
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# define intdbg(x...)
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# endif
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# endif
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# define i2cvdbg vdbg
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#else
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# undef CONFIG_DEBUG_I2CINTS
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# define i2cdbg(x...)
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# define intdbg(x...)
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# define i2cvdbg(x...)
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#endif
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/* I2C event trace logic. NOTE: trace uses the internal, non-standard, low-level
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* debug interface lib_rawprintf() but does not require that any other debug
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* is enabled.
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*/
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#ifndef CONFIG_I2C_TRACE
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# define stm32_i2c_tracereset(p)
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# define stm32_i2c_tracenew(p,s)
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# define stm32_i3c_traceevent(p,e,a)
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# define stm32_i2c_tracedump(p)
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#endif
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#ifndef CONFIG_I2C_NTRACE
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# define CONFIG_I2C_NTRACE 20
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#endif
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/************************************************************************************
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@ -159,6 +160,33 @@ enum stm32_intstate_e
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INTSTATE_DONE, /* Interrupt activity complete */
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};
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/* Trace events */
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enum stm32_trace_e
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{
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I2CEVENT_NONE = 0, /* No events have occurred with this status */
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I2CEVENT_SB, /* Start/Master, param = msgc */
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I2CEVENT_SENDBYTE, /* Send byte, param = byte sent */
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I2CEVENT_READ, /* Read data, param = dcnt */
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I2CEVENT_ITBUFEN, /* Enable buffer interrupts, param = 0 */
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I2CEVENT_RXNE, /* Read more dta, param = dcnt */
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I2CEVENT_REITBUFEN, /* Re-enable buffer interrupts, param = 0 */
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I2CEVENT_DISITBUFEN, /* Disable buffer interrupts, param = 0 */
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I2CEVENT_BTFSTART, /* Last byte sent, re-starting, param = msgc */
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I2CEVENT_BTFSTOP, /* Last byte sten, send stop, param = 0 */
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I2CEVENT_ERROR /* Error occurred, param = 0 */
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};
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/* Trace data */
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struct stm32_trace_s
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{
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uint32_t status; /* I2C 32-bit SR2|SR1 status */
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uint32_t count; /* Interrupt count when status change */
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enum stm32_intstate_e event; /* Last event that occurred with this status */
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uint32_t parm; /* Parameter associated with the event */
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};
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/* I2C Device Private Data */
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struct stm32_i2c_priv_s
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@ -177,6 +205,18 @@ struct stm32_i2c_priv_s
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int dcnt; /* Current message length */
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uint16_t flags; /* Current message flags */
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/* I2C trace support */
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#ifdef CONFIG_I2C_TRACE
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int tndx; /* Trace array index */
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uint32_t isr_count; /* Count of ISRs processed */
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uint32_t old_status; /* Last 32-bit status value */
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/* The actual trace data */
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struct stm32_trace_s trace[CONFIG_I2C_NTRACE];
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#endif
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uint32_t status; /* End of transfer SR2|SR1 status */
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};
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@ -203,11 +243,19 @@ static inline void stm32_i2c_putreg(FAR struct stm32_i2c_priv_s *priv, uint8_t o
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static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
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uint8_t offset, uint16_t clearbits,
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uint16_t setbits);
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static void inline stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev);
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static int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev);
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static void inline stm32_i2c_sem_post(FAR struct i2c_dev_s *dev);
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static void inline stm32_i2c_sem_init(FAR struct i2c_dev_s *dev);
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static void inline stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev);
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static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev);
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv);
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv);
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static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev);
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static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev);
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static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev);
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#ifdef CONFIG_I2C_TRACE
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static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv);
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static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status);
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static void stm32_i3c_traceevent(FAR struct stm32_i2c_priv_s *priv,
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enum stm32_trace_e event, uint32_t parm);
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static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv);
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#endif
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static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv,
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uint32_t frequency);
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static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv);
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@ -356,7 +404,7 @@ static inline void stm32_i2c_modifyreg(FAR struct stm32_i2c_priv_s *priv,
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*
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************************************************************************************/
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static void inline stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
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static inline void stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
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{
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while (sem_wait(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl) != 0)
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{
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@ -365,7 +413,7 @@ static void inline stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
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}
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/************************************************************************************
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* Name: stm32_i2c_sem_waitisr
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* Name: stm32_i2c_sem_waitdone
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*
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* Description:
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* Wait for a transfer to complete
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@ -373,9 +421,8 @@ static void inline stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
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************************************************************************************/
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#ifndef CONFIG_I2C_POLLED
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static int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
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{
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FAR struct stm32_i2c_priv_s *priv = ((struct stm32_i2c_inst_s *)dev)->priv;
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struct timespec abstime;
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irqstate_t flags;
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uint32_t regval;
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@ -446,9 +493,8 @@ static int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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return ret;
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}
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#else
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int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv )
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{
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FAR struct stm32_i2c_priv_s *priv = ((struct stm32_i2c_inst_s *)dev)->priv;
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uint32_t start;
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uint32_t elapsed;
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int ret;
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@ -458,9 +504,9 @@ int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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* sem_timedwait() sleeps.
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*/
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priv->intstate = INTSTATE_WAITING;
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start = clock_systimer();
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do
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priv->intstate = INTSTATE_WAITING;
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start = clock_systimer();
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do
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{
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/* Poll by simply calling the timer interrupt handler until it
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* reports that it is done.
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@ -473,10 +519,13 @@ int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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elapsed = clock_systimer() - start;
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}
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/* Loop until the interrupt level transfer is complete. */
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/* Loop until the transfer is complete. */
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while (priv->intstate != INTSTATE_DONE && elapsed < CONFIG_STM32_I2CTIMEOTICKS);
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i2cvdbg("intstate: %d elapsed: %d threshold: %d status: %08x\n",
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priv->intstate, elapsed, CONFIG_STM32_I2CTIMEOTICKS, priv->status);
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/* Set the interrupt state back to IDLE */
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ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT;
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@ -485,6 +534,62 @@ int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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}
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#endif
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/************************************************************************************
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* Name: stm32_i2c_sem_waitstop
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*
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* Description:
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* Wait for a STOP to complete
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*
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************************************************************************************/
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static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
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{
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uint32_t start;
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uint32_t elapsed;
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uint32_t cr1;
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uint32_t sr1;
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/* Wait as stop might still be in progress; but stop might also
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* be set because of a timeout error: "The [STOP] bit is set and
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* cleared by software, cleared by hardware when a Stop condition is
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* detected, set by hardware when a timeout error is detected."
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*/
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start = clock_systimer();
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do
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{
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/* Check for STOP condition */
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cr1 = stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET);
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if ((cr1 & I2C_CR1_STOP) == 0)
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{
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return;
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}
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/* Check for timeout error */
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sr1 = stm32_i2c_getreg(priv, STM32_I2C_SR1_OFFSET);
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if ((sr1 & I2C_SR1_TIMEOUT) != 0)
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{
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return;
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}
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/* Calculate the elapsed time */
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elapsed = clock_systimer() - start;
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}
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/* Loop until the stop is complete or a timeout occurs. */
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while (elapsed < CONFIG_STM32_I2CTIMEOTICKS);
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/* If we get here then a timeout occurred with the STOP condition
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* still pending.
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*/
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i2cvdbg("Timeout with CR1: %04x SR1: %04x\n", cr1, sr1);
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}
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/************************************************************************************
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* Name: stm32_i2c_sem_post
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*
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@ -493,7 +598,7 @@ int inline stm32_i2c_sem_waitisr(FAR struct i2c_dev_s *dev)
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*
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************************************************************************************/
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static void inline stm32_i2c_sem_post(FAR struct i2c_dev_s *dev)
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static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev)
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{
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sem_post( &((struct stm32_i2c_inst_s *)dev)->priv->sem_excl );
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}
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@ -506,7 +611,7 @@ static void inline stm32_i2c_sem_post(FAR struct i2c_dev_s *dev)
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*
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************************************************************************************/
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static void inline stm32_i2c_sem_init(FAR struct i2c_dev_s *dev)
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static inline void stm32_i2c_sem_init(FAR struct i2c_dev_s *dev)
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{
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sem_init(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl, 0, 1);
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#ifndef CONFIG_I2C_POLLED
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@ -522,7 +627,7 @@ static void inline stm32_i2c_sem_init(FAR struct i2c_dev_s *dev)
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*
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************************************************************************************/
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static void inline stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev)
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static inline void stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev)
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{
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sem_destroy(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
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#ifndef CONFIG_I2C_POLLED
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@ -530,6 +635,77 @@ static void inline stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev)
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#endif
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}
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/************************************************************************************
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* Name: stm32_i2c_trace*
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*
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* Description:
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* I2C trace instrumentation
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*
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************************************************************************************/
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#ifdef CONFIG_I2C_TRACE
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static void stm32_i2c_tracereset(FAR struct stm32_i2c_priv_s *priv)
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{
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/* Reset the trace info for a new data collection */
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priv->isr_count = 0;
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priv->old_status = 0xffffffff;
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priv->tndx = -1;
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}
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static void stm32_i2c_tracenew(FAR struct stm32_i2c_priv_s *priv, uint32_t status)
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{
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/* Increment the cout of interrupts received */
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priv->isr_count++;
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/* Has the status changed from the last interrupt */
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if (status != priv->old_status)
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{
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/* Yes.. bump up the trace index (unless we are out of trace entries) */
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if (priv->tndx < CONFIG_I2C_NTRACE)
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{
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priv->tndx++;
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}
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/* Initialize the new trace entry */
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priv->trace[priv->tndx].status = status;
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priv->trace[priv->tndx].count = priv->isr_count;
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priv->trace[priv->tndx].event = I2CEVENT_NONE;
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priv->trace[priv->tndx].parm = 0;
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priv->old_status = status;
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}
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}
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static void stm32_i3c_traceevent(FAR struct stm32_i2c_priv_s *priv,
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enum stm32_trace_e event, uint32_t parm)
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{
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/* Add the event to the trace entry (possibly overwriting a previous trace
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* event.
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*/
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priv->trace[priv->tndx].event = event;
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priv->trace[priv->tndx].parm = parm;
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}
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static void stm32_i2c_tracedump(FAR struct stm32_i2c_priv_s *priv)
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{
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int i;
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/* Dump all of the buffered trace entries */
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for (i = 0; i < priv->tndx; i++)
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{
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lib_rawprintf("%2d. STATUS: %08x COUNT: %3d EVENT: %2d PARM: %08x\n", i,
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priv->trace[i].status, priv->trace[i].count,
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priv->trace[i].event, priv->trace[i].parm);
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}
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}
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#endif /* CONFIG_I2C_TRACE */
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/************************************************************************************
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* Name: stm32_i2c_setclock
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*
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@ -772,22 +948,16 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
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{
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uint32_t status = stm32_i2c_getstatus(priv);
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#ifdef CONFIG_DEBUG_I2CINTS
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static uint32_t isr_count = 0;
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static uint32_t old_status = 0xffff;
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isr_count++;
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/* Check for new trace setup */
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if (old_status != status)
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{
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intdbg("status = %8x, count=%d\n", status, isr_count); fflush(stdout);
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old_status = status;
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}
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#endif
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stm32_i2c_tracenew(priv, status);
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/* Was start bit sent */
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if ((status & I2C_SR1_SB) != 0)
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{
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stm32_i3c_traceevent(priv, I2CEVENT_SB, priv->msgc);
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/* Get run-time data */
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priv->ptr = priv->msgv->buffer;
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@ -824,11 +994,13 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
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else if ((priv->flags & I2C_M_READ) == 0 && (status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0)
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{
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stm32_i3c_traceevent(priv, I2CEVENT_READ, priv->dcnt);
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if (--priv->dcnt >= 0)
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{
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/* Send a byte */
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intdbg("Send byte: %2x\n", *priv->ptr);
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stm32_i3c_traceevent(priv, I2CEVENT_SENDBYTE, *priv->ptr);
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stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, *priv->ptr++);
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}
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}
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@ -838,6 +1010,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
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/* Enable RxNE and TxE buffers in order to receive one or multiple bytes */
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#ifndef CONFIG_I2C_POLLED
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stm32_i3c_traceevent(priv, I2CEVENT_ITBUFEN, 0);
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stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
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#endif
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}
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||||
@ -848,11 +1021,10 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
|
||||
{
|
||||
/* Read a byte, if dcnt goes < 0, then read dummy bytes to ack ISRs */
|
||||
|
||||
intdbg("dcnt=%d\n", priv->dcnt);
|
||||
stm32_i3c_traceevent(priv, I2CEVENT_RXNE, priv->dcnt);
|
||||
if (--priv->dcnt >= 0)
|
||||
{
|
||||
*priv->ptr++ = stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET);
|
||||
intdbg("Received: %2x\n", *(priv->ptr-1) );
|
||||
|
||||
/* Disable acknowledge when last byte is to be received */
|
||||
|
||||
@ -870,10 +1042,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
|
||||
#ifndef CONFIG_I2C_POLLED
|
||||
if (priv->dcnt > 0)
|
||||
{
|
||||
stm32_i3c_traceevent(priv, I2CEVENT_REITBUFEN, 0);
|
||||
stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_ITBUFEN);
|
||||
}
|
||||
else if (priv->dcnt == 0)
|
||||
{
|
||||
stm32_i3c_traceevent(priv, I2CEVENT_DISITBUFEN, 0);
|
||||
stm32_i2c_modifyreg(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_ITBUFEN, 0);
|
||||
}
|
||||
#endif
|
||||
@ -882,7 +1056,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
|
||||
|
||||
if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0)
|
||||
{
|
||||
intdbg("BTF\n");
|
||||
stm32_i2c_getreg(priv, STM32_I2C_DR_OFFSET); /* ACK ISR */
|
||||
|
||||
/* Do we need to terminate or restart after this byte?
|
||||
@ -895,6 +1068,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
|
||||
|
||||
if (priv->msgc > 0)
|
||||
{
|
||||
stm32_i3c_traceevent(priv, I2CEVENT_BTFSTART, priv->msgc);
|
||||
if (priv->msgv->flags & I2C_M_NORESTART)
|
||||
{
|
||||
priv->ptr = priv->msgv->buffer;
|
||||
@ -916,7 +1090,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
|
||||
}
|
||||
else if (priv->msgv)
|
||||
{
|
||||
intdbg("stop2: status = %8x\n", status);
|
||||
stm32_i3c_traceevent(priv, I2CEVENT_BTFSTOP, 0);
|
||||
stm32_i2c_sendstop(priv);
|
||||
|
||||
/* Is there a thread waiting for this event (there should be) */
|
||||
@ -948,6 +1122,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s * priv)
|
||||
|
||||
if ((status & I2C_SR1_ERRORMASK) != 0)
|
||||
{
|
||||
stm32_i3c_traceevent(priv, I2CEVENT_ERROR, 0);
|
||||
|
||||
/* Clear interrupt flags */
|
||||
|
||||
stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0);
|
||||
@ -1216,46 +1392,30 @@ static int stm32_i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
|
||||
|
||||
static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count)
|
||||
{
|
||||
struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev;
|
||||
struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev;
|
||||
FAR struct stm32_i2c_priv_s *priv = inst->priv;
|
||||
uint32_t status = 0;
|
||||
uint32_t ahbenr;
|
||||
uint16_t regval;
|
||||
int status_errno = 0;
|
||||
int errval = 0;
|
||||
|
||||
ASSERT(count);
|
||||
|
||||
/* Disable FSMC that shares a pin with I2C1 (LBAR) */
|
||||
|
||||
ahbenr = stm32_i2c_disablefsmc(inst->priv);
|
||||
ahbenr = stm32_i2c_disablefsmc(priv);
|
||||
|
||||
/* Wait as stop might still be in progress; but stop might also
|
||||
* be set because of a timeout error: "The [STOP] bit is set and
|
||||
* cleared by software, cleared by hardware when a Stop condition is
|
||||
* detected, set by hardware when a timeout error is detected."
|
||||
/* Wait for any STOP in progress. NOTE: If we have to disable the FSMC
|
||||
* then we cannot do this at the top of the loop, unfortunately. The STOP
|
||||
* will not complete normally if the FSMC is enabled.
|
||||
*/
|
||||
|
||||
for (;;)
|
||||
{
|
||||
/* Check for STOP condition */
|
||||
|
||||
regval = stm32_i2c_getreg(inst->priv, STM32_I2C_CR1_OFFSET);
|
||||
if ((regval & I2C_CR1_STOP) == 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check for timeout error */
|
||||
|
||||
regval = stm32_i2c_getreg(inst->priv, STM32_I2C_SR1_OFFSET);
|
||||
if ((regval & I2C_SR1_TIMEOUT) != 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
#ifndef CONFIG_STM32_I2C1
|
||||
stm32_i2c_sem_waitstop(priv);
|
||||
#endif
|
||||
|
||||
/* Clear any pending error interrupts */
|
||||
|
||||
stm32_i2c_putreg(inst->priv, STM32_I2C_SR1_OFFSET, 0);
|
||||
stm32_i2c_putreg(priv, STM32_I2C_SR1_OFFSET, 0);
|
||||
|
||||
/* "Note: When the STOP, START or PEC bit is set, the software must
|
||||
* not perform any write access to I2C_CR1 before this bit is
|
||||
@ -1264,31 +1424,39 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
||||
* not cleared by hardware, then we will have to do that from hardware.
|
||||
*/
|
||||
|
||||
stm32_i2c_clrstart(inst->priv);
|
||||
stm32_i2c_clrstart(priv);
|
||||
|
||||
/* Old transfers are done */
|
||||
|
||||
inst->priv->msgv = msgs;
|
||||
inst->priv->msgc = count;
|
||||
priv->msgv = msgs;
|
||||
priv->msgc = count;
|
||||
|
||||
/* Reset I2C trace logic */
|
||||
|
||||
stm32_i2c_tracereset(priv);
|
||||
|
||||
/* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */
|
||||
|
||||
stm32_i2c_setclock(inst->priv, inst->frequency);
|
||||
stm32_i2c_setclock(priv, inst->frequency);
|
||||
|
||||
/* Trigger start condition, then the process moves into the ISR. I2C
|
||||
* interrupts will be enabled within stm32_i2c_waitisr().
|
||||
* interrupts will be enabled within stm32_i2c_waitdone().
|
||||
*/
|
||||
|
||||
stm32_i2c_sendstart(inst->priv);
|
||||
priv->status = 0;
|
||||
stm32_i2c_sendstart(priv);
|
||||
|
||||
/* Wait for an ISR, if there was a timeout, fetch latest status to get
|
||||
* the BUSY flag.
|
||||
*/
|
||||
|
||||
if (stm32_i2c_sem_waitisr(dev) == ERROR)
|
||||
if (stm32_i2c_sem_waitdone(priv) == ERROR)
|
||||
{
|
||||
status = stm32_i2c_getstatus(inst->priv);
|
||||
status_errno = ETIMEDOUT;
|
||||
status = stm32_i2c_getstatus(priv);
|
||||
errval = ETIMEDOUT;
|
||||
|
||||
i2cdbg("Timed out: CR1: %04x status: %08x\n",
|
||||
stm32_i2c_getreg(priv, STM32_I2C_CR1_OFFSET), status);
|
||||
|
||||
/* "Note: When the STOP, START or PEC bit is set, the software must
|
||||
* not perform any write access to I2C_CR1 before this bit is
|
||||
@ -1296,13 +1464,13 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
||||
* second STOP, START or PEC request."
|
||||
*/
|
||||
|
||||
stm32_i2c_clrstart(inst->priv);
|
||||
stm32_i2c_clrstart(priv);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* clear SR2 (BUSY flag) as we've done successfully */
|
||||
|
||||
status = inst->priv->status & 0xffff;
|
||||
status = priv->status & 0xffff;
|
||||
}
|
||||
|
||||
/* Check for error status conditions */
|
||||
@ -1315,37 +1483,37 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
||||
{
|
||||
/* Bus Error */
|
||||
|
||||
status_errno = EIO;
|
||||
errval = EIO;
|
||||
}
|
||||
else if (status & I2C_SR1_ARLO)
|
||||
{
|
||||
/* Arbitration Lost (master mode) */
|
||||
|
||||
status_errno = EAGAIN;
|
||||
errval = EAGAIN;
|
||||
}
|
||||
else if (status & I2C_SR1_AF)
|
||||
{
|
||||
/* Acknowledge Failure */
|
||||
|
||||
status_errno = ENXIO;
|
||||
errval = ENXIO;
|
||||
}
|
||||
else if (status & I2C_SR1_OVR)
|
||||
{
|
||||
/* Overrun/Underrun */
|
||||
|
||||
status_errno = EIO;
|
||||
errval = EIO;
|
||||
}
|
||||
else if (status & I2C_SR1_PECERR)
|
||||
{
|
||||
/* PEC Error in reception */
|
||||
|
||||
status_errno = EPROTO;
|
||||
errval = EPROTO;
|
||||
}
|
||||
else if (status & I2C_SR1_TIMEOUT)
|
||||
{
|
||||
/* Timeout or Tlow Error */
|
||||
|
||||
status_errno = ETIME;
|
||||
errval = ETIME;
|
||||
}
|
||||
|
||||
/* This is not an error and should never happen since SMBus is not enabled */
|
||||
@ -1356,13 +1524,13 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
||||
* that want to trade their ability to master for a pin.
|
||||
*/
|
||||
|
||||
status_errno = EINTR;
|
||||
errval = EINTR;
|
||||
}
|
||||
}
|
||||
|
||||
/* This is not an error, but should not happen. The BUSY signal can hang,
|
||||
* however, if there are unhealthy devices on the bus that need to be reset.
|
||||
* NOTE: We will only see this buy indication if stm32_i2c_sem_waitisr()
|
||||
* NOTE: We will only see this buy indication if stm32_i2c_sem_waitdone()
|
||||
* fails above; Otherwise it is cleared.
|
||||
*/
|
||||
|
||||
@ -1370,16 +1538,28 @@ static int stm32_i2c_process(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *ms
|
||||
{
|
||||
/* I2C Bus is for some reason busy */
|
||||
|
||||
status_errno = EBUSY;
|
||||
errval = EBUSY;
|
||||
}
|
||||
|
||||
/* Dump the trace result */
|
||||
|
||||
stm32_i2c_tracedump(priv);
|
||||
|
||||
/* Wait for any STOP in progress. NOTE: If we have to disable the FSMC
|
||||
* then we cannot do this at the top of the loop, unfortunately. The STOP
|
||||
* will not complete normally if the FSMC is enabled.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_I2C1
|
||||
stm32_i2c_sem_waitstop(priv);
|
||||
#endif
|
||||
|
||||
/* Re-enable the FSMC */
|
||||
|
||||
stm32_i2c_enablefsmc(ahbenr);
|
||||
stm32_i2c_sem_post(dev);
|
||||
|
||||
errno = status_errno;
|
||||
return -status_errno;
|
||||
return -errval;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue
Block a user