TM4C129X Timer: Add some missing addresses and some of the register bit definitions. Still incomplete
This commit is contained in:
Gregory Nutt
parent
7be7ace918
commit
a1065a919a
@ -12,6 +12,11 @@
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Some bitfield definitions taken from a header file provided by:
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*
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* Copyright (C) 2014 TRD2 Inc. All rights reserved.
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* Author: Calvin Maguranis <calvin.maguranis@trd2inc.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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@ -105,12 +110,17 @@
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#if TIVA_NTIMERS > 0
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#define TIVA_TIMER0_CFG (TIVA_TIMER0_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER0_TAMR (TIVA_TIMER0_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER0_CTL (TIVA_TIMER0_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER0_TBMR (TIVA_TIMER0_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER0_CTL (TIVA_TIMER0_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER0_SYNC (TIVA_TIMER0_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER0_IMR (TIVA_TIMER0_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER0_RIS (TIVA_TIMER0_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER0_ICR (TIVA_TIMER0_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -145,12 +155,17 @@
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#if TIVA_NTIMERS > 1
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#define TIVA_TIMER1_CFG (TIVA_TIMER1_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER1_TAMR (TIVA_TIMER1_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER1_CTL (TIVA_TIMER1_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER1_TBMR (TIVA_TIMER1_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER1_CTL (TIVA_TIMER1_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER1_SYNC (TIVA_TIMER1_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER1_IMR (TIVA_TIMER1_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER1_RIS (TIVA_TIMER1_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER1_ICR (TIVA_TIMER1_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -185,12 +200,17 @@
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#if TIVA_NTIMERS > 2
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#define TIVA_TIMER2_CFG (TIVA_TIMER2_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER2_TAMR (TIVA_TIMER2_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER2_CTL (TIVA_TIMER2_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER2_TBMR (TIVA_TIMER2_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER2_CTL (TIVA_TIMER2_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER2_SYNC (TIVA_TIMER2_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER2_IMR (TIVA_TIMER2_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER2_RIS (TIVA_TIMER2_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER2_ICR (TIVA_TIMER2_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -225,12 +245,17 @@
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#if TIVA_NTIMERS > 3
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#define TIVA_TIMER3_CFG (TIVA_TIMER3_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER3_TAMR (TIVA_TIMER3_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER3_CTL (TIVA_TIMER3_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER3_TBMR (TIVA_TIMER3_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER3_CTL (TIVA_TIMER3_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER3_SYNC (TIVA_TIMER3_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER3_IMR (TIVA_TIMER3_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER3_RIS (TIVA_TIMER3_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER3_ICR (TIVA_TIMER3_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -265,12 +290,17 @@
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#if TIVA_NTIMERS > 4
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#define TIVA_TIMER4_CFG (TIVA_TIMER4_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER4_TAMR (TIVA_TIMER4_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER4_CTL (TIVA_TIMER4_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER4_TBMR (TIVA_TIMER4_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER4_CTL (TIVA_TIMER4_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER4_SYNC (TIVA_TIMER4_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER4_IMR (TIVA_TIMER4_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER4_RIS (TIVA_TIMER4_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER4_ICR (TIVA_TIMER4_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -305,12 +335,17 @@
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#if TIVA_NTIMERS > 5
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#define TIVA_TIMER5_CFG (TIVA_TIMER5_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER5_TAMR (TIVA_TIMER5_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER5_CTL (TIVA_TIMER5_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER5_TBMR (TIVA_TIMER5_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER5_CTL (TIVA_TIMER5_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER5_SYNC (TIVA_TIMER5_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER5_IMR (TIVA_TIMER5_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER5_RIS (TIVA_TIMER5_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER5_ICR (TIVA_TIMER5_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -345,12 +380,17 @@
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#if TIVA_NTIMERS > 6
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#define TIVA_TIMER6_CFG (TIVA_TIMER6_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER6_TAMR (TIVA_TIMER6_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER6_CTL (TIVA_TIMER6_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER6_TBMR (TIVA_TIMER6_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER6_CTL (TIVA_TIMER6_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER6_SYNC (TIVA_TIMER6_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER6_IMR (TIVA_TIMER6_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER6_RIS (TIVA_TIMER6_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER6_ICR (TIVA_TIMER6_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -385,12 +425,17 @@
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#if TIVA_NTIMERS > 7
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#define TIVA_TIMER7_CFG (TIVA_TIMER7_BASE + TIVA_TIMER_CFG_OFFSET)
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#define TIVA_TIMER7_TAMR (TIVA_TIMER7_BASE + TIVA_TIMER_TAMR_OFFSET)
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#define TIVA_TIMER7_CTL (TIVA_TIMER7_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER7_TBMR (TIVA_TIMER7_BASE + TIVA_TIMER_TBMR_OFFSET)
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#endif
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#define TIVA_TIMER7_CTL (TIVA_TIMER7_BASE + TIVA_TIMER_CTL_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIVA_TIMER7_SYNC (TIVA_TIMER7_BASE + TIVA_TIMER_SYNC_OFFSET)
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#endif
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#define TIVA_TIMER7_IMR (TIVA_TIMER7_BASE + TIVA_TIMER_IMR_OFFSET)
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#define TIVA_TIMER7_RIS (TIVA_TIMER7_BASE + TIVA_TIMER_RIS_OFFSET)
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#define TIVA_TIMER7_ICR (TIVA_TIMER7_BASE + TIVA_TIMER_ICR_OFFSET)
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@ -429,7 +474,7 @@
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#define TIMER__CFG_MASK (7 << TIMER_CFG_CFG_SHIFT)
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# define TIMER_CFG_CFG_32 (0 << TIMER_CFG_CFG_SHIFT) /* 32-bit timer configuration */
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# define TIMER_CFG_CFG_RTC (1 << TIMER_CFG_CFG_SHIFT) /* 32-bit real-time clock (RTC) counter configuration */
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# define TIMER_CFG_CFG_16 (1 << TIMER_CFG_CFG_SHIFT) /* 16-bit timer configuration */
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# define TIMER_CFG_CFG_16 (4 << TIMER_CFG_CFG_SHIFT) /* 16-bit timer configuration */
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/* GPTM Timer A Mode (TAMR) */
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@ -449,10 +494,64 @@
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# define TIMER_TAMR_TACDIR_UP (1 << TIMER_TAMR_TACDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */
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#define TIMER_TAMR_TAMIE (1 << 5) /* Bit 5: Timer A Match Interrupt Enable */
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIMER_TAMR_TAWOT (1 << 6) /* Bit 6: GPTM Timer A Wait-on-Trigger */
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# define TIMER_TAMR_TASNAPS (1 << 7) /* Bit 7: GPTM Timer A Snap-Shot Mode */
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# define TIMER_TAMR_TAILD (1 << 8) /* Bit 8: GPTM Timer A Interval Load Write */
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# define TIMER_TAMR_TAPWMIE (1 << 9) /* Bit 9: GPTM Timer A PWM Interrupt Enable */
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# define TIMER_TAMR_TAMRSU (1 << 10) /* Bit 10: GPTM Timer A Match Register Update */
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# define TIMER_TAMR_TAPLO (1 << 11) /* Bit 11: GPTM Timer A PWM Legacy Operation */
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# define TIMER_TAMR_TACINTD (1 << 12) /* Bit 12: One-shot/Periodic Interrupt Disable */
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# define TIMER_TAMR_TCACT_SHIFT (13) /* Bits 13-15: Timer Compare Action Select */
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# define TIMER_TAMR_TCACT_MASK (7 << TIMER_TAMR_TCACT_SHIFT)
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# define TIMER_TAMR_TCACT_NONE (0 << TIMER_TAMR_TCACT_SHIFT) /* Disable compare operations */
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# define TIMER_TAMR_TCACT_TOGGLE (1 << TIMER_TAMR_TCACT_SHIFT) /* Toggle state on timeout */
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# define TIMER_TAMR_TCACT_CLRTO (2 << TIMER_TAMR_TCACT_SHIFT) /* Clear CCP on timeout */
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# define TIMER_TAMR_TCACT_SETTO (3 << TIMER_TAMR_TCACT_SHIFT) /* Set CCP on timeout */
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# define TIMER_TAMR_TCACT_SETTOGTO (4 << TIMER_TAMR_TCACT_SHIFT) /* Set CCP and toggle on TimeOut */
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# define TIMER_TAMR_TCACT_CLRTOGTO (5 << TIMER_TAMR_TCACT_SHIFT) /* Clear CCP and toggle on TimeOut */
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# define TIMER_TAMR_TCACT_SETCLRTO (6 << TIMER_TAMR_TCACT_SHIFT) /* Set CCP and clear on timeout */
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# define TIMER_TAMR_TCACT_CLRSETTO (7 << TIMER_TAMR_TCACT_SHIFT) /* Clear CCP and set on timeout */
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#endif
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/* GPTM Timer B Mode (TBMR) */
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIMER_TBMR_
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# define TIMER_TBMR_TBMR_SHIFT 0 /* Bits 1-0: Timer B Mode */
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# define TIMER_TBMR_TBMR_MASK (3 << TIMER_TBMR_TBMR_SHIFT)
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# define TIMER_TBMR_TBMR_ONESHOT (1 << TIMER_TBMR_TBMR_SHIFT) /* One-Shot Timer mode */
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# define TIMER_TBMR_TBMR_PERIODIC (2 << TIMER_TBMR_TBMR_SHIFT) /* Periodic Timer mode */
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# define TIMER_TBMR_TBMR_CAPTURE (3 << TIMER_TBMR_TBMR_SHIFT) /* Capture mode */
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# define TIMER_TBMR_TBCMR (1 << 2) /* Bit 2: Timer B Capture Mode */
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# define TIMER_TBMR_TBCMR_EDGECOUNT (0 << TIMER_TBMR_TBCMR_SHIFT) /* Edge-Count mode */
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# define TIMER_TBMR_TBCMR_EDGETIME (1 << TIMER_TBMR_TBCMR_SHIFT) /* Edge-Time mode */
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# define TIMER_TBMR_TBAMS (1 << 3) /* Bit 3: Timer B Alternate Mode Select */
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# define TIMER_TBMR_TBAMS_CAPTURE (0 << TIMER_TBMR_TBAMS_SHIFT) /* Capture mode is enabled */
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# define TIMER_TBMR_TBAMS_PWM (1 << TIMER_TBMR_TBAMS_SHIFT) /* PWM mode is enabled */
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# define TIMER_TBMR_TBCDIR (1 << 4) /* Bit 4: Timer B Count Direction */
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# define TIMER_TBMR_TBCDIR_DOWN (0 << TIMER_TBMR_TBCDIR_SHIFT) /* The timer counts down */
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# define TIMER_TBMR_TBCDIR_UP (1 << TIMER_TBMR_TBCDIR_SHIFT) /* When in one-shot or periodic mode, the timer counts up */
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# define TIMER_TBMR_TBMIE (1 << 5) /* Bit 5: Timer B Match Interrupt Enable */
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# define TIMER_TBMR_TBWOT (1 << 6) /* Bit 6: GPTM Timer B Wait-on-Trigger */
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# define TIMER_TBMR_TBSNAPS (1 << 7) /* Bit 7: GPTM Timer B Snap-Shot Mode */
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# define TIMER_TBMR_TBILD (1 << 8) /* Bit 8: GPTM Timer B Interval Load Write */
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# define TIMER_TBMR_TBPWMIE (1 << 9) /* Bit 9: GPTM Timer B PWM Interrupt Enable */
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# define TIMER_TBMR_TBMRSU (1 << 10) /* Bit 10: GPTM Timer B Match Register Update */
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# define TIMER_TBMR_TBPLO (1 << 11) /* Bit 11: GPTM Timer B PWM Legacy Operation */
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# define TIMER_TBMR_TBCINTD (1 << 12) /* Bit 12: One-shot/Periodic Interrupt Disable */
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# define TIMER_TBMR_TCACT_SHIFT (13) /* Bits 13-15: Timer Compare Action Select */
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# define TIMER_TBMR_TCACT_MASK (7 << TIMER_TBMR_TCACT_SHIFT)
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# define TIMER_TBMR_TCACT_NONE (0 << TIMER_TBMR_TCACT_SHIFT) /* Disable compare operations */
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# define TIMER_TBMR_TCACT_TOGGLE (1 << TIMER_TBMR_TCACT_SHIFT) /* Toggle state on timeout */
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# define TIMER_TBMR_TCACT_CLRTO (2 << TIMER_TBMR_TCACT_SHIFT) /* Clear CCP on timeout */
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# define TIMER_TBMR_TCACT_SETTO (3 << TIMER_TBMR_TCACT_SHIFT) /* Set CCP on timeout */
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# define TIMER_TBMR_TCACT_SETTOGTO (4 << TIMER_TBMR_TCACT_SHIFT) /* Set CCP and toggle on TimeOut */
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# define TIMER_TBMR_TCACT_CLRTOGTO (5 << TIMER_TBMR_TCACT_SHIFT) /* Clear CCP and toggle on TimeOut */
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# define TIMER_TBMR_TCACT_SETCLRTO (6 << TIMER_TBMR_TCACT_SHIFT) /* Set CCP and clear on timeout */
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# define TIMER_TBMR_TCACT_CLRSETTO (7 << TIMER_TBMR_TCACT_SHIFT) /* Clear CCP and set on timeout */
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#endif
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/* GPTM Control (CTL) */
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@ -460,10 +559,39 @@
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#define TIMER_CTL_TAEN (1 << 0) /* Bit 0: Timer A Enable */
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#define TIMER_CTL_TASTALL_SHIFT (1 << 1) /* Bit 1: Timer A Stall Enable */
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIMER_CTL_TAEVENT_SHIFT (2) /* Bits 2-3: GPTM Timer A Event Mode */
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# define TIMER_CTL_TAEVENT_MASK (3 << TIMER_CTL_TAEVENT_SHIFT)
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# define TIMER_CTL_TAEVENT_POS (0 << TIMER_CTL_TAEVENT_SHIFT) /* Positive edge */
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# define TIMER_CTL_TAEVENT_NEG (1 << TIMER_CTL_TAEVENT_SHIFT) /* Negative edge */
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# define TIMER_CTL_TAEVENT_BOTH (3 << TIMER_CTL_TAEVENT_SHIFT) /* Both edges */
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# define TIMER_CTL_RTCEN (1 << 4) /* Bit 4: GPTM RTC Stall Enable */
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# define TIMER_CTL_TAOTE (1 << 5) /* Bit 5: GPTM Timer A Output Trigger Enable */
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# define TIMER_CTL_TAPWML (1 << 6) /* Bit 6: GPTM Timer A PWM Output Level */
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# define TIMER_CTL_TBEN (1 << 8) /* Bit 8: GPTM Timer B Enable */
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# define TIMER_CTL_TBSTALL (1 << 9) /* Bit 9: GPTM Timer B Stall Enable */
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# define TIMER_CTL_TBEVENT_SHFIT (10) /* Bits 10-11: GPTM Timer B Event Mode */
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# define TIMER_CTL_TBEVENT_MASK (3 << TIMER_CTL_TBEVENT_SHFIT)
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# define TIMER_CTL_TBEVENT_POS (0 << TIMER_CTL_TBEVENT_SHFIT) /* Positive edge */
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# define TIMER_CTL_TBEVENT_NEG (1 << TIMER_CTL_TBEVENT_SHFIT) /* Negative edge */
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# define TIMER_CTL_TBEVENT_BOTH (3 << TIMER_CTL_TBEVENT_SHFIT) /* Both edges */
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# define TIMER_CTL_TBOTE (1 << 13) /* Bit 13: GPTM Timer B Output Trigger Enable */
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# define TIMER_CTL_TBPWML (1 << 14) /* Bit 14: GPTM Timer B PWM Output Level */
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#endif
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/* GPTM Synchronize */
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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# define TIMER_SYNC_
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#endif
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/* GPTM Interrupt Mask (IMR) */
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#define TIMER_IMR_TATOIM_SHIFT (1 << 0) /* Bit 0: Timer A Time-Out Interrupt Mask */
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#if defined(CONFIG_ARCH_CHIP_TM4C129XNC)
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#endif
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/* GPTM Raw Interrupt Status (RIS) */
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#define TIMER_RIS_TATORIS_SHIFT (1 << 0) /* Bit 0: Timer A Time-Out Raw Interrupt */
|
||||
|
||||
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Reference in New Issue
Block a user