diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_scu.h b/arch/arm/src/cxd56xx/hardware/cxd56_scu.h
index 224d29313d..307f4fec21 100644
--- a/arch/arm/src/cxd56xx/hardware/cxd56_scu.h
+++ b/arch/arm/src/cxd56xx/hardware/cxd56_scu.h
@@ -21,12 +21,8 @@
 #ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H
 #define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H
 
-#define SCU_PWM0_PARAM			(CXD56_SCU_BASE + 0x0000)
-#define SCU_PWM0_EN			(CXD56_SCU_BASE + 0x0004)
-#define SCU_PWM0_UPDATE			(CXD56_SCU_BASE + 0x0008)
-#define SCU_PWM1_PARAM			(CXD56_SCU_BASE + 0x000c)
-#define SCU_PWM1_EN			(CXD56_SCU_BASE + 0x0010)
-#define SCU_PWM1_UPDATE			(CXD56_SCU_BASE + 0x0014)
+#define SCU_DEBUG_I2C0			(CXD56_SCU_BASE + 0x0018)
+#define SCU_DEBUG_I2C1			(CXD56_SCU_BASE + 0x001c)
 #define SCU_SEQ_ENABLE_ALL		(CXD56_SCU_BASE + 0x0020)
 #define SCU_SEQ_ACCESS_INHIBIT		(CXD56_SCU_BASE + 0x0024)
 #define SCU_START_CTRL_COMMON		(CXD56_SCU_BASE + 0x0028)
@@ -178,5 +174,12 @@
 #define SCU_INT_RAW_STT_ERR_2		(CXD56_SCU_BASE + 0x046c)
 #define SCU_INT_MASKED_STT_ERR_2	(CXD56_SCU_BASE + 0x0470)
 #define SCU_RAM_TEST			(CXD56_SCU_BASE + 0x0500)
+#define SCU_POWER			(CXD56_SCU_BASE + 0x0510)
+#define SCU_INT_ENABLE_MAIN_AD		(CXD56_SCU_BASE + 0x0520)
+#define SCU_INT_DISABLE_MAIN_AD		(CXD56_SCU_BASE + 0x0524)
+#define SCU_INT_CLEAR_MAIN_AD		(CXD56_SCU_BASE + 0x0528)
+#define SCU_INT_LEVEL_SEL_MAIN_AD	(CXD56_SCU_BASE + 0x052c)
+#define SCU_INT_RAW_STT_MAIN_AD		(CXD56_SCU_BASE + 0x0530)
+#define SCU_INT_MASKED_STT_MAIN_AD	(CXD56_SCU_BASE + 0x0534)
 
 #endif /* __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCU_H */
diff --git a/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h b/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h
index 41fc417cea..6a1d399878 100644
--- a/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h
+++ b/arch/arm/src/cxd56xx/hardware/cxd56_scuseq.h
@@ -21,7 +21,11 @@
 #ifndef __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H
 #define __ARCH_ARM_SRC_CXD56XX_HARDWARE_CXD56_SCUSEQ_H
 
+#define SCUSEQ_SW_REVISION_DATE             (CXD56_SCU_SEQ_DRAM_BASE + 0x000)
+#define SCUSEQ_SW_REVISION_TIME             (CXD56_SCU_SEQ_DRAM_BASE + 0x004)
+#define SCUSEQ_SW_REVISION_GIT_HASH         (CXD56_SCU_SEQ_DRAM_BASE + 0x008)
 #define SCUSEQ_SRC_SEL                      (CXD56_SCU_SEQ_DRAM_BASE + 0x00c)
+#define SCUSEQ_REPEAT_TXABORT               (CXD56_SCU_SEQ_DRAM_BASE + 0x010)
 #define SCUSEQ_PROPERTY(s)                  (CXD56_SCU_SEQ_DRAM_BASE + 0x020 + ((s) * 0x20))
 #define SCUSEQ_OUT_FORMAT(s)                (CXD56_SCU_SEQ_DRAM_BASE + 0x024 + ((s) * 0x20))
 #define SCUSEQ_MATH_PROC_OFST_GAIN_X(s)     (CXD56_SCU_SEQ_DRAM_BASE + 0x028 + ((s) * 0x20))