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stm32f7:serial TXDMA ISR was looping on TX Empty

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Interrups were blocked 1*n/baud Seconds. The former comment indicates
   there was an asumption that the TXE would be set at DMA completion.
   In reality this is not true. There can be 1 char in the TX Shift
   register and one in the TX holding register, when DMA completes.
   Waiting on TXE is not needed at all. The DMA will resume on the
   DMA req when the TX holding register is written to the TX Shift
   register.
This commit is contained in:
David Sidrane 2020-08-10 10:40:29 -07:00 committed by Xiang Xiao
parent 562be9e4c7
commit a10e9615ca
1 changed files with 0 additions and 4 deletions
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arch/arm/src/stm32f7/stm32_serial.c
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@ -3181,10 +3181,6 @@ static void up_dma_send(struct uart_dev_s *dev)
stm32_dmastop(priv->txdma);
/* Wait until TX UART is ready for new transfer it should be */
while (!up_txready(dev));
/* Flush the contents of the TX buffer into physical memory */
up_clean_dcache((uintptr_t)dev->dmatx.buffer,