Add AVR32 system timer
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3021 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
d01bbeb562
commit
a117c6bc8e
@ -52,7 +52,8 @@ CMN_CSRCS = up_assert.c up_allocateheap.c up_blocktask.c up_copystate.c \
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CHIP_ASRCS =
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CHIP_CSRCS = at91uc3_clkinit.c at91uc3_gpio.c at91uc3_irq.c \
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at91uc3_lowconsole.c at91uc3_lowinit.c at91uc3_serial.c
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at91uc3_lowconsole.c at91uc3_lowinit.c at91uc3_serial.c \
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at91uc3_timerisr.c
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# Configuration-dependent AT91UC3 files
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@ -73,18 +73,43 @@
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**************************************************************************/
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/**************************************************************************
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* Public Functions
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**************************************************************************/
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/************************************************************************************
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* Name: up_clkinit
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* Name: up_enableosc32
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*
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* Description:
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* Initialiaze clock/PLL settings per the definitions in the board.h file.
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* Initialiaze the 32KHz oscillaor. This oscillaor is used by the RTC
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* logic to provide the sysem timer.
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*
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************************************************************************************/
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**************************************************************************/
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void up_clkinitialize(void)
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static inline void up_enableosc32(void)
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{
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uint32_t regval;
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/* Select the 32KHz oscillator crystal */
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regval = getreg32(AVR32_PM_OSCCTRL32);
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regval &= ~PM_OSCCTRL32_MODE_MASK;
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regval |= PM_OSCCTRL32_MODE_XTAL;
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putreg32(regval, AVR32_PM_OSCCTRL32);
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/* Enable the 32-kHz clock */
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regval = getreg32(AVR32_PM_OSCCTRL32);
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regval &= ~PM_OSCCTRL_STARTUP_MASK;
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regval |= PM_OSCCTRL32_EN|(AVR32_OSC32STARTUP << PM_OSCCTRL_STARTUP_SHIFT);
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putreg32(regval, AVR32_PM_OSCCTRL32);
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}
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/**************************************************************************
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* Name: up_enableosc0
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*
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* Description:
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* Initialiaze clock/PLL settings per the definitions in the board.h
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* file.
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*
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**************************************************************************/
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static inline void up_enableosc0(void)
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{
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uint32_t regval;
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@ -121,16 +146,60 @@ void up_clkinitialize(void)
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/* Wait for CLK0 to be ready */
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while ((getreg32(AVR32_PM_POSCSR) & PM_POSCSR_OSC0RDY) == 0);
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}
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/* Then switch the main clock to OSC0 */
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/**************************************************************************
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* Name: up_mainclk
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*
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* Description:
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* Initialiaze clock/PLL settings per the definitions in the board.h
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* file.
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*
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**************************************************************************/
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static inline void up_mainclk(uint32_t mcsel)
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{
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uint32_t regval;
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regval = getreg32(AVR32_PM_MCCTRL);
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regval &= ~PM_MCCTRL_MCSEL_MASK;
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regval |= PM_MCCTRL_MCSEL_OSC0;
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regval |= mcsel;
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putreg32(regval, AVR32_PM_MCCTRL);
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}
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/* Now, enable PLL0 */
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#warning "Missing Logic"
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/**************************************************************************
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* Public Functions
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**************************************************************************/
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/**************************************************************************
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* Name: up_clkinit
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*
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* Description:
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* Initialiaze clock/PLL settings per the definitions in the board.h
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* file.
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*
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**************************************************************************/
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void up_clkinitialize(void)
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{
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/* Enable the 32KHz oscillator (need by the RTC module) */
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up_enableosc32();
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#if defined(AVR32_CLOCK_OSC0)
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/* Enable OSC0 using the settings in board.h */
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up_enableosc0();
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/* Then switch the main clock to OSC0 */
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up_mainclk(PM_MCCTRL_MCSEL_OSC0);
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#elif defined(AVR32_CLOCK_PLL0)
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# warning "Missing Logic"
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#else
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# error "No main clock"
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#endif
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}
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@ -179,7 +179,7 @@
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#define PM_OSCCTRL32_MODE_SHIFT (8) /* Bits 8-10: Oscillator Mode */
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#define PM_OSCCTRL32_MODE_MASK (7 << PM_OSCCTRL32_MODE_SHIFT)
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# define PM_OSCCTRL32_MODE_EXT (0 << PM_OSCCTRL32_MODE_SHIFT) /* External clock */
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# define PM_OSCCTRL32_MODE_XTALp9 (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */
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# define PM_OSCCTRL32_MODE_XTAL (1 << PM_OSCCTRL32_MODE_SHIFT) /* Crystal */
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#define PM_OSCCTRL32_STARTUPSHIFT (16) /* Bits 16-18: Oscillator Startup Time */
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#define PM_OSCCTRL32_STARTUP_MASK (7 << PM_OSCCTRL32_STARTUP_SHIFT)
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# define PM_OSCCTRL32_STARTUP_0 (0 << PM_OSCCTRL32_STARTUP_SHIFT) /* Num RCOsc cycles */
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@ -196,7 +196,6 @@
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/* Interrupt Status Register Bit-field Definitions */
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/* Interrupt Clear Register Bit-field Definitions */
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#define PM_INT_LOCK0 (1 << 0) /* Bit 0: PLL0 locked */
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#define PM_INT_LOCK1 (1 << 1) /* Bit 1: PLL1 locked */
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#define PM_INT_CKRDY (1 << 5) /* Bit 5: Clock Ready */
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@ -733,7 +733,9 @@ static bool up_txready(struct uart_dev_s *dev)
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* Description:
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* Performs the low level USART initialization early in debug so that the
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* serial console will be available during bootup. This must be called
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* before up_serialinit.
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* before up_serialinit. NOTE: This function depends on GPIO pin
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* configuration performed in up_consoleinit() and main clock iniialization
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* performed in up_clkinitialize().
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*
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****************************************************************************/
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190
arch/avr/src/at91uc3/at91uc3_timerisr.c
Normal file
190
arch/avr/src/at91uc3/at91uc3_timerisr.c
Normal file
@ -0,0 +1,190 @@
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/****************************************************************************
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* arch/avr/src/at91uc3/at91uc3_timerisr.c
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "at91uc3_internal.h"
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#include "at91uc3_rtc.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* The desired timer interrupt frequency is normally provided by the
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* definition CLK_TCK (see include/time.h). CLK_TCK defines the desired
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* number of system clock ticks per second. That value is a user configurable
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* setting that defaults to 100 (100 ticks per second = 10 MS interval).
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*
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* However, the AVR RTC does not support that default value well and so, we
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* will insist that default is over-ridden by CONFIG_TICKS_PER_MSEC in the
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* configuration file. Further, we will insist that CONFIG_TICKS_PER_MSEC
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* have the value 8 (see reasoning below).
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*/
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#if defined(CONFIG_MSEC_PER_TICK) && CONFIG_MSEC_PER_TICK != 10
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# error "Only a 100KHz system clock is supported"
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#endif
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/* The frequency of the RTC is given by:
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*
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* fRTC = fINPUT / 2**(PSEL + 1)
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*
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* Using the 32KHz clock, various RTC counting can be obtained:
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*
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* fRTC = 32000 / 2**16 = 32000/65536 = 0.49Hz -> 2048 ms per tick
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* fRTC = 32000 / 2**15 = 32000/32768 = 0.98Hz -> 1024 ms per tick
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* fRTC = 32000 / 2**14 = 32000/16384 = 1.95Hz -> 512 ms per tick
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* fRTC = 32000 / 2**13 = 32000/8192 = 3.9Hz -> 256 ms per tick
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* fRTC = 32000 / 2**12 = 32000/4096 = 7.8Hz -> 128 ms per tick
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* fRTC = 32000 / 2**11 = 32000/2048 = 15.6Hz -> 64 ms per tick
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* fRTC = 32000 / 2**10 = 32000/1024 = 31.3Hz -> 32 ms per tick
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* fRTC = 32000 / 2**9 = 32000/512 = 62.5Hz -> 16 ms per tick
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* fRTC = 32000 / 2**8 = 32000/256 = 125Hz -> 8 ms per tick
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* fRTC = 32000 / 2**7 = 32000/128 = 250Hz -> 4 ms per tick
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* fRTC = 32000 / 2**6 = 32000/64 = 500Hz -> 2 ms per tick
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* fRTC = 32000 / 2**5 = 32000/32 = 1KHz -> 1 ms per tick
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* fRTC = 32000 / 2**4 = 32000/16 = 2KHz -> 500 us per tick
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* fRTC = 32000 / 2**3 = 32000/8 = 4KHz -> 250 us per tick
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* fRTC = 32000 / 2**2 = 32000/4 = 8KHz -> 125 us per tick
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* fRTC = 32000 / 2 = 16KHz -> 62.5 us per tick
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*
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* We'll use PSEL == 1 (fRTC == 125ns) and we will set TOP to 79.
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* Therefore, the TOP interrupt should occur after 79+1=80 counts
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* at a rate of 125us x 80 = 10 ms
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*/
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#define AV32_PSEL 15
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#define AV32_TOP (80-1)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Function: rtc_busy
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*
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* Description:
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* Make sure that the RTC is no busy before trying to operate on it. If
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* the RTC is busy, it will discard writes to TOP, VAL, and CTRL.
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*
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****************************************************************************/
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static void rtc_waitnotbusy(void)
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{
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while ((getreg32(AVR32_RTC_CTRL) & RTC_CTRL_BUSY) == 0);
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}
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/****************************************************************************
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* Global Functions
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****************************************************************************/
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/****************************************************************************
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* Function: up_timerisr
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*
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* Description:
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* The timer ISR will perform a variety of services for various portions
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* of the systems.
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*
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****************************************************************************/
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int up_timerisr(int irq, uint32_t *regs)
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{
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/* Clear the pending timer interrupt */
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putreg32(RTC_INT_TOPI, AVR32_RTC_ICR);
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/* Process timer interrupt */
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sched_process_timer();
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return 0;
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}
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/****************************************************************************
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* Function: up_timerinit
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*
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* Description:
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* This function is called during start-up to initialize the timer
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* interrupt. NOTE: This function depends on setup of OSC32 by
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* up_clkinitialize().
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*
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****************************************************************************/
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void up_timerinit(void)
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{
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uint32_t regval;
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/* Configure the RTC. Source == 32KHz OSC32 */
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rtc_waitnotbusy();
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putreg32((RTC_CTRL_CLK32 | (AV32_PSEL << RTC_CTRL_PSEL_SHIFT) | RTC_CTRL_CLKEN),
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AVR32_RTC_CTRL);
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/* Set the counter value to zero and the TOP value to AVR32_TOP (see above) */
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rtc_waitnotbusy();
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putreg32(0, AVR32_RTC_VAL);
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putreg32(AV32_TOP, AVR32_RTC_TOP);
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/* Attach the timer interrupt vector */
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(void)irq_attach(AVR32_IRQ_RTC, (xcpt_t)up_timerisr);
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/* Enable RTC interrupts */
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putreg32(RTC_INT_TOPI, AVR32_RTC_IER);
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/* Enable the RTC */
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rtc_waitnotbusy();
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regval = getreg32(AVR32_RTC_CTRL);
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regval |= RTC_CTRL_EN;
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putreg32(regval, AVR32_RTC_CTRL);
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}
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@ -57,7 +57,7 @@
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#endif
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.global up_lowinit /* Perform low level initialization */
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.global os_start /* NuttX entry point */
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.global vectors /* Vector base address */
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.global vectortab /* Vector base address */
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/****************************************************************************
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* Macros
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@ -85,7 +85,7 @@ __start:
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/* Set up the vector base address so interrupts can be enabled. */
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lda.w r0, vectors
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lda.w r0, .Lvectortab
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mtsr AVR32_EVBA, r0
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/* Enable exception processing */
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@ -137,7 +137,9 @@ __start:
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rjmp os_start
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.Lstackbase:
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.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
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.word _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
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.Lvectortab:
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.word vectortab
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.size __start, .-__start
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/* This global variable is unsigned long g_heapbase and is
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123
arch/avr/src/avr32/up_switchcontext.S
Executable file
123
arch/avr/src/avr32/up_switchcontext.S
Executable file
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/************************************************************************************
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* arch/avr/src/avr32/up_switchcontext.S
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/avr32/avr32.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Global Symbols
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************************************************************************************/
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.file "up_switchcontext.S"
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/************************************************************************************
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* Macros
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: up_switchcontext
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*
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* Description:
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* Save the current thread context and restore the specified context. The full
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* C function prototype is:
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*
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* void up_switchcontext(uint32_t *saveregs, uint32_t *restoreregs);
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*
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* Return:
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* up_switchcontext forces a context switch to the task "canned" in restoreregs.
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* It does not 'return' in the normal sense, rather, it will context switch back
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* to the function point. When it does 'return,' it is because the blocked
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* task hat was "pickeled" in the saveregs "can" is again ready to run and has
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* execution priority.
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*
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* Assumptions:
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* global interrupts disabled by the caller.
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*
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************************************************************************************/
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.text
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.globl up_switchcontext
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.type up_switchcontext, @function
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up_switchcontext:
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/* "Pickle" the current thread context in the saveregs "can." r12=saveregs. */
|
||||
/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx */
|
||||
/* ^r12 */
|
||||
/* Sample SR and set r12 to just after the LR storage location. */
|
||||
/* xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx */
|
||||
/* ^r12 */
|
||||
|
||||
mfsr r10, AVR32_SR
|
||||
sub r12, -4*(REG_LR+1)
|
||||
|
||||
/* Then "push" PC=LR, LR, SR, and SP as ther are on entry. */
|
||||
/* xx xx xx xx xx xx xx xx SP SR PC LR xx xx xx xx xx */
|
||||
/* ^r12 */
|
||||
|
||||
st.w --r12, lr
|
||||
st.w --r12, lr
|
||||
st.w --r12, r10
|
||||
st.w --r12, sp
|
||||
|
||||
/* Save the preserved/static registers, r0-r7. There is no reason to save the */
|
||||
/* scratch/volatile registers, r8-r12, in this context. */
|
||||
/* 07 06 05 04 03 02 01 00 SP SR PC LR xx xx xx xx xx */
|
||||
/* ^r12 */
|
||||
|
||||
stm --r12, r0-r7
|
||||
|
||||
/* Finally, let up_fullcontextrestore handling the re-instatement of the thread */
|
||||
/* "canned" in restoregs. */
|
||||
|
||||
mov r12, r11
|
||||
lddpc pc, .Lup_fullcontextrestore
|
||||
|
||||
.Lup_fullcontextrestore:
|
||||
.word up_fullcontextrestore
|
||||
.size up_switchcontext, .-up_switchcontext
|
||||
.end
|
||||
|
||||
@ -50,16 +50,21 @@
|
||||
/* Clocking *************************************************************************/
|
||||
/* #define AVR32_FRCOSC 15200 RCOsc frequency in Hz */
|
||||
|
||||
#define AVR32_FOSC32 32768 /* Osc32 frequency in Hz */
|
||||
#define AVR32_OSC32STARTUP 3 /* Osc32 startup time in RCOsc periods */
|
||||
#define AVR32_FOSC32 32768 /* OSC32 frequency in Hz */
|
||||
#define AVR32_OSC32STARTUP 3 /* OSC32 startup time in RCOsc periods */
|
||||
|
||||
#define AVR32_FOSC0 12000000 /* Osc0 frequency in Hz */
|
||||
#define AVR32_OSC0STARTUP 3 /* Osc0 startup time in RCOsc periods.
|
||||
#define AVR32_FOSC0 12000000 /* OSC0 frequency in Hz */
|
||||
#define AVR32_OSC0STARTUP 3 /* OSC0 startup time in RCOsc periods.
|
||||
|
||||
/* #define AVR32_FOSC1 12000000 Osc1 frequency: Hz.
|
||||
* #define AVR32_OSC1STARTUP 3 Osc1 startup time in RCOsc periods.
|
||||
/* #define AVR32_FOSC1 12000000 OSC1 frequency: Hz.
|
||||
* #define AVR32_OSC1STARTUP 3 OSC1 startup time in RCOsc periods.
|
||||
*/
|
||||
|
||||
/* Select OSC0 as the main clock */
|
||||
|
||||
#define AVR32_CLOCK_OSC0 1
|
||||
#undef AVR32_CLOCK_PLL0
|
||||
|
||||
#define AVR32_CPU_CLOCK AVR32_FOSC0
|
||||
#define AVR32_PBA_CLOCK AVR32_FOSC0
|
||||
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/********************************************************************************
|
||||
* include/time.h
|
||||
*
|
||||
* Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2007-2010 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
|
||||
Loading…
Reference in New Issue
Block a user