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arch/arm/stm32: Make SysTick as a Tickless clock source option

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2020-06-20 11:54:51 +08:00 committed by Alan Carvalho de Assis
parent b64060f717
commit a13ebe5975
3 changed files with 28 additions and 4 deletions
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8
arch/arm/src/stm32/Kconfig
View File

@ -3421,6 +3421,13 @@ config STM32_EXTERNAL_RAM
---help---
In addition to internal SRAM, external RAM may be available through the FSMC/FMC.
config STM32_TICKLESS_SYSTICK
bool "Tickless via SysTick"
default n
depends on SCHED_TICKLESS
---help---
Use SysTick as Tickless clock.
menu "Timer Configuration"
depends on STM32_TIM
@ -3430,6 +3437,7 @@ config STM32_TICKLESS_TIMER
int "Tickless hardware timer"
default 2
range 1 14
depends on !STM32_TICKLESS_SYSTICK
---help---
If the Tickless OS feature is enabled, then one clock must be
assigned to provided the timer needed by the OS.

16
arch/arm/src/stm32/Make.defs
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@ -44,13 +44,21 @@ endif
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_createstack.c
CMN_CSRCS += arm_exit.c arm_hardfault.c arm_initialize.c arm_initialstate.c
CMN_CSRCS += arm_interruptcontext.c arm_mdelay.c arm_memfault.c arm_modifyreg8.c
CMN_CSRCS += arm_interruptcontext.c arm_memfault.c arm_modifyreg8.c
CMN_CSRCS += arm_modifyreg16.c arm_modifyreg32.c arm_releasepending.c
CMN_CSRCS += arm_releasestack.c arm_reprioritizertr.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackframe.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_unblocktask.c arm_udelay.c arm_usestack.c
CMN_CSRCS += arm_doirq.c arm_vfork.c
ifeq ($(CONFIG_STM32_TICKLESS_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifneq ($(CONFIG_TIMER_ARCH),y)
CMN_CSRCS += arm_mdelay.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
@ -104,10 +112,10 @@ ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
endif
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
else
ifdef CONFIG_STM32_TICKLESS_TIMER
CHIP_CSRCS += stm32_tickless.c
else
CHIP_CSRCS += stm32_timerisr.c
endif
ifeq ($(CONFIG_STM32_ONESHOT),y)

8
arch/arm/src/stm32/stm32_timerisr.c
View File

@ -43,12 +43,14 @@
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/arch_timer.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "arm_arch.h"
#include "systick.h"
#include "chip.h"
#include "stm32.h"
@ -98,6 +100,7 @@
*
****************************************************************************/
#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
@ -105,6 +108,7 @@ static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
nxsched_process_timer();
return 0;
}
#endif
/****************************************************************************
* Public Functions
@ -142,6 +146,9 @@ void up_timer_initialize(void)
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
up_timer_set_lowerhalf(systick_initialize(true, STM32_HCLK_FREQUENCY, -1));
#else
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
@ -158,4 +165,5 @@ void up_timer_initialize(void)
/* And enable the timer interrupt */
up_enable_irq(STM32_IRQ_SYSTICK);
#endif
}