stm32f33xxx: Add COMP header file
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arch/arm/src/stm32/chip/stm32f33xxx_comp.h
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arch/arm/src/stm32/chip/stm32f33xxx_comp.h
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32f33xxx_comp.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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#define STM32_COMP2_CSR_OFFSET 0x0020 /* COMP2 Control register */
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#define STM32_COMP4_CSR_OFFSET 0x0028 /* COMP4 Control register */
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#define STM32_COMP6_CSR_OFFSET 0x0030 /* COMP6 Control register */
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/* Register Addresses *******************************************************************************/
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#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET)
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#define STM32_COMP4_CSR (STM32_COMP_BASE+STM32_COMP4_CSR_OFFSET)
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#define STM32_COMP6_CSR (STM32_COMP_BASE+STM32_COMP6_CSR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* COMP control and status register */
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#define COMP_CSR_COMPEN (1 << 0) /* Bit 0: Comparator enable */
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/* Bits 1-3: Reserved */
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#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 4-6: Comparator inverting input selection */
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#define COMP_CSR_INMSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT)
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# define COMP_CSR_INMSEL_1P4VREF (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: 1/4 of Vrefint */
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# define COMP_CSR_INMSEL_1P2VREF (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: 1/2 of Vrefint */
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# define COMP_CSR_INMSEL_3P4VREF (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: 3/4 of Vrefint */
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# define COMP_CSR_INMSEL_VREF (3 << COMP_CSR_INMSEL_SHIFT) /* 0011: Vrefint */
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# define COMP_CSR_INMSEL_PA4 (4 << COMP_CSR_INMSEL_SHIFT) /* 0100: PA4 or DAC1_CH output if enabled */
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# define COMP_CSR_INMSEL_DAC1CH2 (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: DAC1_CH2 output */
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# define COMP_CSR_INMSEL_PA2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: PA2 (COMP2 only) */
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# define COMP_CSR_INMSEL_PB2 (7 << COMP4_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */
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# define COMP_CSR_INMSEL_PB15 (7 << COMP6_CSR_INMSEL_SHIFT) /* 0110: PB15 (COMP6 only) */
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/* 1000: DAC2_CH1 output, look at bit 22 */
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/* Bits 7-9: Reserved */
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#define COMP_CSR_OUTSEL_SHIFT (4) /* Bits 10-13: Comparator output selection */
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#define COMP_CSR_OUTSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT)
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# define COMP_CSR_OUTSEL_NOSEL (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: No selection */
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# define COMP_CSR_OUTSEL_BRKACTH (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: Timer 1 break input */
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# define COMP_CSR_OUTSEL_BRK2 (2 << COMP_CSR_INMSEL_SHIFT) /* 0010: Timer 1 break input 2 */
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/* 0011: Reserved */
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/* 0100: Reserved */
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# define COMP_CSR_OUTSEL_BRK2_ (5 << COMP_CSR_INMSEL_SHIFT) /* 0101: Timer 1 break input2 */
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# define COMP_CSR_OUTSEL_T1OCCC (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 1 OCREF_CLR input (COMP2 only) */
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# define COMP_CSR_OUTSEL_T3CAP3 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 3 input apture 3 (COMP4 only) */
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# define COMP_CSR_OUTSEL_T2CAP2 (6 << COMP_CSR_INMSEL_SHIFT) /* 0110: Timer 2 input apture 2 (COMP6 only) */
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# define COMP_CSR_OUTSEL_T1CAP1 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: Timer 1 input capture 1 (COMP2 only) */
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# define COMP_CSR_OUTSEL_T2CAP4 (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 input capture 4 (COMP2 only) */
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# define COMP_CSR_OUTSEL_T15CAP2 (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 15 input capture 2 (COMP4 only) */
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# define COMP_CSR_OUTSEL_T2OCC (8 << COMP_CSR_INMSEL_SHIFT) /* 1000: Timer 2 OCREF CLR input (COMP6 only) */
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# define COMP_CSR_OUTSEL_T2OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 2 OCREF_CLR input (COMP2 only) */
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# define COMP_CSR_OUTSEL_T16OCC (9 << COMP_CSR_INMSEL_SHIFT) /* 1001: Timer 16 OCREF_CLR input (COMP6 only) */
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# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 3 input capture 1 (COMP2 only) */
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# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */
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# define COMP_CSR_OUTSEL_T3CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */
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# define COMP_CSR_OUTSEL_T3OCC (11 << COMP_CSR_INMSEL_SHIFT) /* 1011: Timer 3 OCREF_CLR input (COMP2,COMP4 only) */
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/* Bit 14: Reserved */
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#define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */
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/* Bits 16-17: Reserved */
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#define COMP_CSR_BLANCKING_SHIFT (18) /* Bit 18-20: comparator output blanking source */
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#define COMP_CSR_BLANCKING_MASK (7 << COMP_CSR_BLANCKING_SHIFT)
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# define COMP_CSR_BLANCKING_DIS (0 << COMP_CSR_BLANCKING_SHIFT) /* 000: No blanking */
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# define COMP_CSR_BLANCKING_T1OC5 (1 << COMP_CSR_BLANCKING_SHIFT) /* 001: TIM1 OC5 as blanking source (COMP2 only) */
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# define COMP_CSR_BLANCKING_T3OC4 (1 << COMP_CSR_BLANCKING_SHIFT) /* 001: TIM3 OC4 as blanking source (COMP4 only) */
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# define COMP_CSR_BLANCKING_T2OC3 (2 << COMP_CSR_BLANCKING_SHIFT) /* 010: TIM2 OC3 as blanking source (COMP2 only) */
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# define COMP_CSR_BLANCKING_T3OC3 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM3 OC3 as blanking source (COMP2 only) */
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# define COMP_CSR_BLANCKING_T15OC1 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM15 OC1 as blanking source (COMP4 only) */
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# define COMP_CSR_BLANCKING_T2OC4 (3 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM2 OC4 as blanking source (COMP6 only) */
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# define COMP_CSR_BLANCKING_T15OC2 (4 << COMP_CSR_BLANCKING_SHIFT) /* 011: TIM15 OC2 as blanking source (COMP6 only) */
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/* Bit 21: Reserved */
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#define COMP_CSR_INMSEL_DAC2CH1 (1 << 22) /* Bit 22: used with bits 4-6, DAC2_CH1 output */
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/* Bits 23-29: Reserved */
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#define COMP_CSR_OUT (1 << 30) /* Bit 30: comparator output */
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#define COMP_CSR_LOCK (1 << 31) /* Bit 31: comparator lock */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_COMP_H */
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