SAM3U-EK board now runs at 96MHz
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Gregory Nutt
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5ed3283b02
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a168132901
@ -2,7 +2,8 @@ README
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^^^^^^
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This README discusses issues unique to NuttX configurations for the Atmel
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SAM3U-EK development board featuring the ATAM3U
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SAM3U-EK development board featuring the ATAM3U. This board features the
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AT91SAM3U4E MCU running at 96MHz.
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Contents
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^^^^^^^^
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@ -55,21 +55,38 @@
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/* Clocking *************************************************************************/
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/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These
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* definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz.
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* definitions will configure clocking
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*
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* MAINOSC: Frequency = 12MHz (crysta)
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* PLLA: PLL Divider = 1, Multiplier = 16 to generate PLLACK = 192MHz
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* Master Clock (MCK): Source = PLLACK, Prescalar = 1 to generate MCK = 96MHz
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* CPU clock: 96MHz
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*/
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/* Main oscillator register settings */
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/* Main oscillator register settings.
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*
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* The start up time should be should be:
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (63 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multipler = 16
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*/
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#define BOARD_CKGR_PLLAR_MUL (7 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_MUL (15 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_STMODE PMC_CKGR_PLLAR_STMODE_FAST
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings */
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/* PMC master clock register settings.
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*
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* Source = PLLA
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* Divider = 2
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
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@ -80,10 +97,10 @@
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/* Resulting frequencies */
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#define BOARD_MAINOSC_FREQUENCY (12000000)
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#define BOARD_MCK_FREQUENCY (48000000)
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#define BOARD_PLLA_FREQUENCY (96000000)
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#define BOARD_CPU_FREQUENCY (48000000)
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#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */
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#define BOARD_PLLA_FREQUENCY (192000000) /* PLLACK: 16 * 12Mhz / 1 */
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#define BOARD_MCK_FREQUENCY (96000000) /* MCK: PLLACK / 2 */
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#define BOARD_CPU_FREQUENCY (96000000) /* CPU: MCK */
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/* HSMCI clocking
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*
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@ -92,24 +109,35 @@
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*
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* MCI_SPEED = MCK / (2*(CLKDIV+1))
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* CLKDIV = MCI / MCI_SPEED / 2 - 1
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* MCK = 48MHz, CLKDIV = 59, MCI_SPEED = 48MHz / 2 * (59+1) = 400 KHz */
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/* MCK = 96MHz, CLKDIV = 119, MCI_SPEED = 96MHz / 2 * (119+1) = 400 KHz */
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#define HSMCI_INIT_CLKDIV (59 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_INIT_CLKDIV (119 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 1, MCI_SPEED = 48MHz / 2 * (1+1) = 12 MHz */
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/* MCK = 96MHz, CLKDIV = 3, MCI_SPEED = 96MHz / 2 * (3+1) = 12 MHz */
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#define HSMCI_MMCXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 48MHz, CLKDIV = 0, MCI_SPEED = 48MHz / 2 * (0+1) = 24 MHz */
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/* MCK = 96MHz, CLKDIV = 1, MCI_SPEED = 96MHz / 2 * (1+1) = 24 MHz */
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#define HSMCI_SDXFR_CLKDIV (0 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDXFR_CLKDIV (3 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/* FLASH wait states */
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/* FLASH wait states
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*
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* FWS Max frequency
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* 1.62V 1.8V
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* --- ----- ------
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* 0 24MHz 27MHz
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* 1 40MHz 47MHz
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* 2 72MHz 84MHz
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* 3 84MHz 96MHz
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*/
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#define BOARD_FWS 2
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#define BOARD_FWS 3
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/* LED definitions ******************************************************************/
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@ -193,7 +193,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
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#
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# Board Settings
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#
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CONFIG_BOARD_LOOPSPERMSEC=4768
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CONFIG_BOARD_LOOPSPERMSEC=8720
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# CONFIG_ARCH_CALIBRATION is not set
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CONFIG_DRAM_START=0x20000000
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CONFIG_DRAM_SIZE=32768
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@ -185,7 +185,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
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#
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# Board Settings
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#
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CONFIG_BOARD_LOOPSPERMSEC=4768
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CONFIG_BOARD_LOOPSPERMSEC=8720
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# CONFIG_ARCH_CALIBRATION is not set
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CONFIG_DRAM_START=0x20000000
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CONFIG_DRAM_SIZE=32768
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@ -185,7 +185,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
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#
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# Board Settings
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#
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CONFIG_BOARD_LOOPSPERMSEC=4768
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CONFIG_BOARD_LOOPSPERMSEC=8720
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# CONFIG_ARCH_CALIBRATION is not set
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CONFIG_DRAM_START=0x20000000
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CONFIG_DRAM_SIZE=32768
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@ -185,7 +185,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
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#
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# Board Settings
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#
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CONFIG_BOARD_LOOPSPERMSEC=4768
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CONFIG_BOARD_LOOPSPERMSEC=8720
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# CONFIG_ARCH_CALIBRATION is not set
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CONFIG_DRAM_START=0x20000000
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CONFIG_DRAM_SIZE=32768
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