diff --git a/arch/arm/include/xmc4/xmc4500_irq.h b/arch/arm/include/xmc4/xmc4500_irq.h
index b35a1b3f8a..556af56422 100644
--- a/arch/arm/include/xmc4/xmc4500_irq.h
+++ b/arch/arm/include/xmc4/xmc4500_irq.h
@@ -171,12 +171,12 @@
 #define XMC4_IRQ_USIC1_SR3  (XMC4_IRQ_FIRST+93)  /*  93: USIC1 Channel, SR3 */
 #define XMC4_IRQ_USIC1_SR4  (XMC4_IRQ_FIRST+94)  /*  94: USIC1 Channel, SR4 */
 #define XMC4_IRQ_USIC1_SR5  (XMC4_IRQ_FIRST+95)  /*  95: USIC1 Channel, SR5 */
-#define XMC4_IRQ_USIC2_SR0  (XMC4_IRQ_FIRST+96)  /*  96: USIC1 Channel, SR0 */
-#define XMC4_IRQ_USIC2_SR1  (XMC4_IRQ_FIRST+97)  /*  97: USIC1 Channel, SR1 */
-#define XMC4_IRQ_USIC2_SR2  (XMC4_IRQ_FIRST+98)  /*  98: USIC1 Channel, SR2 */
-#define XMC4_IRQ_USIC2_SR3  (XMC4_IRQ_FIRST+99)  /*  99: USIC1 Channel, SR3 */
-#define XMC4_IRQ_USIC2_SR4  (XMC4_IRQ_FIRST+100) /* 100: USIC1 Channel, SR4 */
-#define XMC4_IRQ_USIC2_SR5  (XMC4_IRQ_FIRST+101) /* 101: USIC1 Channel, SR5 */
+#define XMC4_IRQ_USIC2_SR0  (XMC4_IRQ_FIRST+96)  /*  96: USIC2 Channel, SR0 */
+#define XMC4_IRQ_USIC2_SR1  (XMC4_IRQ_FIRST+97)  /*  97: USIC2 Channel, SR1 */
+#define XMC4_IRQ_USIC2_SR2  (XMC4_IRQ_FIRST+98)  /*  98: USIC2 Channel, SR2 */
+#define XMC4_IRQ_USIC2_SR3  (XMC4_IRQ_FIRST+99)  /*  99: USIC2 Channel, SR3 */
+#define XMC4_IRQ_USIC2_SR4  (XMC4_IRQ_FIRST+100) /* 100: USIC2 Channel, SR4 */
+#define XMC4_IRQ_USIC2_SR5  (XMC4_IRQ_FIRST+101) /* 101: USIC2 Channel, SR5 */
 #define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */
 #define XMC4_IRQ_RESVD103   (XMC4_IRQ_FIRST+103) /* 103: Reserved */
 #define XMC4_IRQ_FCR_SR0    (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */
diff --git a/arch/arm/src/xmc4/chip/xmc4_usic.h b/arch/arm/src/xmc4/chip/xmc4_usic.h
index 274d0fae53..0ca992d548 100644
--- a/arch/arm/src/xmc4/chip/xmc4_usic.h
+++ b/arch/arm/src/xmc4/chip/xmc4_usic.h
@@ -477,7 +477,7 @@
 #  define USIC_INPR_TSINP_SR3       (3 << USIC_INPR_TSINP_SHIFT) /* Output SR3 activated */
 #  define USIC_INPR_TSINP_SR4       (4 << USIC_INPR_TSINP_SHIFT) /* Output SR4 activated */
 #  define USIC_INPR_TSINP_SR5       (5 << USIC_INPR_TSINP_SHIFT) /* Output SR5 activated */
-#define USIC_INPR_TBINP_SHIFT       (4)       /* Bits 4-6: Transmit Buffer Interrupt Node Poi */
+#define USIC_INPR_TBINP_SHIFT       (4)       /* Bits 4-6: Transmit Buffer Interrupt Node Pointer */
 #define USIC_INPR_TBINP_MASK        (7 << USIC_INPR_TBINP_SHIFT)
 #  define USIC_INPR_TBINP_SR0       (0 << USIC_INPR_TBINP_SHIFT) /* Output SR0 activated */
 #  define USIC_INPR_TBINP_SR1       (1 << USIC_INPR_TBINP_SHIFT) /* Output SR1 activated */