Changes to resulting previous merge of arch/c5471 and arch/dm320 into arch/arm and
also to adding lpc214x to arch/arm. git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@194 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
af000ee096
commit
a19bd351b5
@ -146,8 +146,15 @@ arch/arm
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NuttX operates on the ARM9EJS of this dual core processor. This port
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NuttX operates on the ARM9EJS of this dual core processor. This port
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complete, verified, and included in the NuttX release 0.2.1.
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complete, verified, and included in the NuttX release 0.2.1.
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arch/arm/include/lpc214x and arch/arm/src/lpc214x
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These directories provide support for NXP LPC214x family of
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processors.
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STATUS: This port is in progress and should be available in the
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nuttx-0.2.5 release.
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arch/m68322
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arch/m68322
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A work in progress.
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A work in progress.
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STATUS: Stalled for the moment.
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arch/pjrc-8051
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arch/pjrc-8051
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8051 Microcontroller. This port is not quite ready for prime time.
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8051 Microcontroller. This port is not quite ready for prime time.
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@ -99,10 +99,10 @@ ifeq ($(CONFIG_RRLOAD_BINARY),y)
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fi
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fi
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endif
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endif
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.depend: Makefile $(SRCS)
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.depend: Makefile chip/Make.defs $(SRCS)
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@if [ -e board/Makefile ]; then \
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@if [ -e board/Makefile ]; then \
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$(MAKE) -C board TOPDIR=$(TOPDIR) depend ; \
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$(MAKE) -C board TOPDIR=$(TOPDIR) depend ; \
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if
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fi
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$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
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$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
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@touch $@
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@touch $@
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@ -37,12 +37,12 @@ HEAD_ASRC = up_nommuhead.S
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S
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CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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up_createstack.c up_dataabort.c up_delay.c up_exit.c up_idle.c \
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up_createstack.c up_dataabort.c up_delay.c up_doirq.c \
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up_initialize.c up_initialstate.c up_interruptcontext.c \
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up_exit.c up_idle.c up_initialize.c up_initialstate.c \
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up_prefetchabort.c up_releasepending.c up_releasestack.c \
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up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
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up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c \
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up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
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up_syscall.c up_unblocktask.c up_undefinedinsn.c up_usestack.c
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up_sigdeliver.c up_syscall.c up_unblocktask.c \
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up_undefinedinsn.c up_usestack.c
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CHIP_ASRCS = c5471_lowputc.S c5471_vectors.S
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CHIP_ASRCS = c5471_lowputc.S c5471_vectors.S
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CHIP_CSRCS = c5471_doirq.c c5471_irq.c c5471_serial.c c5471_timerisr.c \
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CHIP_CSRCS = c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c
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c5471_watchdog.c
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@ -1,104 +0,0 @@
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/************************************************************
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* c5471/c5471_doirq.c
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*
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* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name Gregory Nutt nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************/
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/************************************************************
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* Included Files
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************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <assert.h>
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#include "up_arch.h"
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#include "os_internal.h"
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#include "up_internal.h"
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/************************************************************
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* Definitions
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************************************************************/
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/************************************************************
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* Public Data
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************************************************************/
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/************************************************************
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* Private Data
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************************************************************/
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/************************************************************
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* Private Functions
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************************************************************/
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/************************************************************
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* Public Funtions
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************************************************************/
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void c5471_doirq(int irq, uint32* regs)
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{
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up_ledon(LED_INIRQ);
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#ifdef CONFIG_SUPPRESS_INTERRUPTS
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PANIC(OSERR_ERREXCEPTION);
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#else
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if ((unsigned)irq < NR_IRQS)
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{
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/* Current regs non-zero indicates that we are processing
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* an interrupt; current_regs is also used to manage
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* interrupt level context switches.
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*/
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current_regs = regs;
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/* Mask and acknowledge the interrupt */
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up_maskack_irq(irq);
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/* Deliver the IRQ */
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irq_dispatch(irq, regs);
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/* Indicate that we are no long in an interrupt handler */
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current_regs = NULL;
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/* Unmask the last interrupt (global interrupts are still
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* disabled.
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*/
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up_enable_irq(irq);
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}
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up_ledoff(LED_INIRQ);
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#endif
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}
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@ -156,7 +156,7 @@ up_vectorirq:
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mov fp, #0 /* Init frame pointer */
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mov fp, #0 /* Init frame pointer */
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mov r1, sp /* Get r1=xcp */
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mov r1, sp /* Get r1=xcp */
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bl c5471_doirq /* Call the handler */
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bl up_doirq /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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/* Restore the CPSR, SVC modr registers and return */
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.Lnoirqset:
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.Lnoirqset:
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@ -316,8 +316,4 @@
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* Public Function Prototypes
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* Public Function Prototypes
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************************************************************/
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************************************************************/
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#ifndef __ASSEMBLY__
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extern void c5471_doirq(int irq, uint32* regs);
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#endif
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#endif /* __C5471_CHIP_H */
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#endif /* __C5471_CHIP_H */
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@ -101,7 +101,8 @@ extern void up_boot(void);
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extern void up_copystate(uint32 *dest, uint32 *src);
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extern void up_copystate(uint32 *dest, uint32 *src);
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extern void up_dataabort(uint32 *regs);
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extern void up_dataabort(uint32 *regs);
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extern void up_delay(int milliseconds);
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extern void up_delay(int milliseconds);
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extern void up_doirq(uint32 *regs);
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extern void up_decodeirq(uint32 *regs);
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extern void up_doirq(int irq, uint32 *regs);
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extern void up_fullcontextrestore(uint32 *regs) __attribute__ ((noreturn));
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extern void up_fullcontextrestore(uint32 *regs) __attribute__ ((noreturn));
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extern void up_irqinitialize(void);
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extern void up_irqinitialize(void);
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extern void up_prefetchabort(uint32 *regs);
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extern void up_prefetchabort(uint32 *regs);
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@ -128,7 +128,7 @@ up_vectorirq:
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mov fp, #0 /* Init frame pointer */
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mov fp, #0 /* Init frame pointer */
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mov r0, sp /* Get r0=xcp */
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mov r0, sp /* Get r0=xcp */
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bl up_doirq /* Call the handler */
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bl up_decodeirq /* Call the handler */
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/* Restore the CPSR, SVC modr registers and return */
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/* Restore the CPSR, SVC modr registers and return */
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.Lnoirqset:
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.Lnoirqset:
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@ -138,6 +138,7 @@ up_vectorirq:
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.Lirqtmp:
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.Lirqtmp:
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.word g_irqtmp
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.word g_irqtmp
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.size up_vectorirq, . - up_vectorirq
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.align 5
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.align 5
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@ -183,6 +184,7 @@ up_vectorswi:
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r0
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msr spsr, r0
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ldmia sp, {r0-r15}^ /* Return */
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ldmia sp, {r0-r15}^ /* Return */
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.size up_vectorswi, . - up_vectorswi
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.align 5
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.align 5
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@ -251,6 +253,7 @@ up_vectordata:
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.Ldaborttmp:
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.Ldaborttmp:
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.word g_aborttmp
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.word g_aborttmp
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.size up_vectordata, . - up_vectordata
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.align 5
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.align 5
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@ -317,6 +320,7 @@ up_vectorprefetch:
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.Lpaborttmp:
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.Lpaborttmp:
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.word g_aborttmp
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.word g_aborttmp
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.size up_vectorprefetch, . - up_vectorprefetch
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.align 5
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.align 5
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@ -383,6 +387,7 @@ up_vectorundefinsn:
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.Lundeftmp:
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.Lundeftmp:
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.word g_undeftmp
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.word g_undeftmp
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.size up_vectorundefinsn, . - up_vectorundefinsn
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.align 5
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.align 5
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@ -397,6 +402,9 @@ up_vectorundefinsn:
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.type up_vectorfiq, %function
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.type up_vectorfiq, %function
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up_vectorfiq:
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up_vectorfiq:
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subs pc, lr, #4
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subs pc, lr, #4
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.size up_vectofiq, . - up_vectorfiq
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.align 5
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/********************************************************************
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/********************************************************************
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* Name: up_vectoraddrexcption
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* Name: up_vectoraddrexcption
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@ -410,40 +418,5 @@ up_vectorfiq:
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.type up_vectoraddrexcptn, %function
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.type up_vectoraddrexcptn, %function
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up_vectoraddrexcptn:
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up_vectoraddrexcptn:
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b up_vectoraddrexcptn
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b up_vectoraddrexcptn
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.size up_vectoaddrexcptn, . - up_vectoraddrexcptn
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/**************************************************************************
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* Vector initialization block.
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**************************************************************************/
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/* These will be relocated to VECTOR_BASE. */
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.globl _vector_start
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_vector_start:
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ldr pc, .Lresethandler /* 0x00: Reset */
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ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
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ldr pc, .Lswihandler /* 0x08: Software interrupt */
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ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
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ldr pc, .Ldataaborthandler /* 0x10: Data abort */
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ldr pc, .Laddrexcptnhandler /* 0x14: Address exception */
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ldr pc, .Lirqhandler /* 0x18: IRQ */
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ldr pc, .Lfiqhandler /* 0x1c: FIQ */
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.Lresethandler:
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.long __start
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.Lundefinedhandler:
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.long up_vectorundefinsn
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.Lswihandler:
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.long up_vectorswi
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.Lprefetchaborthandler:
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.long up_vectorprefetch
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.Ldataaborthandler:
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.long up_vectordata
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.Laddrexcptnhandler:
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.long up_vectoraddrexcptn
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.Lirqhandler:
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.long up_vectorirq
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.Lfiqhandler:
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.long up_vectorfiq
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.globl _vector_end
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_vector_end:
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.end
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.end
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103
arch/arm/src/common/up_vectortab.S
Normal file
103
arch/arm/src/common/up_vectortab.S
Normal file
@ -0,0 +1,103 @@
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|
/********************************************************************
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||||||
|
* common/up_vectortab.S
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||||||
|
*
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||||||
|
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
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||||||
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
********************************************************************/
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||||||
|
|
||||||
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/********************************************************************
|
||||||
|
* Included Files
|
||||||
|
********************************************************************/
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||||||
|
|
||||||
|
#include <nuttx/config.h>
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||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Definitions
|
||||||
|
********************************************************************/
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||||||
|
|
||||||
|
/********************************************************************
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||||||
|
* Global Data
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||||||
|
********************************************************************/
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||||||
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||||||
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/********************************************************************
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||||||
|
* Assembly Macros
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||||||
|
********************************************************************/
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||||||
|
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||||||
|
/********************************************************************
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||||||
|
* Name: _vector_start
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||||||
|
*
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||||||
|
* Description:
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||||||
|
* Vector initialization block
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||||||
|
********************************************************************/
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||||||
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||||||
|
.globl _vector_start
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||||||
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||||||
|
/* These will be relocated to VECTOR_BASE. */
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||||||
|
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||||||
|
_vector_start:
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||||||
|
ldr pc, .Lresethandler /* 0x00: Reset */
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||||||
|
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
|
||||||
|
ldr pc, .Lswihandler /* 0x08: Software interrupt */
|
||||||
|
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
|
||||||
|
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
|
||||||
|
ldr pc, .Laddrexcptnhandler /* 0x14: Address exception */
|
||||||
|
ldr pc, .Lirqhandler /* 0x18: IRQ */
|
||||||
|
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
|
||||||
|
|
||||||
|
.globl __start
|
||||||
|
.globl up_vectorundefinsn
|
||||||
|
.globl up_vectorswi
|
||||||
|
.globl up_vectorprefetch
|
||||||
|
.globl up_vectordata
|
||||||
|
.globl up_vectoraddrexcptn
|
||||||
|
.globl up_vectorirq
|
||||||
|
.globl up_vectorfiq
|
||||||
|
|
||||||
|
.Lresethandler:
|
||||||
|
.long __start
|
||||||
|
.Lundefinedhandler:
|
||||||
|
.long up_vectorundefinsn
|
||||||
|
.Lswihandler:
|
||||||
|
.long up_vectorswi
|
||||||
|
.Lprefetchaborthandler:
|
||||||
|
.long up_vectorprefetch
|
||||||
|
.Ldataaborthandler:
|
||||||
|
.long up_vectordata
|
||||||
|
.Laddrexcptnhandler:
|
||||||
|
.long up_vectoraddrexcptn
|
||||||
|
.Lirqhandler:
|
||||||
|
.long up_vectorirq
|
||||||
|
.Lfiqhandler:
|
||||||
|
.long up_vectorfiq
|
||||||
|
|
||||||
|
.globl _vector_end
|
||||||
|
_vector_end:
|
||||||
|
.end
|
||||||
@ -35,7 +35,8 @@
|
|||||||
|
|
||||||
HEAD_ASRC = up_head.S
|
HEAD_ASRC = up_head.S
|
||||||
|
|
||||||
CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S
|
CMN_ASRCS = up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
|
||||||
|
up_vectors.S up_vectortab.S
|
||||||
CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
|
CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
|
||||||
up_dataabort.c up_delay.c up_exit.c up_idle.c \
|
up_dataabort.c up_delay.c up_exit.c up_idle.c \
|
||||||
up_initialize.c up_initialstate.c up_interruptcontext.c \
|
up_initialize.c up_initialstate.c up_interruptcontext.c \
|
||||||
@ -44,7 +45,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
|
|||||||
up_sigdeliver.c up_syscall.c up_unblocktask.c \
|
up_sigdeliver.c up_syscall.c up_unblocktask.c \
|
||||||
up_undefinedinsn.c up_usestack.c
|
up_undefinedinsn.c up_usestack.c
|
||||||
|
|
||||||
CHIP_ASRCS = dm320_lowputc.S dm320_restart.S dm320_vectors.S
|
CHIP_ASRCS = dm320_lowputc.S dm320_restart.S
|
||||||
CHIP_CSRCS = dm320_allocateheap.c dm320_boot.c dm320_doirq.c dm320_irq.c \
|
CHIP_CSRCS = dm320_allocateheap.c dm320_boot.c dm320_decodeirq.c \
|
||||||
dm320_serial.c dm320_timerisr.c
|
dm320_irq.c dm320_serial.c dm320_timerisr.c
|
||||||
|
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
/********************************************************************************
|
/********************************************************************************
|
||||||
* dm320/dm320_doirq.c
|
* dm320/dm320_decodeirq.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@ -67,7 +67,7 @@
|
|||||||
* Public Funtions
|
* Public Funtions
|
||||||
********************************************************************************/
|
********************************************************************************/
|
||||||
|
|
||||||
void up_doirq(uint32* regs)
|
void up_decodeirq(uint32* regs)
|
||||||
{
|
{
|
||||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||||
lib_lowprintf("Unexpected IRQ\n");
|
lib_lowprintf("Unexpected IRQ\n");
|
||||||
@ -1,449 +0,0 @@
|
|||||||
/********************************************************************
|
|
||||||
* dm320/dm320_vectors.S
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
|
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Included Files
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
|
||||||
#include <nuttx/irq.h>
|
|
||||||
#include "up_arch.h"
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Definitions
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Global Data
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.data
|
|
||||||
g_irqtmp:
|
|
||||||
.word 0 /* Saved lr */
|
|
||||||
.word 0 /* Saved spsr */
|
|
||||||
g_undeftmp:
|
|
||||||
.word 0 /* Saved lr */
|
|
||||||
.word 0 /* Saved spsr */
|
|
||||||
g_aborttmp:
|
|
||||||
.word 0 /* Saved lr */
|
|
||||||
.word 0 /* Saved spsr */
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Assembly Macros
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Private Functions
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.text
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Public Functions
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.text
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Name: up_vectorirq
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Interrupt excetpion. Entered in IRQ mode with spsr = SVC
|
|
||||||
* CPSR, lr = SVC PC
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectorirq
|
|
||||||
.type up_vectorirq, %function
|
|
||||||
up_vectorirq:
|
|
||||||
/* On entry, we are in IRQ mode. We are free to use
|
|
||||||
* the IRQ mode r13 and r14.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
ldr r13, .Lirqtmp
|
|
||||||
sub lr, lr, #4
|
|
||||||
str lr, [r13] @ save lr_IRQ
|
|
||||||
mrs lr, spsr
|
|
||||||
str lr, [r13, #4] @ save spsr_IRQ
|
|
||||||
|
|
||||||
/* Then switch back to SVC mode */
|
|
||||||
|
|
||||||
bic lr, lr, #MODE_MASK /* Keep F and T bits */
|
|
||||||
orr lr, lr, #(SVC_MODE | PSR_I_BIT)
|
|
||||||
msr cpsr_c, lr /* Switch to SVC mode */
|
|
||||||
|
|
||||||
/* Create a context structure. First set aside a stack frame
|
|
||||||
* and store r0-r12 into the frame.
|
|
||||||
*/
|
|
||||||
|
|
||||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
|
||||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
|
||||||
|
|
||||||
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
|
|
||||||
|
|
||||||
add r1, sp, #XCPTCONTEXT_SIZE
|
|
||||||
mov r2, r14
|
|
||||||
|
|
||||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
|
||||||
|
|
||||||
ldr r0, .Lirqtmp /* Points to temp storage */
|
|
||||||
ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
|
|
||||||
|
|
||||||
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
|
|
||||||
stmia r0, {r1-r4}
|
|
||||||
|
|
||||||
/* Then call the IRQ handler with interrupts disabled. */
|
|
||||||
|
|
||||||
mov fp, #0 /* Init frame pointer */
|
|
||||||
mov r0, sp /* Get r0=xcp */
|
|
||||||
bl up_doirq /* Call the handler */
|
|
||||||
|
|
||||||
/* Restore the CPSR, SVC modr registers and return */
|
|
||||||
.Lnoirqset:
|
|
||||||
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
|
||||||
msr spsr, r0
|
|
||||||
ldmia sp, {r0-r15}^ /* Return */
|
|
||||||
|
|
||||||
.Lirqtmp:
|
|
||||||
.word g_irqtmp
|
|
||||||
|
|
||||||
.align 5
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Function: up_vectorswi
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* SWI interrupt. We enter the SWI in SVC mode
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectorswi
|
|
||||||
.type up_vectorswi, %function
|
|
||||||
up_vectorswi:
|
|
||||||
|
|
||||||
/* Create a context structure. First set aside a stack frame
|
|
||||||
* and store r0-r12 into the frame.
|
|
||||||
*/
|
|
||||||
|
|
||||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
|
||||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
|
||||||
|
|
||||||
/* Get the correct values of r13(sp), r14(lr), r15(pc)
|
|
||||||
* and CPSR in r1-r4 */
|
|
||||||
|
|
||||||
add r1, sp, #XCPTCONTEXT_SIZE
|
|
||||||
mov r2, r14 /* R14 is altered on return from SWI */
|
|
||||||
mov r3, r14 /* Save r14 as the PC as well */
|
|
||||||
mrs r4, spsr /* Get the saved CPSR */
|
|
||||||
|
|
||||||
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
|
|
||||||
stmia r0, {r1-r4}
|
|
||||||
|
|
||||||
/* Then call the SWI handler with interrupt disabled.
|
|
||||||
* void up_syscall(struct xcptcontext *xcp)
|
|
||||||
*/
|
|
||||||
|
|
||||||
mov fp, #0 /* Init frame pointer */
|
|
||||||
mov r0, sp /* Get r0=xcp */
|
|
||||||
bl up_syscall /* Call the handler */
|
|
||||||
|
|
||||||
/* Restore the CPSR, SVC modr registers and return */
|
|
||||||
|
|
||||||
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
|
||||||
msr spsr, r0
|
|
||||||
ldmia sp, {r0-r15}^ /* Return */
|
|
||||||
|
|
||||||
.align 5
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Name: up_vectordata
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Data abort Exception dispatcher. Give control to data
|
|
||||||
* abort handler. This function is entered in ABORT mode
|
|
||||||
* with spsr = SVC CPSR, lr = SVC PC
|
|
||||||
*
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectordata
|
|
||||||
.type up_vectordata, %function
|
|
||||||
up_vectordata:
|
|
||||||
/* On entry we are free to use the ABORT mode registers
|
|
||||||
* r13 and r14
|
|
||||||
*/
|
|
||||||
|
|
||||||
ldr r13, .Ldaborttmp /* Points to temp storage */
|
|
||||||
sub lr, lr, #8 /* Fixup return */
|
|
||||||
str lr, [r13] /* Save in temp storage */
|
|
||||||
mrs lr, spsr /* Get SPSR */
|
|
||||||
str lr, [r13, #4] /* Save in temp storage */
|
|
||||||
|
|
||||||
/* Then switch back to SVC mode */
|
|
||||||
|
|
||||||
bic lr, lr, #MODE_MASK /* Keep F and T bits */
|
|
||||||
orr lr, lr, #(SVC_MODE | PSR_I_BIT)
|
|
||||||
msr cpsr_c, lr /* Switch to SVC mode */
|
|
||||||
|
|
||||||
/* Create a context structure. First set aside a stack frame
|
|
||||||
* and store r0-r12 into the frame.
|
|
||||||
*/
|
|
||||||
|
|
||||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
|
||||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
|
||||||
|
|
||||||
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
|
|
||||||
|
|
||||||
add r1, sp, #XCPTCONTEXT_SIZE
|
|
||||||
mov r2, r14
|
|
||||||
|
|
||||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
|
||||||
|
|
||||||
ldr r0, .Ldaborttmp /* Points to temp storage */
|
|
||||||
ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
|
|
||||||
|
|
||||||
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
|
|
||||||
stmia r0, {r1-r4}
|
|
||||||
|
|
||||||
/* Then call the data abort handler with interrupt disabled.
|
|
||||||
* void up_dataabort(struct xcptcontext *xcp)
|
|
||||||
*/
|
|
||||||
|
|
||||||
mov fp, #0 /* Init frame pointer */
|
|
||||||
mov r0, sp /* Get r0=xcp */
|
|
||||||
bl up_dataabort /* Call the handler */
|
|
||||||
|
|
||||||
/* Restore the CPSR, SVC modr registers and return */
|
|
||||||
|
|
||||||
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
|
||||||
msr spsr_cxsf, r0
|
|
||||||
ldmia sp, {r0-r15}^ /* Return */
|
|
||||||
|
|
||||||
.Ldaborttmp:
|
|
||||||
.word g_aborttmp
|
|
||||||
|
|
||||||
.align 5
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Name: up_vectorprefetch
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Prefetch abort exception. Entered in ABT mode with
|
|
||||||
* spsr = SVC CPSR, lr = SVC PC
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectorprefetch
|
|
||||||
.type up_vectorprefetch, %function
|
|
||||||
up_vectorprefetch:
|
|
||||||
/* On entry we are free to use the ABORT mode registers
|
|
||||||
* r13 and r14
|
|
||||||
*/
|
|
||||||
|
|
||||||
ldr r13, .Lpaborttmp /* Points to temp storage */
|
|
||||||
sub lr, lr, #4 /* Fixup return */
|
|
||||||
str lr, [r13] /* Save in temp storage */
|
|
||||||
mrs lr, spsr /* Get SPSR */
|
|
||||||
str lr, [r13, #4] /* Save in temp storage */
|
|
||||||
|
|
||||||
/* Then switch back to SVC mode */
|
|
||||||
|
|
||||||
bic lr, lr, #MODE_MASK /* Keep F and T bits */
|
|
||||||
orr lr, lr, #(SVC_MODE | PSR_I_BIT)
|
|
||||||
msr cpsr_c, lr /* Switch to SVC mode */
|
|
||||||
|
|
||||||
/* Create a context structure. First set aside a stack frame
|
|
||||||
* and store r0-r12 into the frame.
|
|
||||||
*/
|
|
||||||
|
|
||||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
|
||||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
|
||||||
|
|
||||||
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
|
|
||||||
|
|
||||||
add r1, sp, #XCPTCONTEXT_SIZE
|
|
||||||
mov r2, r14
|
|
||||||
|
|
||||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
|
||||||
|
|
||||||
ldr r0, .Lpaborttmp /* Points to temp storage */
|
|
||||||
ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
|
|
||||||
|
|
||||||
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
|
|
||||||
stmia r0, {r1-r4}
|
|
||||||
|
|
||||||
/* Then call the prefetch abort handler with interrupt disabled.
|
|
||||||
* void up_prefetchabort(struct xcptcontext *xcp)
|
|
||||||
*/
|
|
||||||
|
|
||||||
mov fp, #0 /* Init frame pointer */
|
|
||||||
mov r0, sp /* Get r0=xcp */
|
|
||||||
bl up_prefetchabort /* Call the handler */
|
|
||||||
|
|
||||||
/* Restore the CPSR, SVC modr registers and return */
|
|
||||||
|
|
||||||
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
|
||||||
msr spsr_cxsf, r0
|
|
||||||
ldmia sp, {r0-r15}^ /* Return */
|
|
||||||
|
|
||||||
.Lpaborttmp:
|
|
||||||
.word g_aborttmp
|
|
||||||
|
|
||||||
.align 5
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Name: up_vectorundefinsn
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Undefined instruction entry exception. Entered in
|
|
||||||
* UND mode, spsr = SVC CPSR, lr = SVC PC
|
|
||||||
*
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectorundefinsn
|
|
||||||
.type up_vectorundefinsn, %function
|
|
||||||
up_vectorundefinsn:
|
|
||||||
/* On entry we are free to use the UND mode registers
|
|
||||||
* r13 and r14
|
|
||||||
*/
|
|
||||||
|
|
||||||
ldr r13, .Lundeftmp /* Points to temp storage */
|
|
||||||
str lr, [r13] /* Save in temp storage */
|
|
||||||
mrs lr, spsr /* Get SPSR */
|
|
||||||
str lr, [r13, #4] /* Save in temp storage */
|
|
||||||
|
|
||||||
/* Then switch back to SVC mode */
|
|
||||||
|
|
||||||
bic lr, lr, #MODE_MASK /* Keep F and T bits */
|
|
||||||
orr lr, lr, #(SVC_MODE | PSR_I_BIT)
|
|
||||||
msr cpsr_c, lr /* Switch to SVC mode */
|
|
||||||
|
|
||||||
/* Create a context structure. First set aside a stack frame
|
|
||||||
* and store r0-r12 into the frame.
|
|
||||||
*/
|
|
||||||
|
|
||||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
|
||||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
|
||||||
|
|
||||||
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
|
|
||||||
|
|
||||||
add r1, sp, #XCPTCONTEXT_SIZE
|
|
||||||
mov r2, r14
|
|
||||||
|
|
||||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
|
||||||
|
|
||||||
ldr r0, .Lundeftmp /* Points to temp storage */
|
|
||||||
ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
|
|
||||||
|
|
||||||
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
|
|
||||||
stmia r0, {r1-r4}
|
|
||||||
|
|
||||||
/* Then call the undef insn handler with interrupt disabled.
|
|
||||||
* void up_undefinedinsn(struct xcptcontext *xcp)
|
|
||||||
*/
|
|
||||||
|
|
||||||
mov fp, #0 /* Init frame pointer */
|
|
||||||
mov r0, sp /* Get r0=xcp */
|
|
||||||
bl up_undefinedinsn /* Call the handler */
|
|
||||||
|
|
||||||
/* Restore the CPSR, SVC modr registers and return */
|
|
||||||
|
|
||||||
ldr r0, [sp, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
|
||||||
msr spsr_cxsf, r0
|
|
||||||
ldmia sp, {r0-r15}^ /* Return */
|
|
||||||
|
|
||||||
.Lundeftmp:
|
|
||||||
.word g_undeftmp
|
|
||||||
|
|
||||||
.align 5
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Name: up_vectorfiq
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Shouldn't happen
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectorfiq
|
|
||||||
.type up_vectorfiq, %function
|
|
||||||
up_vectorfiq:
|
|
||||||
subs pc, lr, #4
|
|
||||||
|
|
||||||
/********************************************************************
|
|
||||||
* Name: up_vectoraddrexcption
|
|
||||||
*
|
|
||||||
* Description:
|
|
||||||
* Shouldn't happen
|
|
||||||
*
|
|
||||||
********************************************************************/
|
|
||||||
|
|
||||||
.globl up_vectoraddrexcptn
|
|
||||||
.type up_vectoraddrexcptn, %function
|
|
||||||
up_vectoraddrexcptn:
|
|
||||||
b up_vectoraddrexcptn
|
|
||||||
|
|
||||||
/**************************************************************************
|
|
||||||
* Vector initialization block.
|
|
||||||
**************************************************************************/
|
|
||||||
|
|
||||||
/* These will be relocated to VECTOR_BASE. */
|
|
||||||
|
|
||||||
.globl _vector_start
|
|
||||||
_vector_start:
|
|
||||||
ldr pc, .Lresethandler /* 0x00: Reset */
|
|
||||||
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
|
|
||||||
ldr pc, .Lswihandler /* 0x08: Software interrupt */
|
|
||||||
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
|
|
||||||
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
|
|
||||||
ldr pc, .Laddrexcptnhandler /* 0x14: Address exception */
|
|
||||||
ldr pc, .Lirqhandler /* 0x18: IRQ */
|
|
||||||
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
|
|
||||||
|
|
||||||
.Lresethandler:
|
|
||||||
.long __start
|
|
||||||
.Lundefinedhandler:
|
|
||||||
.long up_vectorundefinsn
|
|
||||||
.Lswihandler:
|
|
||||||
.long up_vectorswi
|
|
||||||
.Lprefetchaborthandler:
|
|
||||||
.long up_vectorprefetch
|
|
||||||
.Ldataaborthandler:
|
|
||||||
.long up_vectordata
|
|
||||||
.Laddrexcptnhandler:
|
|
||||||
.long up_vectoraddrexcptn
|
|
||||||
.Lirqhandler:
|
|
||||||
.long up_vectorirq
|
|
||||||
.Lfiqhandler:
|
|
||||||
.long up_vectorfiq
|
|
||||||
.globl _vector_end
|
|
||||||
_vector_end:
|
|
||||||
.end
|
|
||||||
Loading…
Reference in New Issue
Block a user