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arch/arm/src/tiva/hardware: Initialize .bss sooner, Fix some PRCM register definitions

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configs/launchxl-cc1312r1:  Correct DIOs used to provide the UART0 serial console.

Status:  Board boots to NSH prompt now.  But I am not getting serial input.  Things are probably not very stable in general.
This commit is contained in:
Gregory Nutt 2019-02-12 16:35:14 -06:00
parent cf62b2288b
commit a2406c1ac8
7 changed files with 306 additions and 287 deletions
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16
arch/arm/src/tiva/cc13xx/cc13xx_gpio.c
View File

@ -48,16 +48,12 @@
#include <nuttx/irq.h>
#include "up_arch.h"
#include "tiva_enablepwr.h"
#include "tiva_enableclks.h"
#include "tiva_gpio.h"
/****************************************************************************
* Private Data
****************************************************************************/
static bool g_gpio_powered;
/****************************************************************************
* Public Functions
****************************************************************************/
@ -67,6 +63,7 @@ static bool g_gpio_powered;
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* NOTE: Power and clocking provided in __start().
*
****************************************************************************/
@ -82,17 +79,6 @@ int tiva_configgpio(pinconfig_t pinconfig)
flags = spin_lock_irqsave();
/* Enable power and clocking for this GPIO peripheral if this is the first
* GPIO pin configured.
*/
if (!g_gpio_powered)
{
tiva_gpio_enablepwr();
tiva_gpio_enableclk();
g_gpio_powered = true;
}
#ifdef CONFIG_TIVA_GPIO_IRQS
/* Mask and clear any pending GPIO interrupt */

31
arch/arm/src/tiva/cc13xx/cc13xx_start.c
View File

@ -53,6 +53,8 @@
#include "up_arch.h"
#include "up_internal.h"
#include "tiva_enablepwr.h"
#include "tiva_enableclks.h"
#include "tiva_lowputc.h"
#include "tiva_userspace.h"
#include "tiva_eeprom.h"
@ -229,12 +231,6 @@ void __start(void)
cc13xx_trim_device();
/* Configure the UART so that we can get debug output as soon as possible */
tiva_lowsetup();
tiva_fpuconfig();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
@ -244,7 +240,16 @@ void __start(void)
*dest++ = 0;
}
showprogress('B');
/* Enable power and clocking for the GPIO peripheral. */
tiva_gpio_enablepwr();
tiva_gpio_enableclk();
/* Configure the UART so that we can get debug output as soon as possible */
tiva_lowsetup();
tiva_fpuconfig();
showprogress('A');
#ifdef CONFIG_BOOT_RUNFROMFLASH
/* Move the initialized data section from his temporary holding spot in
@ -258,14 +263,14 @@ void __start(void)
*dest++ = *src++;
}
showprogress('C');
showprogress('B');
#endif
#ifdef USE_EARLYSERIALINIT
/* Perform early serial initialization */
up_earlyserialinit();
showprogress('D');
showprogress('C');
#endif
#ifdef CONFIG_BUILD_PROTECTED
@ -276,7 +281,7 @@ void __start(void)
*/
tiva_userspace();
showprogress('E');
showprogress('D');
#endif
#ifdef CONFIG_TIVA_CC26X2_POWERLIB /* REVISIT: Used with CC13x2 as well. */
@ -285,19 +290,19 @@ void __start(void)
*/
cc13xx_power_initialize();
showprogress('F');
showprogress('E');
#endif
/* Initialize on-board resources */
tiva_boardinitialize();
showprogress('G');
showprogress('F');
#ifdef CONFIG_TIVA_EEPROM
/*Initialize the EEPROM */
tiva_eeprom_initialize();
showprogress('H');
showprogress('G');
#endif
/* Then start NuttX */

12
arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h
View File

@ -231,11 +231,11 @@
* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
/* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and
@ -269,16 +269,16 @@
* UART Clock Gate For Deep Sleep Mode
*/
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
/* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and
* SSI Clock Gate For Deep Sleep Mode.
*/
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and

20
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_prcm.h
View File

@ -256,13 +256,13 @@
* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_PKA_CLKEN_SHIFT (1 << 2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKG_PKA_CLKEN_SHIFT (2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKG_PKA_CLKEN (1 << PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes (only) */
@ -282,7 +282,7 @@
/* GPIO Clock Gate For Run And All Modes (only) */
#define PRCM_GPIOCLKGR_AMCLKEN (1 << 8) /* Bit 8 Force clock for all modes */
#define PRCM_GPIOCLKGR_AMCLKEN (1 << 8) /* Bit 8: Force clock for all modes */
/* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and
* GPT Clock Gate For Deep Sleep Mode.
@ -319,9 +319,9 @@
* UART Clock Gate For Deep Sleep Mode
*/
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
#define PRCM_UARTCLKG_CLKEN_UART1_SHIFT (1 << 1) /* Bit 1: UART1 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART1_SHIFT (1) /* Bit 1: UART1 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART1 (1 << PRCM_UARTCLKGDS_CLKEN_UART1_SHIFT)
/* UART Clock Gate For Run And All Modes (only) */
@ -333,9 +333,9 @@
* SSI Clock Gate For Deep Sleep Mode
*/
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
/* SSI Clock Gate For Run And All Modes (only) */
@ -492,7 +492,7 @@
/* PERIPH Power Domain Control */
#define PRCM_PDCTL0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDCTL0.PERIOPH_ON */
#define PRCM_PDCTL0PERIPH_ON (1 << 0) /* Bit 0: Alias for PDCTL0.PERIPH_ON */
/* Power Domain Status */

42
configs/launchxl-cc1312r1/README.txt
View File

@ -21,21 +21,30 @@ Status
development. Serious board development will occur later. Board
support is missing LED and button support.
2019-02-10: Figured out how to connect J-Link and began debug.
2019-02-12: Now hard-faults in tiva_lowsetup() here:
2019-02-12: A little progress. I do make it all the way into NSH:
352 ctl = getreg32(TIVA_CONSOLE_BASE + TIVA_UART_CTL_OFFSET);
ABCF
nx_start: Entry
uart_register: Registering /dev/console
uart_register: Registering /dev/ttyS0
work_hpstart: Starting high-priority kernel worker thread(s)
up_release_pending: From TCB=20000c00
nx_start_application: Starting init thread
Most likely UART0 clocking is not being enabled correctly.
NuttShell (NSH) NuttX-7.28
nsh> nx_start: CPU0: Beginning Idle Loop
But things are not very stable and I do not get any console input.
Serial Console
==============
The on-board XDS110 Debugger provide a USB virtual serial console using
UART0 (PA0/U0RX and PA1/U0TX).
UART0 (DIO2_RXD and DIO3_TXD).
A J-Link debugger is used (see below), then the RXD/TXD jumper pins can
be used to support a serial console through appropriate TTL level adapater
(RS-232 or USB serial).
be used to support a serial console through these same pins via an
appropriate TTL level adapater (RS-232 or USB serial).
LEDs and Buttons
================
@ -133,5 +142,24 @@ Using J-Link
NOTE: When connecting the J-Link GDB server, the interface must be set to
JTAG, not SWD as you might expect.
The RXD/TXD pins. PA0/U0RX and PA1/U0TX, can then support a Serial console
The RXD/TXD pins, DIO2_RXD and DIO3_TXD, can then support a Serial console
using the appropriate TTL adapter (TTL to RS-232 or TTL to USB serial).
One odd behavior that I have found is after a reset from the J-Link, the
SP and PC registers are not automatically set and I had to manually set
them as shown below:
(gdb) target remote localhost:2331
(gdb) mon reset
(gdb) mon halt
(gdb) file nuttx
(gdb) mon memu32 0
Reading from address 0x00000000 (Data = 0x20001950)
(gdb) mon memu32 4
Reading from address 0x00000004 (Data = 0x00000139)
(gdb) mon reg sp 0x20001950
Writing register (SP = 0x20001950)
(gdb) mon reg pc 0x00000139
Writing register (PC = 0x00000139)
(gdb) n
232 cc13xx_trim_device();

2
configs/launchxl-cc1312r1/include/board.h
View File

@ -126,7 +126,7 @@
/* UART0:
*
* The on-board XDS110 Debugger provide a USB virtual serial console using
* UART0 (PA0/U0RX and PA1/U0TX).
* UART0 (DIO2_RXD and DIO3_TXD).
*/
# define GPIO_UART0_RX &g_gpio_uart0_rx

6
configs/launchxl-cc1312r1/src/cc1312_pinconfig.c
View File

@ -51,18 +51,18 @@
/* UART0:
*
* The on-board XDS110 Debugger provide a USB virtual serial console using
* UART0 (PA0/U0RX and PA1/U0TX).
* UART0 (DIO2_RXD and DIO3_TXD).
*/
const struct cc13xx_pinconfig_s g_gpio_uart0_rx =
{
.gpio = GPIO_DIO(0),
.gpio = GPIO_DIO(2),
.ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_STD_INPUT
};
const struct cc13xx_pinconfig_s g_gpio_uart0_tx =
{
.gpio = GPIO_DIO(1),
.gpio = GPIO_DIO(3),
.ioc = IOC_IOCFG_PORTID(IOC_IOCFG_PORTID_UART0_TX) | IOC_STD_OUTPUT
};
#endif