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arch/xtensa: Fix task signal process preemption A0 modification error

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Dong Heng 2020-09-28 11:55:32 +08:00 committed by Alan Carvalho de Assis
parent 9369ce6488
commit a266dc9629
1 changed files with 34 additions and 0 deletions
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34
arch/xtensa/src/common/xtensa_sigdeliver.c
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@ -155,6 +155,40 @@ void xtensa_sig_deliver(void)
regs[REG_PS] = rtcb->xcp.saved_ps;
rtcb->xcp.sigdeliver = NULL; /* Allows next handler to be scheduled */
/* Issue:
*
* Task1 --> process
* --> xtensa_context_save(S1)
* --> s32i a0, a2, (4 * REG_A0)
* --> rtcb->xcp.regs[REG_A0] = A0
*
* Task preemption
*
* Task2 --> Post signal to Task1
* --> Wake up Task1
*
* Task1 --> xtensa_sig_deliver
* --> up_irq_enable()
* --> Task preemption
*
* Task preemption --> xtensa_context_save
* --> rtcb->xcp.regs[REG_A0] = A0 of "xtensa_sig_deliver"
* = _xtensa_sig_trampoline + 6
* = "j 1b"
*
* Process ...
*
* Task1 --> xtensa_sig_deliver
* --> xtensa_context_restore
* --> xtensa_context_save(S1)
* --> l32i a0, a2, (4 * REG_A0)
* --> a0 = "j 1b"
* --> ret
* --> run "j 1b"
*/
rtcb->xcp.regs[REG_A0] = regs[REG_A0];
#ifdef CONFIG_SMP
/* Restore the saved 'irqcount' and recover the critical section
* spinlocks.