From a276de741f448dd4b9cbebd792fc38b1d4bdddd1 Mon Sep 17 00:00:00 2001
From: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Date: Wed, 19 May 2021 17:04:05 +0900
Subject: [PATCH] arch: cxd56xx: Fix SPI setmode function

When SSP mode is changed, SSE bit of SSPCR1 register must be disabled.
---
 arch/arm/src/cxd56xx/cxd56_spi.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/src/cxd56xx/cxd56_spi.c b/arch/arm/src/cxd56xx/cxd56_spi.c
index f537e603e7..ac3c60c0ac 100644
--- a/arch/arm/src/cxd56xx/cxd56_spi.c
+++ b/arch/arm/src/cxd56xx/cxd56_spi.c
@@ -509,6 +509,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
 {
   FAR struct cxd56_spidev_s *priv = (FAR struct cxd56_spidev_s *)dev;
   uint32_t regval;
+  uint32_t cr1val;
 
   /* Has the mode changed? */
 
@@ -551,8 +552,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
             return;
         }
 
+      /* Disable SSE */
+
+      cr1val = spi_getreg(priv, CXD56_SPI_CR1_OFFSET);
+      spi_putreg(priv, CXD56_SPI_CR1_OFFSET, cr1val & ~SPI_CR1_SSE);
+
       spi_putreg(priv, CXD56_SPI_CR0_OFFSET, regval);
 
+      /* Enable SSE after a few microseconds delay */
+
+      up_udelay(3);
+
+      spi_putreg(priv, CXD56_SPI_CR1_OFFSET, cr1val);
+
       /* Enable clock gating (clock disable) */
 
       cxd56_spi_clock_gate_enable(priv->port);