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arch: cxd56xx: Fix SPI setmode function

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When SSP mode is changed, SSE bit of SSPCR1 register must be disabled.
This commit is contained in:
SPRESENSE 2021-05-19 17:04:05 +09:00 committed by Alin Jerpelea
parent 89fd987a1a
commit a276de741f
1 changed files with 12 additions and 0 deletions
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12
arch/arm/src/cxd56xx/cxd56_spi.c
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@ -509,6 +509,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
{ {
FAR struct cxd56_spidev_s *priv = (FAR struct cxd56_spidev_s *)dev; FAR struct cxd56_spidev_s *priv = (FAR struct cxd56_spidev_s *)dev;
uint32_t regval; uint32_t regval;
uint32_t cr1val;
/* Has the mode changed? */ /* Has the mode changed? */
@ -551,8 +552,19 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
return; return;
} }
/* Disable SSE */
cr1val = spi_getreg(priv, CXD56_SPI_CR1_OFFSET);
spi_putreg(priv, CXD56_SPI_CR1_OFFSET, cr1val & ~SPI_CR1_SSE);
spi_putreg(priv, CXD56_SPI_CR0_OFFSET, regval); spi_putreg(priv, CXD56_SPI_CR0_OFFSET, regval);
/* Enable SSE after a few microseconds delay */
up_udelay(3);
spi_putreg(priv, CXD56_SPI_CR1_OFFSET, cr1val);
/* Enable clock gating (clock disable) */ /* Enable clock gating (clock disable) */
cxd56_spi_clock_gate_enable(priv->port); cxd56_spi_clock_gate_enable(priv->port);