diff --git a/arch/arm/src/tms570/chip/tms570_pbist.h b/arch/arm/src/tms570/chip/tms570_pbist.h index 1cc8387428..2e4cfb5d72 100644 --- a/arch/arm/src/tms570/chip/tms570_pbist.h +++ b/arch/arm/src/tms570/chip/tms570_pbist.h @@ -54,118 +54,195 @@ ****************************************************************************************************/ /* PBIST RAM Groups */ -#define PBIST_PBIST_ROM_GROUP 1 /* ROM */ -#define PBIST_STC_ROM_GROUP 2 /* ROM */ -#define PBIST_DCAN1_RAM_GROUP 3 /* Dual-port */ -#define PBIST_DCAN2_RAM_GROUP 4 /* Dual-port */ -#define PBIST_ESRAM1_RAM_GROUP 6 /* Single-port */ -#define PBIST_MIBSPI1_RAM_GROUP 7 /* Dual-port */ -#define PBIST_VIM_RAM_GROUP 10 /* Dual-port */ -#define PBIST_MIBADC_RAM_GROUP 11 /* Dual-port */ -#define PBIST_N2HET_RAM_GROUP 13 /* Dual-port */ -#define PBIST_HET_TU_RAM_GROUP 14 /* Dual-port */ +#define PBIST_PBIST_ROM_GROUP 1 /* ROM */ +#define PBIST_STC_ROM_GROUP 2 /* ROM */ +#define PBIST_DCAN1_RAM_GROUP 3 /* Dual-port */ +#define PBIST_DCAN2_RAM_GROUP 4 /* Dual-port */ +#define PBIST_ESRAM1_RAM_GROUP 6 /* Single-port */ +#define PBIST_MIBSPI1_RAM_GROUP 7 /* Dual-port */ +#define PBIST_VIM_RAM_GROUP 10 /* Dual-port */ +#define PBIST_MIBADC_RAM_GROUP 11 /* Dual-port */ +#define PBIST_N2HET_RAM_GROUP 13 /* Dual-port */ +#define PBIST_HET_TU_RAM_GROUP 14 /* Dual-port */ /* RAM Group Select */ -#define PBIST_PBIST_ROM_RGS 1 /* ROM */ -#define PBIST_STC_ROM_RGS 2 /* ROM */ -#define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */ -#define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */ -#define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */ -#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ -#define PBIST_VIM_RAM_RGS 8 /* Dual-port */ -#define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */ -#define PBIST_N2HET_RAM_RGS 11 /* Dual-port */ -#define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */ +#define PBIST_PBIST_ROM_RGS 1 /* ROM */ +#define PBIST_STC_ROM_RGS 2 /* ROM */ +#define PBIST_DCAN1_RAM_RGS 3 /* Dual-port */ +#define PBIST_DCAN2_RAM_RGS 4 /* Dual-port */ +#define PBIST_ESRAM1_RAM_RGS 6 /* Single-port */ +#define PBIST_MIBSPI1_RAM_RGS 7 /* Dual-port */ +#define PBIST_VIM_RAM_RGS 8 /* Dual-port */ +#define PBIST_MIBADC_RAM_RGS 9 /* Dual-port */ +#define PBIST_N2HET_RAM_RGS 11 /* Dual-port */ +#define PBIST_HET_TU_RAM_RGS 12 /* Dual-port */ /* Register Offsets *********************************************************************************/ -#define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */ -#define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */ -#define TMS570_PBIST_PCR_OFFSET 0x016c /* Program Control Register */ -#define TMS570_PBIST_PACT_OFFSET 0x0180 /* PBIST Activate/ROM Clock Enable Register */ -#define TMS570_PBIST_PBISTID_OFFSET 0x0184 /* PBIST ID Register */ -#define TMS570_PBIST_OVER_OFFSET 0x0188 /* Override Register */ -#define TMS570_PBIST_FSRF0_OFFSET 0x0190 /* Fail Status Fail Register 0 */ -#define TMS570_PBIST_FSRC0_OFFSET 0x0198 /* Fail Status Count Register 0 */ -#define TMS570_PBIST_FSRC1_OFFSET 0x019c /* Fail Status Count Register 1 */ -#define TMS570_PBIST_FSRA0_OFFSET 0x01a0 /* Fail Status Address 0 Register */ -#define TMS570_PBIST_FSRA1_OFFSET 0x01a4 /* Fail Status Address 1 Register */ -#define TMS570_PBIST_FSRDL0_OFFSET 0x01a8 /* Fail Status Data Register 0 */ -#define TMS570_PBIST_FSRDL1_OFFSET 0x01b0 /* Fail Status Data Register 1 */ -#define TMS570_PBIST_ROM_OFFSET 0x01c0 /* ROM Mask Register */ -#define TMS570_PBIST_ALGO_OFFSET 0x01c4 /* ROM Algorithm Mask Register */ -#define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */ -#define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */ +#define TMS570_PBIST_RAMT_OFFSET 0x0160 /* RAM Configuration Register */ +#define TMS570_PBIST_DLR_OFFSET 0x0164 /* Datalogger Register */ +#define TMS570_PBIST_PCR_OFFSET 0x016c /* Program Control Register */ +#define TMS570_PBIST_PACT_OFFSET 0x0180 /* PBIST Activate/ROM Clock Enable Register */ +#define TMS570_PBIST_PBISTID_OFFSET 0x0184 /* PBIST ID Register */ +#define TMS570_PBIST_OVER_OFFSET 0x0188 /* Override Register */ +#define TMS570_PBIST_FSRF0_OFFSET 0x0190 /* Fail Status Fail Register 0 */ +#define TMS570_PBIST_FSRF1_OFFSET 0x0194 /* Fail Status Fail Register 1 */ +#define TMS570_PBIST_FSRC0_OFFSET 0x0198 /* Fail Status Count Register 0 */ +#define TMS570_PBIST_FSRC1_OFFSET 0x019c /* Fail Status Count Register 1 */ +#define TMS570_PBIST_FSRA0_OFFSET 0x01a0 /* Fail Status Address 0 Register */ +#define TMS570_PBIST_FSRA1_OFFSET 0x01a4 /* Fail Status Address 1 Register */ +#define TMS570_PBIST_FSRDL0_OFFSET 0x01a8 /* Fail Status Data Register 0 */ +#define TMS570_PBIST_FSRDL1_OFFSET 0x01b0 /* Fail Status Data Register 1 */ +#define TMS570_PBIST_ROM_OFFSET 0x01c0 /* ROM Mask Register */ +#define TMS570_PBIST_ALGO_OFFSET 0x01c4 /* ROM Algorithm Mask Register */ +#define TMS570_PBIST_RINFOL_OFFSET 0x01c8 /* RAM Info Mask Lower Register */ +#define TMS570_PBIST_RINFOU_OFFSET 0x01cc /* RAM Info Mask Upper Register */ /* Register Addresses *******************************************************************************/ -#define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET) -#define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET) -#define TMS570_PBIST_PCR (TMS570_PBIST_BASE+TMS570_PBIST_PCR_OFFSET) -#define TMS570_PBIST_PACT (TMS570_PBIST_BASE+TMS570_PBIST_PACT_OFFSET) -#define TMS570_PBIST_PBISTID (TMS570_PBIST_BASE+TMS570_PBIST_PBISTID_OFFSET) -#define TMS570_PBIST_OVER (TMS570_PBIST_BASE+TMS570_PBIST_OVER_OFFSET) -#define TMS570_PBIST_FSRF0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF0_OFFSET) -#define TMS570_PBIST_FSRC0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC0_OFFSET) -#define TMS570_PBIST_FSRC1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC1_OFFSET) -#define TMS570_PBIST_FSRA0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA0_OFFSET) -#define TMS570_PBIST_FSRA1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA1_OFFSET) -#define TMS570_PBIST_FSRDL0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL0_OFFSET) -#define TMS570_PBIST_FSRDL1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL1_OFFSET) -#define TMS570_PBIST_ROM (TMS570_PBIST_BASE+TMS570_PBIST_ROM_OFFSET) -#define TMS570_PBIST_ALGO (TMS570_PBIST_BASE+TMS570_PBIST_ALGO_OFFSET) -#define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET) -#define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET) +#define TMS570_PBIST_RAMT (TMS570_PBIST_BASE+TMS570_PBIST_RAMT_OFFSET) +#define TMS570_PBIST_DLR (TMS570_PBIST_BASE+TMS570_PBIST_DLR_OFFSET) +#define TMS570_PBIST_PCR (TMS570_PBIST_BASE+TMS570_PBIST_PCR_OFFSET) +#define TMS570_PBIST_PACT (TMS570_PBIST_BASE+TMS570_PBIST_PACT_OFFSET) +#define TMS570_PBIST_PBISTID (TMS570_PBIST_BASE+TMS570_PBIST_PBISTID_OFFSET) +#define TMS570_PBIST_OVER (TMS570_PBIST_BASE+TMS570_PBIST_OVER_OFFSET) +#define TMS570_PBIST_FSRF0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF0_OFFSET) +#define TMS570_PBIST_FSRF1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRF1_OFFSET) +#define TMS570_PBIST_FSRC0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC0_OFFSET) +#define TMS570_PBIST_FSRC1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRC1_OFFSET) +#define TMS570_PBIST_FSRA0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA0_OFFSET) +#define TMS570_PBIST_FSRA1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRA1_OFFSET) +#define TMS570_PBIST_FSRDL0 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL0_OFFSET) +#define TMS570_PBIST_FSRDL1 (TMS570_PBIST_BASE+TMS570_PBIST_FSRDL1_OFFSET) +#define TMS570_PBIST_ROM (TMS570_PBIST_BASE+TMS570_PBIST_ROM_OFFSET) +#define TMS570_PBIST_ALGO (TMS570_PBIST_BASE+TMS570_PBIST_ALGO_OFFSET) +#define TMS570_PBIST_RINFOL (TMS570_PBIST_BASE+TMS570_PBIST_RINFOL_OFFSET) +#define TMS570_PBIST_RINFOU (TMS570_PBIST_BASE+TMS570_PBIST_RINFOU_OFFSET) /* Register Bit-Field Definitions *******************************************************************/ /* RAM Configuration Register */ -#define PBIST_RAMT_ + +#define PBIST_RAMT_RLS_SHIFT (0) /* Bits 0-1: RAM Latency Select */ +#define PBIST_RAMT_RLS_MASK (3 << PBIST_RAMT_RLS_SHIFT) +# define PBIST_RAMT_RLS(n) ((uint32_t)(n) << PBIST_RAMT_RLS_SHIFT) +#define PBIST_RAMT_PLS_SHIFT (2) /* Bits 2-5: Pipeline Latency Select */ +#define PBIST_RAMT_PLS_MASK (15 << PBIST_RAMT_PLS_SHIFT) +# define PBIST_RAMT_PLS(n) ((uint32_t)(n) << PBIST_RAMT_PLS_SHIFT) +#define PBIST_RAMT_SMS_SHIFT (6) /* Bits 6-7: Sense Margin Select Register */ +#define PBIST_RAMT_SMS_MASK (3 << PBIST_RAMT_SMS_SHIFT) +# define PBIST_RAMT_SMS(n) ((uint32_t)(n) << PBIST_RAMT_SMS_SHIFT) +#define PBIST_RAMT_DWR_SHIFT (8) /* Bits 8-15: Data Width Register */ +#define PBIST_RAMT_DWR_MASK (0xff << PBIST_RAMT_DWR_SHIFT) +# define PBIST_RAMT_DWR(n) ((uint32_t)(n) << PBIST_RAMT_DWR_SHIFT) +#define PBIST_RAMT_RDS_SHIFT (16) /* Bits 16-23: Return Data Select */ +#define PBIST_RAMT_RDS_MASK (0xff << PBIST_RAMT_RDS_SHIFT) +# define PBIST_RAMT_RDS(n) ((uint32_t)(n) << PBIST_RAMT_RDS_SHIFT) +#define PBIST_RAMT_RGS_SHIFT (14) /* Bits 24-31: Ram Group Select */ +#define PBIST_RAMT_RGS_MASK (0xff << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS(n) ((uint32_t)(n) << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_PBIST_ROM (PBIST_PBIST_ROM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_STC_ROM (PBIST_STC_ROM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_DCAN1_RAM (PBIST_DCAN1_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_DCAN2_RAM (PBIST_DCAN2_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_ESRAM1_RAM (PBIST_ESRAM1_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_MIBSPI1_RAM (PBIST_MIBSPI1_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_VIM_RAM (PBIST_VIM_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_MIBADC_RAM (PBIST_MIBADC_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_N2HET_RAM (PBIST_N2HET_RAM_RGS << PBIST_RAMT_RGS_SHIFT) +# define PBIST_RAMT_RGS_HET_TU_RAM (PBIST_HET_TU_RAM_RGS << PBIST_RAMT_RGS_SHIFT) + /* Datalogger Register */ -#define PBIST_DLR_ + +#define PBIST_DLR_DLR2 (1 << 2) /* Bit 2: ROM-based testing */ +#define PBIST_DLR_DLR4 (1 << 4) /* Bit 4: Configuration access */ + /* Program Control Register */ -#define PBIST_PCR_ + +#define PBIST_PCR_STR_SHIFT (0) /* Bits 0-4: PBIST Controller Mode */ +#define PBIST_PCR_STR_MASK (0x1f << PBIST_PCR_STR_SHIFT) +# define PBIST_PCR_STR_START (1 << PBIST_PCR_STR_SHIFT) /* Start / Time Stamp mode restart */ +# define PBIST_PCR_STR_RESUME (2 << PBIST_PCR_STR_SHIFT) /* Resume / Emulation read */ +# define PBIST_PCR_STR_STOP (4 << PBIST_PCR_STR_SHIFT) /* Stop */ +# define PBIST_PCR_STR_STEP (8 << PBIST_PCR_STR_SHIFT) /* Step / Step for emulation mode */ +# define PBIST_PCR_STR_MISR (16 << PBIST_PCR_STR_SHIFT) /* Check MISR mode */ + /* PBIST Activate/ROM Clock Enable Register */ -#define PBIST_PACT_ + +#define PBIST_PACT_PACT0 (1 << 0) /* Bit 0: ROM Clock Enable */ +#define PBIST_PACT_PACT1 (1 << 1) /* Bit 1: PBIST Activate */ + /* PBIST ID Register */ -#define PBIST_PBISTID_ + +#define PBIST_PBISTID_SHIFT (0) /* Bits 0-7: PBIST controller ID */ +#define PBIST_PBISTID_MASK (0xff << PBIST_PBISTID_SHIFT) +# define PBIST_PBISTID(n) ((uint32_t)(n) << PBIST_PBISTID_SHIFT) + /* Override Register */ -#define PBIST_OVER_ -/* Fail Status Fail Register 0 */ -#define PBIST_FSRF0_ -/* Fail Status Count Register 0 */ -#define PBIST_FSRC0_ -/* Fail Status Count Register 1 */ -#define PBIST_FSRC1_ -/* Fail Status Address 0 Register */ -#define PBIST_FSRA0_ -/* Fail Status Address 1 Register */ -#define PBIST_FSRA1_ -/* Fail Status Data Register 0 */ -#define PBIST_FSRDL0_ -/* Fail Status Data Register 1 */ -#define PBIST_FSRDL1_ + +#define PBIST_OVER_OVER0 (1 << 0) /* Bit 0: RINFO Override Bit */ + +/* Fail Status Fail Register 0/1 */ + +#define PBIST_FSRF (1 << 0) /* Bit 0: Fail Status */ + +/* Fail Status Count Register 0/1 */ + +#define PBIST_FSRC_SHIFT (0) /* Bits 0-7: Failure status count */ +#define PBIST_FSRC_MASK (0xff << PBIST_FSRC0_SHIFT) + +/* Fail Status Address 0/1 Register */ + +#define PBIST_FSRA_SHIFT (0) /* Bits 0-15: Failure status address */ +#define PBIST_FSRA_MASK (0xffff << PBIST_FSRA_SHIFT) + +/* Fail Status Data Register 0/1 (32-bit data) */ + /* ROM Mask Register */ -#define PBIST_ROM_ + +#define PBIST_ROM_SHIFT (0) /* Bits 0-1: ROM Mask */ +#define PBIST_ROM_MASK (3 << PBIST_ROM_SHIFT) +# define PBIST_ROM_NONE (0 << PBIST_ROM_SHIFT) /* No information used from ROM */ +# define PBIST_ROM_RAMINFO (1 << PBIST_ROM_SHIFT) /* Only RAM Group information from ROM */ +# define PBIST_ROM_ALGOINFO (2 << PBIST_ROM_SHIFT) /* Only Algorithm information from ROM */ +# define PBIST_ROM_BOTH (3 << PBIST_ROM_SHIFT) /* Both Algorithm and RAM information from ROM */ + /* ROM Algorithm Mask Register */ -#define PBIST_ALGO_ + +#define PBIST_ALGO_TripleReadSlow (1 << 0) +#define PBIST_ALGO_TripleReadFast (1 << 1) +#define PBIST_ALGO_March13N_DP (1 << 2) +#define PBIST_ALGO_March13N_SP (1 << 3) +#define PBIST_ALGO_DOWN1a_DP (1 << 4) +#define PBIST_ALGO_DOWN1a_SP (1 << 5) +#define PBIST_ALGO_MapColumn_DP (1 << 6) +#define PBIST_ALGO_MapColumn_SP (1 << 7) +#define PBIST_ALGO_Precharge_DP (1 << 8) +#define PBIST_ALGO_Precharge_SP (1 << 9) +#define PBIST_ALGO_DTXN2a_DP (1 << 10) +#define PBIST_ALGO_DTXN2a_SP (1 << 11) +#define PBIST_ALGO_PMOSOpen_DP (1 << 12) +#define PBIST_ALGO_PMOSOpen_SP (1 << 13) +#define PBIST_ALGO_PPMOSOpenSlice1_DP (1 << 14) +#define PBIST_ALGO_PPMOSOpenSlice1_SP (1 << 15) +#define PBIST_ALGO_PPMOSOpenSlice2_DP (1 << 16) +#define PBIST_ALGO_PPMOSOpenSlice2_SP (1 << 17) /* RAM Info Mask Lower Register */ -#define PBIST_RINFOL(n) (1 << ((n)-1)) /* Bit n: Select RAM group n+1 */ -# define PBIST_RINFOL_PBIST_ROM PBIST_RINFOL(PBIST_PBIST_ROM_GROUP) -# define PBIST_RINFOL_STC_ROM PBIST_RINFOL(PBIST_STC_ROM_GROUP) -# define PBIST_RINFOL_DCAN1_RAM PBIST_RINFOL(PBIST_DCAN1_RAM_GROUP) -# define PBIST_RINFOL_DCAN2_RAM PBIST_RINFOL(PBIST_DCAN2_RAM_GROUP) -# define PBIST_RINFOL_ESRAM1_RAM PBIST_RINFOL(PBIST_ESRAM1_RAM_GROUP) -# define PBIST_RINFOL_MIBSPI1_RAM PBIST_RINFOL(PBIST_MIBSPI1_RAM_GROUP) -# define PBIST_RINFOL_VIM_RAM PBIST_RINFOL(PBIST_VIM_RAM_GROUP) -# define PBIST_RINFOL_MIBADC_RAM PBIST_RINFOL(PBIST_MIBADC_RAM_GROUP) -# define PBIST_RINFOL_N2HET_RAM PBIST_RINFOL(PBIST_N2HET_RAM_GROUP) -# define PBIST_RINFOL_HET_TU_RAM PBIST_RINFOL(PBIST_HET_TU_RAM_GROUP) +#define PBIST_RINFOL(n) (1 << ((n)-1)) /* Bit n: Select RAM group n+1 */ +# define PBIST_RINFOL_PBIST_ROM PBIST_RINFOL(PBIST_PBIST_ROM_GROUP) +# define PBIST_RINFOL_STC_ROM PBIST_RINFOL(PBIST_STC_ROM_GROUP) +# define PBIST_RINFOL_DCAN1_RAM PBIST_RINFOL(PBIST_DCAN1_RAM_GROUP) +# define PBIST_RINFOL_DCAN2_RAM PBIST_RINFOL(PBIST_DCAN2_RAM_GROUP) +# define PBIST_RINFOL_ESRAM1_RAM PBIST_RINFOL(PBIST_ESRAM1_RAM_GROUP) +# define PBIST_RINFOL_MIBSPI1_RAM PBIST_RINFOL(PBIST_MIBSPI1_RAM_GROUP) +# define PBIST_RINFOL_VIM_RAM PBIST_RINFOL(PBIST_VIM_RAM_GROUP) +# define PBIST_RINFOL_MIBADC_RAM PBIST_RINFOL(PBIST_MIBADC_RAM_GROUP) +# define PBIST_RINFOL_N2HET_RAM PBIST_RINFOL(PBIST_N2HET_RAM_GROUP) +# define PBIST_RINFOL_HET_TU_RAM PBIST_RINFOL(PBIST_HET_TU_RAM_GROUP) /* RAM Info Mask Upper Register */ -#define PBIST_RINFOU_ #endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_PBIST_H */ diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/chip/tms570_sys.h index 02227702e8..af6f4c9752 100644 --- a/arch/arm/src/tms570/chip/tms570_sys.h +++ b/arch/arm/src/tms570/chip/tms570_sys.h @@ -318,16 +318,16 @@ /* Peripheral Asynchronous Clock Source Register */ -#define SYS_VCLKASRC_VCLKA1S_SHIFT (0) /* Bits 0-3: Peripheral asynchronous clock1 source */ -#define SYS_VCLKASRC_VCLKA1S_MASK (15 << SYS_VCLKASRC_VCLKA1S_SHIFT) -# define SYS_VCLKASRC_VCLKA1S_SRC0 (0 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source0 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC1 (1 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source1 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC2 (2 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source2 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC3 (3 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source3 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC4 (4 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source4 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC5 (5 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source5 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC6 (6 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source6 for RTICLK1 */ -# define SYS_VCLKASRC_VCLKA1S_SRC7 (7 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source7 for RTICLK1 */ +#define SYS_VCLKASRC_VCLKA1S_SHIFT (0) /* Bits 0-3: Peripheral asynchronous clock1 source */ +#define SYS_VCLKASRC_VCLKA1S_MASK (15 << SYS_VCLKASRC_VCLKA1S_SHIFT) +# define SYS_VCLKASRC_VCLKA1S_SRC0 (0 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source0 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC1 (1 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source1 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC2 (2 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source2 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC3 (3 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source3 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC4 (4 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source4 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC5 (5 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source5 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC6 (6 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source6 for RTICLK1 */ +# define SYS_VCLKASRC_VCLKA1S_SRC7 (7 << SYS_VCLKASRC_VCLKA1S_SHIFT) /* Clock source7 for RTICLK1 */ # define SYS_VCLKASRC_VCLKA1S(n) ((uint32_t)(n) << SYS_VCLKASRC_VCLKA1S_SHIFT) # define SYS_VCLKASRC_VCLKA1S_OSC SYS_VCLKASRC_VCLKA1S(SYS_CLKSRC_OSC) @@ -341,45 +341,55 @@ /* RTI Clock Source Register */ -#define SYS_RCLKSRC_RTI1SRC_SHIFT (0) /* Bits 0-3: RTI clock1 source */ -#define SYS_RCLKSRC_RTI1SRC_MASK (15 << SYS_RCLKSRC_RTI1SRC_SHIFT) -# define SYS_RCLKSRC_RTI1SRC_SRC0 (0 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source0 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC1 (1 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source1 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC2 (2 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source2 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC3 (3 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source3 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC4 (4 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source4 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC5 (5 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source5 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC6 (6 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source6 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC_SRC7 (7 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source7 for RTICLK1 */ +#define SYS_RCLKSRC_RTI1SRC_SHIFT (0) /* Bits 0-3: RTI clock1 source */ +#define SYS_RCLKSRC_RTI1SRC_MASK (15 << SYS_RCLKSRC_RTI1SRC_SHIFT) +# define SYS_RCLKSRC_RTI1SRC_SRC0 (0 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source0 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC1 (1 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source1 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC2 (2 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source2 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC3 (3 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source3 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC4 (4 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source4 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC5 (5 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source5 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC6 (6 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source6 for RTICLK1 */ +# define SYS_RCLKSRC_RTI1SRC_SRC7 (7 << SYS_RCLKSRC_RTI1SRC_SHIFT) /* Clock source7 for RTICLK1 */ -# define SYS_RCLKSRC_RTI1SRC(n) ((uint32_t)(n) << SYS_RCLKSRC_RTI1SRC_SHIFT) -# define SYS_RCLKSRC_RTI1SRC_OSC SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_OSC) -# define SYS_RCLKSRC_RTI1SRC_PLL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL1) -# define SYS_RCLKSRC_RTI1SRC_EXTERNAL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL1) -# define SYS_RCLKSRC_RTI1SRC_LPOLOW SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOLOW) -# define SYS_RCLKSRC_RTI1SRC_LPOHIGH SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOHIGH) -# define SYS_RCLKSRC_RTI1SRC_PLL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL2) -# define SYS_RCLKSRC_RTI1SRC_EXTERNAL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL2) -# define SYS_RCLKSRC_RTI1SRC_VCLK SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_VCLK) +# define SYS_RCLKSRC_RTI1SRC(n) ((uint32_t)(n) << SYS_RCLKSRC_RTI1SRC_SHIFT) +# define SYS_RCLKSRC_RTI1SRC_OSC SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_OSC) +# define SYS_RCLKSRC_RTI1SRC_PLL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL1) +# define SYS_RCLKSRC_RTI1SRC_EXTERNAL1 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL1) +# define SYS_RCLKSRC_RTI1SRC_LPOLOW SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOLOW) +# define SYS_RCLKSRC_RTI1SRC_LPOHIGH SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_LPOHIGH) +# define SYS_RCLKSRC_RTI1SRC_PLL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_PLL2) +# define SYS_RCLKSRC_RTI1SRC_EXTERNAL2 SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_EXTERNAL2) +# define SYS_RCLKSRC_RTI1SRC_VCLK SYS_RCLKSRC_RTI1SRC(SYS_CLKSRC_VCLK) -#define SYS_RCLKSRC_RTI1DIV_SHIFT (8) /* Bits 8-9: RTI clock 1 divider */ -#define SYS_RCLKSRC_RTI1DIV_MASK (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) -# define SYS_RCLKSRC_RTI1DIV_DIV1 (0 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 1 */ -# define SYS_RCLKSRC_RTI1DIV_DIV2 (1 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 2 */ -# define SYS_RCLKSRC_RTI1DIV_DIV4 (2 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 4 */ -# define SYS_RCLKSRC_RTI1DIV_DIV8 (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 8 */ +#define SYS_RCLKSRC_RTI1DIV_SHIFT (8) /* Bits 8-9: RTI clock 1 divider */ +#define SYS_RCLKSRC_RTI1DIV_MASK (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) +# define SYS_RCLKSRC_RTI1DIV_DIV1 (0 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 1 */ +# define SYS_RCLKSRC_RTI1DIV_DIV2 (1 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 2 */ +# define SYS_RCLKSRC_RTI1DIV_DIV4 (2 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 4 */ +# define SYS_RCLKSRC_RTI1DIV_DIV8 (3 << SYS_RCLKSRC_RTI1DIV_SHIFT) /* RTICLK1 divider value is 8 */ /* Clock Source Valid Status Register */ -#define SYS_CSVSTAT_ + +#define SYS_CSVSTAT_CLKSR0V (1 << 0) /* Bit 0: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR1V (1 << 1) /* Bit 1: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR3V (1 << 3) /* Bit 3: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR4V (1 << 4) /* Bit 4: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSR5V (1 << 5) /* Bit 5: Clock source xx valid */ +#define SYS_CSVSTAT_CLKSRVALL (0x3b) /* Memory Self-Test Global Control Register */ -#define SYS_MSTGCR_CLKSR0V (1 << 0) /* Bit 0: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR1V (1 << 1) /* Bit 1: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR3V (1 << 3) /* Bit 3: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR4V (1 << 4) /* Bit 4: Clock source xx valid */ -#define SYS_MSTGCR_CLKSR5V (1 << 5) /* Bit 5: Clock source xx valid */ -#define SYS_MSTGCR_CLKSRVALL (0x3b) +#define SYS_MSTGCR_MSTGENA_SHIFT (0) /* Bits 0-3: Memory self-test controller global enable key */ +#define SYS_MSTGCR_MSTGENA_MASK (15 << SYS_MSTGCR_MSTGENA_SHIFT) +# define SYS_MSTGCR_MSTGENA_ENABLE (10 << SYS_MSTGCR_MSTGENA_SHIFT) +# define SYS_MSTGCR_MSTGENA_DISABLE (5 << SYS_MSTGCR_MSTGENA_SHIFT) +#define SYS_MSTGCR_ROMDIV_SHIFT (8) /* Bits 8-9: Prescaler divider bits for ROM clock source */ +#define SYS_MSTGCR_ROMDIV_MASK (3 << SYS_MSTGCR_ROMDIV_SHIFT) +# define SYS_MSTGCR_ROMDIV_DIV1 (0 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCL/1; PBIST reset=16 VBUS cycles */ +# define SYS_MSTGCR_ROMDIV_DIV2 (1 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCLK/2; PBIST reset=32 VBUS cycles */ +# define SYS_MSTGCR_ROMDIV_DIV4 (2 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCLK/4. PBIST reset=64 VBUS cycles */ +# define SYS_MSTGCR_ROMDIV_DIV8 (3 << SYS_MSTGCR_ROMDIV_SHIFT) /* ROM clock=HCLK/8. PBIST reset=96 VBUS cycles */ /* Memory Hardware Initialization Global Control Register */ @@ -389,8 +399,6 @@ /* Memory Self-Test/Initialization Enable Register */ -#define SYS_MSIENA_ - #if defined(CONFIG_ARCH_CHIP_TMS570LS0332PZ) || defined(CONFIG_ARCH_CHIP_TMS570LS0432PZ) /* From TMS570LS0x32 Data Sheet */ diff --git a/arch/arm/src/tms570/tms570_boot.c b/arch/arm/src/tms570/tms570_boot.c index f4abd925e8..fb893b8eec 100644 --- a/arch/arm/src/tms570/tms570_boot.c +++ b/arch/arm/src/tms570/tms570_boot.c @@ -234,7 +234,7 @@ void arm_boot(void) /* Run the memory selftest on CPU RAM. */ tms570_memtest_start(PBIST_RINFOL_ESRAM1_RAM); - ASSERT(tms570_memtest_complete() == 0); + ASSERT(tms570_memtest_complete() == OK); #endif /* CONFIG_TMS570_SELFTEST */ /* Initialize CPU RAM. */ @@ -272,7 +272,7 @@ void arm_boot(void) /* Wait for the memory test to complete */ - ASSERT(tms570_memtest_complete() == 0); + ASSERT(tms570_memtest_complete() == OK); #endif /* CONFIG_TMS570_SELFTEST */ /* Release the MibSPI1 modules from local reset. */ diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c index a92b2b60b8..2e8b76a480 100644 --- a/arch/arm/src/tms570/tms570_clockconfig.c +++ b/arch/arm/src/tms570/tms570_clockconfig.c @@ -440,7 +440,7 @@ static void tms570_clocksrc_configure(void) { /* Get the set of valid clocks */ - csvstat = getreg32(TMS570_SYS_CSVSTAT) & SYS_MSTGCR_CLKSRVALL; + csvstat = getreg32(TMS570_SYS_CSVSTAT) & SYS_CSVSTAT_CLKSRVALL; /* Get the (inverted) state of each clock. Inverted so that '1' means * ON not OFF. diff --git a/arch/arm/src/tms570/tms570_selftest.c b/arch/arm/src/tms570/tms570_selftest.c index eba0f3deed..2739ffd3dc 100644 --- a/arch/arm/src/tms570/tms570_selftest.c +++ b/arch/arm/src/tms570/tms570_selftest.c @@ -20,9 +20,10 @@ * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. + * 3. Neither the name NuttX, Texas Instruments Incorporated, nor the + * names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT @@ -45,8 +46,14 @@ #include +#include #include +#include +#include "up_arch.h" + +#include "chip/tms570_sys.h" +#include "chip/tms570_pbist.h" #include "tms570_selftest.h" #ifdef CONFIG_TMS570_SELFTEST @@ -55,6 +62,157 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pbist_memtest_start + * + * Description: + * This function performs Memory Built-in Self test using PBIST module. + * + * Input Parameters: + * rinfol - The OR of each RAM grouping bit. See the PBIST_RINFOL* + * definitions in chip/tms570_pbist.h + * algomask - The list of algorithms to be run. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pbist_memtest_start(uint32_t rinfol, uint32_t algomask) +{ + uint32_t regval; + volatile int i; + + /* PBIST ROM clock frequency = HCLK frequency /2 */ + + regval = getreg32(TMS570_SYS_MSTGCR); + regval &= ~SYS_MSTGCR_ROMDIV_MASK; + regval |= SYS_MSTGCR_ROMDIV_DIV2; + putreg32(regval, TMS570_SYS_MSTGCR); + + /* Enable PBIST controller */ + + putreg32(SYS_MSIENA_RAM, TMS570_SYS_MSIENA); + + /* clear MSTGENA field */ + + regval = getreg32(TMS570_SYS_MSTGCR); + regval &= ~SYS_MSTGCR_MSTGENA_MASK; + putreg32(regval, TMS570_SYS_MSTGCR); + + /* Enable PBIST self-test */ + + regval |= SYS_MSTGCR_MSTGENA_ENABLE; + putreg32(regval, TMS570_SYS_MSTGCR); + + /* Wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + + for (i = 0; i < (32 + (32 * 0)); i++); + + /* Enable PBIST clocks and ROM clock */ + + regval = (PBIST_PACT_PACT0 | PBIST_PACT_PACT1); + putreg32(regval, TMS570_PBIST_PACT); + + /* Select all algorithms to be tested */ + + putreg32(algomask, TMS570_PBIST_ALGO); + + /* Select RAM groups */ + + putreg32(rinfol, TMS570_PBIST_RINFOL); + + /* Select all RAM groups */ + + putreg32(0, TMS570_PBIST_RINFOU); + + /* ROM contents will not override RINFOx settings */ + + putreg32(0, TMS570_PBIST_OVER); + + /* Algorithm code is loaded from ROM */ + + putreg32(PBIST_ROM_BOTH, TMS570_PBIST_ROM); + + /* Start PBIST */ + + regval = (PBIST_DLR_DLR2 | PBIST_DLR_DLR4); + putreg32(PBIST_ROM_BOTH, TMS570_PBIST_DLR); +} + +/**************************************************************************** + * Name: pbist_test_complete + * + * Description: + * Return true if the PBIST test is completed + * + * Input Parameters: + * None + * + * Returned Value: + * true if the PBIST test is compelte + * + ****************************************************************************/ + +static inline bool pbist_test_complete(void) +{ + return ((getreg32(TMS570_SYS_MSTCGSTAT) & SYS_MSTCGSTAT_MSTDONE) != 0); +} + +/**************************************************************************** + * Name: pbist_test_passed + * + * Description: + * Return true if the PBIST test passed + * + * Input Parameters: + * None + * + * Returned Value: + * true if the PBIST test passed + * + ****************************************************************************/ + +static inline bool pbist_test_passed(void) +{ + return ((getreg32(TMS570_PBIST_FSRF0) & PBIST_FSRF) == 0 && + (getreg32(TMS570_PBIST_FSRF1) & PBIST_FSRF) == 0); +} + +/**************************************************************************** + * Name: pbist_stop + * + * Description: + * This function is called to stop PBIST after test is performed. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void pbist_stop(void) +{ + uint32_t regval; + + /* Disable PBIST clocks and ROM clock */ + + putreg32(0, TMS570_PBIST_PACT); + + regval = getreg32(TMS570_SYS_MSTGCR); + regval &= ~SYS_MSTGCR_MSTGENA_MASK; + putreg32(regval, TMS570_SYS_MSTGCR); + + regval |= SYS_MSTGCR_MSTGENA_DISABLE; + putreg32(regval, TMS570_SYS_MSTGCR); +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -70,6 +228,9 @@ * that the PBIST controller is capable of detecting and indicating a * memory self-test failure. * + * Returned Value: + * None + * ****************************************************************************/ void tms570_memtest_selftest(void) @@ -84,15 +245,18 @@ void tms570_memtest_selftest(void) * Start the memory test on the selecte set of RAMs. This test does not * return until the memory test is completed. * - * Input Paramters: + * Input Parameters: * rinfol - The OR of each RAM grouping bit. See the PBIST_RINFOL* * definitions in chip/tms570_pbist.h * + * Returned Value: + * None + * ****************************************************************************/ void tms570_memtest_start(uint32_t rinfol) { -#warning Missing Logic + pbist_memtest_start(rinfol, PBIST_ALGO_March13N_SP); } /**************************************************************************** @@ -109,8 +273,22 @@ void tms570_memtest_start(uint32_t rinfol) int tms570_memtest_complete(void) { -#warning Missing Logic - return 0; + bool pass; + /* Wait for the test to complete */ + + while (!pbist_test_complete()); + + /* Get the test result */ + + pass = pbist_test_passed(); + + /* Disable PBIST clocks and disable memory self-test mode */ + + pbist_stop(); + + /* Then return the test result */ + + return pass ? OK : ERROR; } /****************************************************************************