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Costmetic changes from review of last PR.

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This commit is contained in:
Gregory Nutt 2017-02-07 17:16:56 -06:00 committed by David Sidrane
parent 7262a788c4
commit a292da29d0
6 changed files with 33 additions and 24 deletions
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16
arch/arm/include/kinetis/kinetis_mcg.h
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@ -33,6 +33,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H
@ -56,8 +57,9 @@
* 2/5/2017, the catch all KINETIS_MCG_VERSION_UKN configuration is assigned
* to all the chips that did not have any conditional compilation based on
* NEW_MCG or KINETIS_K64. This is a "No worse" than the original code solution.
* N.B. Each original chip "if"definitions have been left intact so that the complete
* legacy definitions prior to 2/5/2017 may be filled in completely when vetted.
* N.B. Each original chip "if"definitions have been left intact so that the
* complete legacy definitions prior to 2/5/2017 may be filled in completely when
* vetted.
*/
/* MCG Configuration Parameters
@ -65,7 +67,8 @@
* KINETIS_MCG_PLL_REF_MIN - OSCCLK/PLL_R minimum
* KINETIS_MCG_PLL_REF_MAX - OSCCLK/PLL_R maximum
* KINETIS_MCG_PLL_INTERNAL_DIVBY - The PLL clock is divided by n before VCO divider
* KINETIS_MCG_HAS_PLL_EXTRA_DIVBY - Is PLL clock divided by n before MCG PLL/FLL clock selection in the SIM module
* KINETIS_MCG_HAS_PLL_EXTRA_DIVBY - Is PLL clock divided by n before MCG PLL/FLL
* clock selection in the SIM module
* KINETIS_MCG_FFCLK_DIVBY - MCGFFCLK divided by n
* KINETIS_MCG_HAS_IRC_48M - Has 48MHz internal oscillator
* KINETIS_MCG_HAS_LOW_FREQ_IRC - Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]
@ -347,9 +350,9 @@
# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
@ -439,6 +442,7 @@
* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
*/
#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)

2
arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
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@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_k64memorymap.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

17
arch/arm/src/kinetis/chip/kinetis_mcg.h
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@ -40,12 +40,15 @@
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define KINETIS_MCG_C1_OFFSET 0x0000 /* MCG Control 1 Register */
@ -306,7 +309,7 @@
#if defined(KINETIS_MCG_HAS_C7)
# if defined(KINETIS_MCG_HAS_C7_OSCSEL)
# define MCG_C7_OSCSEL_SHIFT (0) /* Bits 0-[1]: MCG OSC Clock Select */
# define MCG_C7_OSCSEL_SHIFT (0) /* Bits 0-[1]: MCG OSC Clock Select */
# define MCG_C7_OSCSEL_MASK (KINETIS_MCG_C7_OSCSEL_MASK << MCG_C7_OSCSEL_SHIFT)
# define MCG_C7_OSCSEL_OSCCLK (0 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK) */
# define MCG_C7_OSCSEL_32KHZ (1 << MCG_C7_OSCSEL_SHIFT) /* Selects 32 kHz RTC Oscillator */
@ -320,7 +323,7 @@
#if defined(KINETIS_MCG_HAS_C8)
# if defined(KINETIS_MCG_HAS_C8_LOCS1)
# define MCG_C8_LOCS1 (1 << 0) /* Bit 0: RTC Loss of Clock Status */
# define MCG_C8_LOCS1 (1 << 0) /* Bit 0: RTC Loss of Clock Status */
# endif
/* Bits 1-4: Reserved */
# if defined(KINETIS_MCG_HAS_C8_CME1)
@ -353,9 +356,9 @@
/* MCG Control 10 Register */
#if defined(KINETIS_MCG_HAS_C10)
/* Bits 0-[1]: Reserved */
/* Bits 0-[1]: Reserved */
# if defined(KINETIS_MCG_HAS_C10_LOCS1)
# define MCG_C10_LOCS1_SHIFT (1 << 1) /* Bit 1: RTC Loss of Clock Status */
# define MCG_C10_LOCS1_SHIFT (1 << 1) /* Bit 1: RTC Loss of Clock Status */
# endif
# define MCG_C10_EREFS1 (1 << 2) /* Bit 2: External Reference Select */
# define MCG_C10_HGO1 (1 << 3) /* Bit 3: High Gain Oscillator1 Select */
@ -364,7 +367,7 @@
# define MCG_C10_RANGE_LOW (0 << MCG_C10_RANGE_SHIFT) /* Oscillator of 32 kHz to 40 kHz */
# define MCG_C10_RANGE_HIGH (1 << MCG_C10_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */
# define MCG_C10_RANGE_VHIGH (2 << MCG_C10_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */
/* Bit 6: Reserved */
/* Bit 6: Reserved */
# define MCG_C10_LOCRE2 (1 << 7) /* Bit 7: OSC1 Loss of Clock Reset Enable */
#endif
@ -407,11 +410,11 @@
# define MCG_S2_LOCS2_SHIFT (1 << 0) /* Bit 0: OSC1 Loss of Clock Status */
# define MCG_S2_OSCINIT1 (1 << 1) /* Bit 1: OSC1 Initialization */
# endif
/* Bits 2-3: Reserved */
/* Bits 2-3: Reserved */
# if defined(KINETIS_MCG_HAS_S2_PLLCST)
# define MCG_S2_PLLCST (1 << 4) /* Bit 4: PLL Clock Select Status */
# endif
/* Bit 5: Reserved */
/* Bit 5: Reserved */
# if defined(KINETIS_MCG_HAS_S2_PLL1OSC1)
# define MCG_S2_LOCK1 (1 << 6) /* Bit 6: Lock1 Status */
# define MCG_S2_LOLS1 (1 << 7) /* Bit 7: Loss of Lock1 Status */

18
arch/arm/src/kinetis/kinetis_clockconfig.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_clockconfig.c
*
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -128,26 +128,27 @@
/* Do some sanity checking */
#if BOARD_PRDIV > KINETIS_MCG_C5_PRDIV_MAX || \
BOARD_PRDIV < KINETIS_MCG_C5_PRDIV_BASE
BOARD_PRDIV < KINETIS_MCG_C5_PRDIV_BASE
# error BOARD_PRDIV must satisfy KINETIS_MCG_C5_PRDIV_BASE >= \
BOARD_VDIV <= KINETIS_MCG_C5_PRDIV_MAX
#endif
#if BOARD_VDIV > KINETIS_MCG_C6_VDIV_MAX || \
BOARD_VDIV < KINETIS_MCG_C6_VDIV_BASE
BOARD_VDIV < KINETIS_MCG_C6_VDIV_BASE
# error BOARD_VDIV must satisfy KINETIS_MCG_C6_VDIV_BASE >= \
BOARD_VDIV <= KINETIS_MCG_C6_VDIV_MAX
#endif
#if BOARD_PLLIN_FREQ < KINETIS_MCG_PLL_REF_MIN || \
BOARD_PLLIN_FREQ > KINETIS_MCG_PLL_REF_MAX
BOARD_PLLIN_FREQ > KINETIS_MCG_PLL_REF_MAX
# error BOARD_PLLIN_FREQ must satisfy KINETIS_MCG_PLL_REF_MIN >= \
BOARD_PLLIN_FREQ <= KINETIS_MCG_PLL_REF_MAX
BOARD_PLLIN_FREQ <= KINETIS_MCG_PLL_REF_MAX
#endif
#if ((BOARD_FRDIV & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT) > KINETIS_MCG_C1_FRDIV_MAX
# error BOARD_FRDIV choice is not supported on this SoC
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@ -223,7 +224,8 @@ void kinetis_pllconfig(void)
* LOCRE0 = 0 if not supported or value provided by board
*/
putreg8(BOARD_MCG_C2_LOCRE0 | BOARD_MCG_C2_FCFTRIM | BOARD_MGC_C2_HGO | MCG_C2_RANGE_VHIGH | MCG_C2_EREFS, KINETIS_MCG_C2);
putreg8(BOARD_MCG_C2_LOCRE0 | BOARD_MCG_C2_FCFTRIM | BOARD_MGC_C2_HGO |
MCG_C2_RANGE_VHIGH | MCG_C2_EREFS, KINETIS_MCG_C2);
# endif
#endif /* defined(BOARD_MCG_C2) */
@ -249,11 +251,11 @@ void kinetis_pllconfig(void)
putreg8(BOARD_FRDIV | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
#ifndef BOARD_EXTCLOCK
/* If we aren't using an oscillator input we don't need to wait for the
* oscillator to initialize
*/
#ifndef BOARD_EXTCLOCK
while ((getreg8(KINETIS_MCG_S) & MCG_S_OSCINIT) == 0);
#endif
@ -438,7 +440,7 @@ void __ramfunc__
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4)
{
uint32_t regval;
int i;
volatile int i;
/* Save the current value of the Flash Access Protection Register */

2
configs/freedom-k64f/include/board.h
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@ -1,7 +1,7 @@
/************************************************************************************
* configs/freedom-k64f/include/board.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

2
configs/teensy-3.x/include/board.h
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@ -2,7 +2,7 @@
* configs/teensy-3.x/include/board.h
* include/arch/board/board.h
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without