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arch/arm/src/tiva: Add CC13xx PRCM support library.

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This commit is contained in:
Gregory Nutt 2018-12-08 12:35:15 -06:00
parent 7aefd5a45f
commit a2a7b1d664
9 changed files with 1689 additions and 188 deletions
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4
arch/arm/src/tiva/Make.defs
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@ -93,9 +93,9 @@ CHIP_CSRCS += tiva_start.c lm4f_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
CHIP_CSRCS += tiva_start.c tm4c_gpio.c tiva_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_gpio.c cc13xx_gpioirq.c
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_gpio.c cc13xx_gpioirq.c
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
endif
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)

17
arch/arm/src/tiva/cc13xx/cc13xx_gpio.h
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@ -1,5 +1,5 @@
/****************************************************************************
* arch/arm/src/tiva/cc13x0/cc13x0_gpio.h
* arch/arm/src/tiva/cc13xx/cc13xx_gpio.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -35,8 +35,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H
#define __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_GPIO_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_GPIO_H
/****************************************************************************
* Included Files
@ -246,8 +246,17 @@
#define GPIO_DIO_MASK (0x1f << GPIO_PORTID_SHIFT)
# define GPIO_DIO(n) ((uint32_t)(n) << GPIO_PORTID_SHIFT)
/* Helper Definitions *******************************************************/
#define GPIO_STD_INPUT (GPIO_IOCURR_2MA | GPIO_IOSTR_AUTO | \
GPIO_PULL_DISABLE | GPIO_EDGE_NONE | \
GPIO_IOMODE_NORMAL | GPIO_IE)
#define GPIO_STD_OUTPUT (GPIO_IOCURR_2MA | GPIO_IOSTR_AUTO | \
GPIO_PULL_DISABLE | GPIO_EDGE_NONE | \
GPIO_IOMODE_NORMAL)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H */
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_GPIO_H */

748
arch/arm/src/tiva/cc13xx/cc13xx_prcm.c Normal file
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@ -0,0 +1,748 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's prcm.c file (revision 49363) which has a fully
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.y>
#include <stdint.h>
#include <assert.h>
#include "cc13xx/cc13xx_prcm.h"
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/* This macro extracts the array index out of the peripheral number */
#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf)
/* This macro extracts the peripheral instance number and generates bit mask */
#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f))
/* The size of a register look-up table */
#define TABLE_SIZE 7
/******************************************************************************
* Private Data
******************************************************************************/
/* Arrays that maps the "peripheral set" number (which is stored in
* bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that
* contains the relevant bit for that peripheral.
*/
/* Run mode registers */
static const uintptr_t g_rcgcr_base[TABLE_SIZE] =
{
TIVA_PRCM_GPTCLKGR, /* Index 0 */
TIVA_PRCM_SSICLKGR, /* Index 1 */
TIVA_PRCM_UARTCLKGR, /* Index 2 */
TIVA_PRCM_I2CCLKGR, /* Index 3 */
TIVA_PRCM_SECDMACLKGR, /* Index 4 */
TIVA_PRCM_GPIOCLKGR, /* Index 5 */
TIVA_PRCM_I2CCLKGR /* Index 6 */
};
/* Sleep mode registers */
static const uintptr_t g_scgcr_base[TABLE_SIZE] =
{
TIVA_PRCM_GPTCLKGS, /* Index 0 */
TIVA_PRCM_SSICLKGS, /* Index 1 */
TIVA_PRCM_UARTCLKGS, /* Index 2 */
TIVA_PRCM_I2CCLKGS, /* Index 3 */
TIVA_PRCM_SECDMACLKGS, /* Index 4 */
TIVA_PRCM_GPIOCLKGS, /* Index 5 */
TIVA_PRCM_I2CCLKGS /* Index 6 */
};
/* Deep sleep mode registers */
static const uintptr_t g_dcgcr_base[TABLE_SIZE] =
{
TIVA_PRCM_GPTCLKGDS, /* Index 0 */
TIVA_PRCM_SSICLKGDS, /* Index 1 */
TIVA_PRCM_UARTCLKGDS, /* Index 2 */
TIVA_PRCM_I2CCLKGDS, /* Index 3 */
TIVA_PRCM_SECDMACLKGDS, /* Index 4 */
TIVA_PRCM_GPIOCLKGDS, /* Index 5 */
TIVA_PRCM_I2CCLKGDS /* Index 6 */
};
/******************************************************************************
* Public Functions
******************************************************************************/
/******************************************************************************
* Name: prcm_infclock_configure
*
* Description:
* Configure the infrastructure clock.
*
* Each System CPU power mode has its own infrastructure clock division
* factor. This function can be used for setting up the division factor for
* the infrastructure clock in the available power modes for the System CPU.
* The infrastructure clock is used for all internal logic in the PRCM, and
* is always running as long as power is on in the MCU voltage domain. This
* can be enabled and disabled from the AON Wake Up Controller.
*
* NOTE: If source clock is 48 MHz, minimum clock divider is 2.
*
* Input Parameters
* clockdiv - Determines the division ratio for the infrastructure
* clock when the device is in the specified mode. Allowed
* division factors for all three System CPU power modes are:
* {1, 2, 8, or 32}
* powermode - Determines the System CPU operation mode for which to
* modify the clock division factor. The three allowed power
* modes are:{PRCM_RUN_MODE, PRCM_SLEEP_MODE, or
* PRCM_DEEP_SLEEP_MODE}
*
******************************************************************************/
void prcm_infclock_configure(enum prcm_clkdivider_e clkdiv,
enum prcm_powermode_e powermode)
{
uint32_t divisor;
/* Find the correct division factor. */
divisor = 0;
if (clkdiv == PRCM_CLOCK_DIV_1)
{
divisor = PRCM_INFRCLKDIVR_RATIO_DIV1;
}
else if (clkdiv == PRCM_CLOCK_DIV_2)
{
divisor = PRCM_INFRCLKDIVR_RATIO_DIV2;
}
else if (clkdiv == PRCM_CLOCK_DIV_8)
{
divisor = PRCM_INFRCLKDIVR_RATIO_DIV8;
}
else if (clkdiv == PRCM_CLOCK_DIV_32)
{
divisor = PRCM_INFRCLKDIVR_RATIO_DIV32;
}
else
{
DEBUGPANIC();
}
/* Determine the correct power mode set the division factor accordingly. */
if (powermode == PRCM_RUN_MODE)
{
putreg32(divisor, TIVA_PRCM_INFRCLKDIVR);
}
else if (powermode == PRCM_SLEEP_MODE)
{
putreg32(divisor, TIVA_PRCM_INFRCLKDIVS);
}
else if (powermode == PRCM_DEEP_SLEEP_MODE)
{
putreg32(divisor, TIVA_PRCM_INFRCLKDIVDSS);
}
else
{
DEBUGPANIC();
}
}
/******************************************************************************
* Name: prcm_audioclock_manual
*
* Description:
* Configure the audio clock generation with manual setting of clock divider.
*
* NOTE: See hardware documentation before setting audio clock dividers manually.
*
* Input Parameters:
* clkconfig - The audio clock configuration. The parameter is a bitwise
* OR'ed value consisting of:
*
* 1) Phase: PRCM_I2SCLKCTL_WCLKPHASE_SINGLE or
* PRCM_I2SCLKCTL_WCLKPHASE_DUAL and
* 2) Clock polarity: PRCM_I2SCLKCTL_POSEDGE or
* PRCM_I2SCLKCTL_NEGEDGE
*
* mstdiv - The desired master clock divider.
* worddiv - The desired word clock divider.
* bitdiv - The desired bit clock divider.
*
******************************************************************************/
#ifdef CONFIG_TIVA_I2S
void prcm_audioclock_manual(uint32_t clkconfig, uint32_t mstdiv,
uint32_t bitdiv, uint32_t worddiv)
{
uint32_t regval;
DEBUGASSERT(clkconfig & ~(PRCM_I2SCLKCTL_WCLKPHASE_MASK |
PRCM_I2SCLKCTL_POSEDGE) == 0);
/* Make sure the audio clock generation is disabled before reconfiguring. */
prcm_audioclock_disable();
/* Make sure to compensate the Frame clock division factor if using single
* phase format. */
if ((clkconfig & PRCM_I2SCLKCTL_WCLKPHASE_MASK) ==
PRCM_I2SCLKCTL_WCLKPHASE_SINGLE)
{
worddiv -= 1;
}
/* Write the clock division factors. */
putreg32(mstdiv, TIVA_PRCM_I2SMCLKDIV);
putreg32(bitdiv, TIVA_PRCM_I2SBCLKDIV);
putreg32(worddiv, TIVA_PRCM_I2SWCLKDIV);
/* Configure the Word clock format and polarity. */
regval = getreg32(TIVA_PRCM_I2SCLKCTL);
retval &= ~(PRCM_I2SCLKCTL_WCLKPHASE_MASK | PRCM_I2SCLKCTL_POSEDGE);
putreg32(regval | clkconfig, TIVA_PRCM_I2SCLKCTL);
}
/******************************************************************************
* Name: prcm_audioclock_configure
*
* Description:
* Configure the audio clock generation
*
* Use this function to set the sample rate when using internal audio clock
* generation for the I2S module.
*
* NOTE: While other clocks are possible, the stability of the four sample
* rates defined here are only guaranteed if the clock input to the I2S module
* is 48MHz.
*
* Input Parameters:
* clkconfig - The audio clock configuration. The parameter is a bitwise
* OR'ed value consisting of:
*
* 1) Phase: PRCM_I2SCLKCTL_WCLKPHASE_SINGLE or
* PRCM_I2SCLKCTL_WCLKPHASE_DUAL and
* 2) Clock polarity: PRCM_I2SCLKCTL_POSEDGE or
* PRCM_I2SCLKCTL_NEGEDGE
*
* samplerate - The desired audio clock sample rate. The supported sample
* rate configurations are: {I2S_SAMPLE_RATE_16K,
* I2S_SAMPLE_RATE_24K, I2S_SAMPLE_RATE_32K, or
* I2S_SAMPLE_RATE_48K}
*
******************************************************************************/
#ifdef CONFIG_TIVA_I2S
void prcm_audioclock_configure(uint32_t clkconfig,
enum prcm_i2samplerate_e samplerate)
{
uint32_t mstdiv;
uint32_t bitdiv;
uint32_t worddiv;
DEBUGASSERT(samplerate == I2S_SAMPLE_RATE_16K ||
samplerate == I2S_SAMPLE_RATE_24K ||
samplerate == I2S_SAMPLE_RATE_32K ||
samplerate == I2S_SAMPLE_RATE_48K);
mstdiv = 0;
bitdiv = 0;
worddiv = 0;
/* Define the clock division factors for the audio interface. */
switch (samplerate)
{
case I2S_SAMPLE_RATE_16K:
mstdiv = 6;
bitdiv = 60;
worddiv = 25;
break;
case I2S_SAMPLE_RATE_24K:
mstdiv = 4;
bitdiv = 40;
worddiv = 25;
break;
case I2S_SAMPLE_RATE_32K:
mstdiv = 3;
bitdiv = 30;
worddiv = 25;
break;
case I2S_SAMPLE_RATE_48K:
mstdiv = 2;
bitdiv = 20;
worddiv = 25;
break;
}
prcm_audioclock_manual(clkconfig, mstdiv, bitdiv, worddiv);
}
#endif
/******************************************************************************
* Name: prcm_powerdomain_on
*
* Description:
* Turn power on in power domains in the MCU domain
* Use this function to turn on power domains inside the MCU voltage domain.
*
* Power on and power off request has different implications for the
* different power domains.
* - RF Core power domain:
* - Power On : Domain is on or in the process of turning on.
* - Power Off : Domain is powered down when System CPU is in deep sleep.
* The third option for the RF Core is to power down when
* the it is idle. prcm_rfpowerdown_whenidle()
* - SERIAL power domain:
* - Power on : Domain is powered on.
* - Power off : Domain is powered off.
* - PERIPHERIAL power domain:
* - Power on : Domain is powered on.
* - Power off : Domain is powered off.
* - VIMS power domain:
* - Power On : Domain is powered if Bus domain is powered.
* - Power Off : Domain is only powered when CPU domain is on.
* - BUS power domain:
* - Power On : Domain is on.
* - Power Off : Domain is on if requested by RF Core or if CPU domain
* is on.
* - CPU power domain:
* - Power On : Domain is on.
* - Power Off : Domain is powering down if System CPU is idle. This
* will also initiate a power down of the SRAM and BUS
* power domains, unless RF Core is requesting them to
* be on.
*
* NOTE: After a call to this function the status of the power domain
* should be checked using either prcm_powerdomain_status().
* Any write operation to a power domain which is still not operational can
* result in unexpected behavior.
*
* Input Parameters
* domains - Determines which power domains to turn on. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1,
* I2S, DMA, UART1
* 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
* 5) PRCM_DOMAIN_SYSBUS
* 6) PRCM_DOMAIN_CPU
*
******************************************************************************/
void prcm_powerdomain_on(uint32_t domains)
{
/* Check the arguments. */
DEBUGASSERT((domains & PRCM_DOMAIN_RFCORE) != 0 ||
(domains & PRCM_DOMAIN_SERIAL) != 0 ||
(domains & PRCM_DOMAIN_PERIPH) != 0 ||
(domains & PRCM_DOMAIN_CPU) != 0 ||
(domains & PRCM_DOMAIN_VIMS) != 0);
/* Assert the request to power on the right domains. */
if ((domains & PRCM_DOMAIN_RFCORE) != 0)
{
putreg32(PRCM_PDCTL0RFC_ON, TIVA_PRCM_PDCTL0RFC);
#ifdef CONFIG_ARCH_CHIP_CC13X0
/* The PDCTL1RFC access is meant to "be used by RFC in autonomous mode",
* but keeping it for compatibility on already ROM'ed products (since
* this is a ROM function). RFC power domain is on if (PRCM_O_PDCTL0RFC
* || PRCM_O_PDCTL1RFC).
*/
putreg32(PRCM_PDCTL1RFC_ON, TIVA_PRCM_PDCTL1RFC);
#endif
}
if ((domains & PRCM_DOMAIN_SERIAL) != 0)
{
putreg32(PRCM_PDCTL0SERIAL_ON, TIVA_PRCM_PDCTL0SERIAL);
}
if ((domains & PRCM_DOMAIN_PERIPH) != 0)
{
putreg32(PRCM_PDCTL0PERIPH_ON, TIVA_PRCM_PDCTL0PERIPH);
}
if ((domains & PRCM_DOMAIN_VIMS) != 0)
{
putreg32(PRCM_PDCTL1VIMS_ON, TIVA_PRCM_PDCTL1VIMS);
}
if ((domains & PRCM_DOMAIN_CPU) != 0)
{
putreg32(PRCM_PDCTL1CPU_ON, TIVA_PRCM_PDCTL1CPU);
}
}
/******************************************************************************
* Name: prcm_powerdomain_off
*
* Description:
* Turn off a specific power domain
* Use this function to power down domains inside the MCU voltage domain.
*
* NOTE: See prcm_powerdomain_on() for specifics regarding on/off
* configuration.
*
* Input Parameters
* domains - Determines which power domains to turn off. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1,
* I2S, DMA, UART1
* 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
* 5) PRCM_DOMAIN_SYSBUS
* 6) PRCM_DOMAIN_CPU
*
******************************************************************************/
void prcm_powerdomain_off(uint32_t domains)
{
/* Check the arguments. */
DEBUGASSERT((domains & PRCM_DOMAIN_RFCORE) != 0 ||
(domains & PRCM_DOMAIN_SERIAL) != 0 ||
(domains & PRCM_DOMAIN_PERIPH) != 0 ||
(domains & PRCM_DOMAIN_CPU) != 0 ||
(domains & PRCM_DOMAIN_VIMS) != 0);
/* Assert the request to power off the right domains. */
if (domains & PRCM_DOMAIN_RFCORE)
{
putreg32(0, TIVA_PRCM_PDCTL0RFC);
#ifdef CONFIG_ARCH_CHIP_CC13X0
/* The PDCTL1RFC access is meant to "be used by RFC in autonomous mode",
* but keeping it for compatibility on already ROM'ed products (since
* this is a ROM function). RFC power domain is on if (PRCM_O_PDCTL0RFC
* || PRCM_O_PDCTL1RFC).
*/
putreg32(0, TIVA_PRCM_PDCTL1RFC);
#endif
}
if (domains & PRCM_DOMAIN_SERIAL)
{
putreg32(0, TIVA_PRCM_PDCTL0SERIAL);
}
if (domains & PRCM_DOMAIN_PERIPH)
{
putreg32(0, TIVA_PRCM_PDCTL0PERIPH);
}
if (domains & PRCM_DOMAIN_VIMS)
{
#ifdef CONFIG_ARCH_CHIP_CC13X0
putreg32(0, TIVA_PRCM_PDCTL1VIMS);
#else
/* Write bits domains[17:16] to the VIMS_MODE alias register.
* PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP
* sets VIMS_MODE=0b10.
*/
DEBUGASSERT((domains & 0x00010000) == 0);
putreg32((domains >> 16) & 3, TIVA_PRCM_PDCTL1VIMS);
#endif
}
if (domains & PRCM_DOMAIN_CPU)
{
putreg32(0, TIVA_PRCM_PDCTL1CPU);
}
}
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
* Enables a peripheral in Run mode
*
* Peripherals are enabled with this function. At power-up, some peripherals
* are disabled; they must be enabled in order to operate or respond to
* register reads/writes.
*
* NOTE: The actual enabling of the peripheral may be delayed until some
* time after this function returns. Care should be taken to ensure that the
* peripheral is not accessed until it is enabled.
*
* When enabling Timers always make sure that the division factor for the
* PERBUSCPUCLK is set. This will guarantee that the timers run at a
* continuous rate even if the SYSBUSCLK is gated.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the
* system controller in the AON domain a call to this function should always
* be followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to enable. This is an encoded value. See the
* PRCRM_PERIPH_* definitions for available encodings.
*
******************************************************************************/
void prcm_periph_runenable(uint32_t peripheral)
{
unsigned int index;
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
/* Enable module in Run Mode. */
modifyreg32(g_rcgcr_base[index], PRCM_PERIPH_MASKBIT(peripheral), 0);
}
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
* Disables a peripheral in Run mode
*
* Peripherals are disabled with this function. Once disabled, they will not
* operate or respond to register reads/writes.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* NOTE: The actual disabling of the peripheral may be delayed until some
* time after this function returns. Care should be taken by the user to
* ensure that the peripheral is not accessed in this interval as this might
* cause the system to hang.
*
* Input Parameters:
* peripheral - The peripheral to disable. This is an encoded value. See the
* PRCRM_PERIPH_* definitions for available encodings.
*
******************************************************************************/
void prcm_periph_rundisable(uint32_t peripheral)
{
unsigned int index;
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
/* Disable module in Run Mode. */
modifyreg32(g_rcgcr_base[index], 0, PRCM_PERIPH_MASKBIT(peripheral));
}
/******************************************************************************
* Name: prcm_periph_sleepenable
*
* Description:
* Enables a peripheral in sleep mode
*
* This function allows a peripheral to continue operating when the processor
* goes into sleep mode. Since the clocking configuration of the device does
* not change, any peripheral can safely continue operating while the
* processor is in sleep mode, and can therefore wake the processor from sleep
* mode.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to enable in sleep mode. This is an encoded
* value. See the PRCRM_PERIPH_* definitions for available
* encodings.
*
******************************************************************************/
void prcm_periph_sleepenable(uint32_t peripheral)
{
unsigned int index;
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
/* Enable this peripheral in sleep mode. */
modifyreg32(g_scgcr_base[index], PRCM_PERIPH_MASKBIT(peripheral), 0);
}
/******************************************************************************
* Name: prcm_periph_sleepdisable
*
* Description:
* Disables a peripheral in sleep mode
*
* This function causes a peripheral to stop operating when the processor goes
* into sleep mode. Disabling peripherals while in sleep mode helps to lower
* the current draw of the device. If enabled (via prcm_periph_runenable()),
* the peripheral will automatically resume operation when the processor
* leaves sleep mode, maintaining its entire state from before sleep mode was
* entered.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to disable in sleep mode. This is an encoded
* value. See the PRCRM_PERIPH_* definitions for available
* encodings.
*
******************************************************************************/
void prcm_periph_sleepdisable(uint32_t peripheral)
{
unsigned int index;
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
/* Disable this peripheral in sleep mode */
modifyreg32(g_scgcr_base[index], 0, PRCM_PERIPH_MASKBIT(peripheral));
}
/******************************************************************************
* Name: prcm_periph_deepsleepenable
*
* Description:
* Enables a peripheral in deep-sleep mode
*
* This function allows a peripheral to continue operating when the processor
* goes into deep-sleep mode. Since the clocking configuration of the device
* may change, not all peripherals can safely continue operating while the
* processor is in sleep mode. This in turn depends on the chosen power mode.
* It is the responsibility of the caller to make sensible choices.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to ensable in deep sleep mode. This is an
* encoded value. See the PRCRM_PERIPH_* definitions for
* available encodings.
*
******************************************************************************/
void prcm_periph_deepsleepenable(uint32_t peripheral)
{
unsigned int index;
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
/* Enable this peripheral in sleep mode. */
modifyreg32(g_dcgcr_base[index], PRCM_PERIPH_MASKBIT(peripheral), 0);
}
/******************************************************************************
* Name: prcm_periph_deepsleepdisable
*
* Description:
* Disables a peripheral in deep-sleep mode
*
* This function causes a peripheral to stop operating when the processor goes
* into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
* to lower the current draw of the device, and can keep peripherals that
* require a particular clock frequency from operating when the clock changes
* as a result of entering deep-sleep mode. If enabled (via
* prcm_periph_runenable()), the peripheral will automatically resume
* operation when the processor leaves deep-sleep mode, maintaining its entire
* state from before deep-sleep mode was entered.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to disable in deep sleep mode. This is an
* encoded value. See the PRCRM_PERIPH_* definitions for
* available encodings.
*
******************************************************************************/
void prcm_periph_deepsleepdisable(uint32_t peripheral)
{
unsigned int index;
/* Extract the index */
index = PRCM_PERIPH_INDEX(peripheral);
DEBUGASSERT(index < TABLE_SIZE);
/* Enable this peripheral in sleep mode. */
modifyreg32(g_dcgcr_base[index], 0, PRCM_PERIPH_MASKBIT(peripheral));
}

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/****************************************************************************
* arch/arm/src/tiva/cc13xx/.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Includes definitions from TI's prcm.c file which has a fully compatible
* BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_PRCM_H
#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_PRCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Power Domains */
#define PRCM_DOMAIN_RFCORE (1 << 0) /* RF Core domain ID for
* clock/power control. */
#define PRCM_DOMAIN_SERIAL (1 << 1) /* Serial domain ID for
* clock/power control. */
#define PRCM_DOMAIN_PERIPH (1 << 2) /* Peripheral domain ID for
* clock/power control. */
#define PRCM_DOMAIN_SYSBUS (1 << 3) /* Bus domain ID for clock/power
* control. */
#define PRCM_DOMAIN_VIMS (1 << 4) /* VIMS domain ID for clock/power
* control. */
#define PRCM_DOMAIN_CPU (1 << 5) /* CPU domain ID for clock/power
* control. */
#define PRCM_DOMAIN_TIMER (1 << 6) /* GPT domain ID for clock
* control. */
#define PRCM_DOMAIN_CLKCTRL (1 << 7) /* Clock Control domain ID for
* clock/power control. */
#define PRCM_DOMAIN_MCU (1 << 8) /* Reset control for entire MCU
* domain. */
#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \
0x00020010 /* For function PRCMPowerDomainOff()
* it is an option to select that
* VIMS power domain shall not
* power up during the next wake
* up from uLDO (VIMS_MODE=0b10). */
/* Encoded values used for enabling and disabling peripheral modules in the
* MCU domain. Encoding:
*
* Bits 0-4: Defines the bit position within the register.
* Bits 8-11: Defines the index into the register offset constant tables.
*/
#define PRCM_PERIPH_TIMER0 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
#define PRCM_PERIPH_TIMER1 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
#define PRCM_PERIPH_TIMER2 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
#define PRCM_PERIPH_TIMER3 ((0 << 8) | PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
#define PRCM_PERIPH_SSI0 ((1 << 8) | PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
#define PRCM_PERIPH_SSI1 ((1 << 8) | PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
#define PRCM_PERIPH_UART0 ((2 << 8) | PRCM_UARTCLKG_CLKEN_UART0_SHIFT)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define PRCM_PERIPH_UART1 ((2 << 8) | PRCM_UARTCLKG_CLKEN_UART1_SHIFT)
#endif
#define PRCM_PERIPH_I2C0 ((3 << 8) | PRCM_I2CCLKGR_CLKEN_SHIFT)
#define PRCM_PERIPH_CRYPTO ((4 << 8) | PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_PERIPH_TRNG ((4 << 8) | PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#ifdef CONFIG_ARCH_CHIP_CC13X2
# define PRCM_PERIPH_PKA ((4 << 8) | PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
#endif
#define PRCM_PERIPH_UDMA ((4 << 8) | PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
#define PRCM_PERIPH_GPIO ((5 << 8) | PRCM_GPIOCLKG_CLKEN_SHIFT)
#define PRCM_PERIPH_I2S ((6 << 8) | PRCM_I2SCLKG_CLKEN_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
enum prcm_powermode_e
{
PRCM_RUN_MODE = 0,
PRCM_SLEEP_MODE,
PRCM_DEEP_SLEEP_MODE
};
enum prcm_clkdivider_e
{
PRCM_CLOCK_DIV_1 = 0,
PRCM_CLOCK_DIV_2,
PRCM_CLOCK_DIV_8,
PRCM_CLOCK_DIV_32
};
enum prcm_i2samplerate_e
{
I2S_SAMPLE_RATE_16K = 1,
I2S_SAMPLE_RATE_24K = 2,
I2S_SAMPLE_RATE_32K = 4,
I2S_SAMPLE_RATE_48K = 8
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: prcm_audioclock_enable
*
* Description:
* Use this function to enable the audio clock generation.
*
****************************************************************************/
#ifdef CONFIG_TIVA_I2S
static inline void prcm_audioclock_enable(void)
{
/* Enable the audio clock generation. */
modifyreg32(TIVA_PRCM_I2SCLKCTL, PRCM_I2SCLKCTL_EN, 0);
}
#endif
/****************************************************************************
* Name: prcm_audioclock_disable
*
* Description:
* Use this function to disable the audio clock generation.
*
****************************************************************************/
#ifdef CONFIG_TIVA_I2S
static inline void prcm_audioclock_disable(void)
{
/* Disable the audio clock generation */
modifyreg32(TIVA_PRCM_I2SCLKCTL, 0, PRCM_I2SCLKCTL_EN);
}
#endif
/******************************************************************************
* Name: prcm_mcuuldo_configure
*
* Description:
* Assert or de-assert a request for the uLDO.
*
* Use this function to request to switch to the micro Low Voltage Dropout
* regulator (uLDO). The uLDO has a much lower capacity for supplying power
* to the system. It is therefore imperative and solely the programmers
* responsibility to ensure that a sufficient amount of peripheral modules
* have been turned of before requesting a switch to the uLDO.
*
* NOTE: Asserting this bit has no effect until:
* 1. FLASH has accepted to be powered down
* 2. Deepsleep must be asserted
*
* Input Parameters:
* enable
* - 0 : Disable uLDO request
* - 1 : Enable uLDO request
*
******************************************************************************/
static inline void prcm_mcuuldo_configure(uint32_t enable)
{
/* Enable or disable the uLDO request signal. */
putreg32(enabled, TIVA_PRCM_VDCTL);
}
/******************************************************************************
* Name: prcm_gptclock_set
*
* Description:
* Setup the clock division factor for the GP-Timer domain.
*
* Use this function to set up the clock division factor on the GP-Timer.
*
* The division rate will be constant and ungated for Run / Sleep / DeepSleep
* mode when it is slower than PRCM_GPTCLKDIV_RATIO setting.
* When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO
* will be used.
*
* Note that the register will contain the written content even though the
* setting is faster than PRCM_GPTCLKDIV_RATIO setting.
*
* NOTE: For change to take effect, prcm_load_set() needs to be called
*
* Input Parameters:
* clkdiv - The division factor to set. The argument must be only one of
* the following values:
* PRCM_GPTCLKDIV_DIV1, PRCM_GPTCLKDIV_DIV2, PRCM_GPTCLKDIV_DIV4,
* PRCM_GPTCLKDIV_DIV8, PRCM_GPTCLKDIV_DIV16, PRCM_GPTCLKDIV_DIV32.
* PRCM_GPTCLKDIV_DIV64, PRCM_GPTCLKDIV_DIV128, PRCM_GPTCLKDIV_DIV256
*
******************************************************************************/
static inline void prcm_gptclock_set(uint32_t clkdiv)
{
putreg32(clkdiv, TIVA_PRCM_GPTCLKDIV);
}
/******************************************************************************
* Name:
*
* Description:
* Get the clock division factor for the GP-Timer domain.
*
******************************************************************************/
static inline uint32_t PRCMGPTimerClockDivisionGet(void)
{
return getreg32(TIVA_PRCM_GPTCLKDIV);
}
/******************************************************************************
* Name: prcm_load_set
*
* Description:
* Use this function to synchronize the load settings.
*
* Most of the clock settings in the PRCM module should be updated
* synchronously. This is ensured by the implementation of a load registers
* that, when written to, will let the previous written update values for all
* the relevant registers propagate through to hardware.
*
* The functions that require a synchronization of the clock settings are:
* - prcm_audioclock_manual()
* - prcm_audioclock_configure()
* - prcm_audioclock_disable()
* - prcm_domain_enable()
* - prcm_domain_disable()
* - prcm_periph_runenable()
* - prcm_periph_rundisable()
* - prcm_periph_sleepenable()
* - prcm_periph_sleepdisable()
* - prcm_periph_deepsleepenable()
* - prcm_periph_deepsleepdisable()
*
******************************************************************************/
static inline void prcm_load_set(void)
{
/* Enable the update of all load related registers. */
putreg32(PRCM_CLKLOADCTL_LOAD, TIVA_PRCM_CLKLOADCTL);
}
/******************************************************************************
* Name: prcm_load_get
*
* Description:
* Check if any of the load sensitive register has been updated.
*
* Returned Value:
* Returns status of the load sensitive register:
* - true : No registers have changed since the last load.
* - false : Any register has changed.
*
******************************************************************************/
static inline bool prcm_load_get(void)
{
/* Return the load status. */
return ((getreg32(TIVA_PRCM_CLKLOADCTL) & PRCM_CLKLOADCTL_LOADDONE) != 0);
}
/******************************************************************************
* Name: prcm_domain_enable
*
* Description:
* Enable clock domains in the MCU voltage domain.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* NOTE: Clocks will only be running if the domain is powered.
*
* domains is a bit mask containing the clock domains to enable.
* The independent clock domains inside the MCU voltage domain which can be
* configured are:
* - PRCM_DOMAIN_RFCORE
* - PRCM_DOMAIN_VIMS
*
******************************************************************************/
static inline void prcm_domain_enable(uint32_t domains)
{
DEBUGASSERT((domains & PRCM_DOMAIN_RFCORE) != 0 ||
(domains & PRCM_DOMAIN_VIMS) != 0);
/* Enable the clock domain(s). */
if ((domains & PRCM_DOMAIN_RFCORE) != 0)
{
putreg32(PRCM_RFCCLKG_CLKEN, TIVA_PRCM_RFCCLKG);
}
if ((domains & PRCM_DOMAIN_VIMS) != 0)
{
putreg32(PRCM_VIMSCLKG_CLKEN_ENA, TIVA_PRCM_VIMSCLKG);
}
}
/******************************************************************************
* Name: prcm_domain_disable
*
* Description:
* Disable clock domains in the MCU voltage domain.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* NOTE: Clocks will only be running if the domain is powered.
*
* domains is a bit mask containing the clock domains to disable.
* The independent clock domains inside the MCU voltage domain are:
* - PRCM_DOMAIN_RFCORE
* - PRCM_DOMAIN_VIMS
*
******************************************************************************/
static inline void prcm_domain_disable(uint32_t domains)
{
DEBUGASSERT((domains & PRCM_DOMAIN_RFCORE) != 0 ||
(domains & PRCM_DOMAIN_VIMS) != 0);
/* Disable the power domains. */
if ((domains & PRCM_DOMAIN_RFCORE) != 0)
{
putreg32(0, TIVA_PRCM_RFCCLKG);
}
if ((domains & PRCM_DOMAIN_VIMS) != 0)
{
putreg32(0, TIVA_PRCM_VIMSCLKG);
}
}
/******************************************************************************
* Name: prcm_rfpowerdown_whenidle
*
* Description:
* Configure RF core to power down when idle.
*
* Use this function to configure the RF core to power down when Idle. This
* is handled automatically in hardware if the RF Core reports that it is
* idle.
*
******************************************************************************/
static inline void prcm_rfpowerdown_whenidle(void)
{
/* Configure the RF power domain. */
modifyreg32(TIVA_PRCM_PDCTL0RFC, 0, PRCM_PDCTL0RFC_ON);
}
/******************************************************************************
* Name: prcm_rfready
*
* Description:
* Return the access status of the RF Core.
*
* Use this function to check if the RF Core is on and ready to be accessed.
* Accessing register or memories that are not powered and clocked will
* cause a bus fault.
*
* Returns access status of the RF Core.
* - true : RF Core can be accessed.
* - false : RF Core domain is not ready for access.
*
******************************************************************************/
static inline bool (void)
{
/* Return the ready status of the RF Core. */
return ((getreg32(TIVA_PRCM_PDSTAT1RFC) & PRCM_PDSTAT1RFC_ON) != 0);
}
/******************************************************************************
* Name: prcm_cacheretention_enable
*
* Description:
* Enable CACHE RAM retention
*
* Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM
*
******************************************************************************/
static inline void prcm_cacheretention_enable(void)
{
modifyreg32(TIVA_PRCM_RAMRETEN,
PRCM_RAMRETEN_VIMS_TRAM | PRCM_RAMRETEN_VIMS_CRAM, 0);
}
/******************************************************************************
* Name: prcm_cacheretention_disable
*
* Description:
* Disable CACHE RAM retention
*
* Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM
*
*****************************************************************************/
static inline void prcm_cacheretention_disable(void)
{
modifyreg32(TIVA_PRCM_RAMRETEN, 0, PRCM_RAMRETEN_VIMS_MASK);
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/******************************************************************************
* Name: prcm_infclock_configure
*
* Description:
* Configure the infrastructure clock.
*
* Each System CPU power mode has its own infrastructure clock division
* factor. This function can be used for setting up the division factor for
* the infrastructure clock in the available power modes for the System CPU.
* The infrastructure clock is used for all internal logic in the PRCM, and
* is always running as long as power is on in the MCU voltage domain. This
* can be enabled and disabled from the AON Wake Up Controller.
*
* NOTE: If source clock is 48 MHz, minimum clock divider is 2.
*
* Input Parameters
* clockdiv - Determines the division ratio for the infrastructure
* clock when the device is in the specified mode. Allowed
* division factors for all three System CPU power modes are:
* {1, 2, 8, or 32}
* powermode - Determines the System CPU operation mode for which to
* modify the clock division factor. The three allowed power
* modes are:{PRCM_RUN_MODE, PRCM_SLEEP_MODE, or
* PRCM_DEEP_SLEEP_MODE}
*
******************************************************************************/
void prcm_infclock_configure(uint32_t clkdiv, enum prcm_powermode_e powermode);
/******************************************************************************
* Name: prcm_audioclock_manual
*
* Description:
* Configure the audio clock generation with manual setting of clock divider.
*
* NOTE: See hardware documentation before setting audio clock dividers manually.
*
* Input Parameters:
* clkconfig - The audio clock configuration. The parameter is a bitwise
* OR'ed value consisting of:
*
* 1) Phase: PRCM_I2SCLKCTL_WCLKPHASE_SINGLE or
* PRCM_I2SCLKCTL_WCLKPHASE_DUAL and
* 2) Clock polarity: PRCM_I2SCLKCTL_POSEDGE or
* PRCM_I2SCLKCTL_NEGEDGE
*
* mstdiv - The desired master clock divider.
* worddiv - The desired word clock divider.
* bitdiv - The desired bit clock divider.
*
******************************************************************************/
#ifdef CONFIG_TIVA_I2S
void prcm_audioclock_manual(uint32_t clkconfig, uint32_t mstdiv,
uint32_t bitdiv, uint32_t worddiv);
#endif
/******************************************************************************
* Name: prcm_audioclock_configure
*
* Description:
* Configure the audio clock generation
*
* Use this function to set the sample rate when using internal audio clock
* generation for the I2S module.
*
* NOTE: While other clocks are possible, the stability of the four sample
* rates defined here are only guaranteed if the clock input to the I2S module
* is 48MHz.
*
* Input Parameters:
* clkconfig - The audio clock configuration. The parameter is a bitwise
* OR'ed value consisting of:
*
* 1) Phase: PRCM_I2SCLKCTL_WCLKPHASE_SINGLE or
* PRCM_I2SCLKCTL_WCLKPHASE_DUAL and
* 2) Clock polarity: PRCM_I2SCLKCTL_POSEDGE or
* PRCM_I2SCLKCTL_NEGEDGE
*
* samplerate - The desired audio clock sample rate. The supported sample
* rate configurations are: {I2S_SAMPLE_RATE_16K,
* I2S_SAMPLE_RATE_24K, I2S_SAMPLE_RATE_32K, or
* I2S_SAMPLE_RATE_48K}
*
******************************************************************************/
#ifdef CONFIG_TIVA_I2S
void prcm_audioclock_configure(uint32_t clkconfig,
enum prcm_i2samplerate_e samplerate);
#endif
/******************************************************************************
* Name: prcm_powerdomain_on
*
* Description:
* Turn power on in power domains in the MCU domain
* Use this function to turn on power domains inside the MCU voltage domain.
*
* Power on and power off request has different implications for the
* different power domains.
* - RF Core power domain:
* - Power On : Domain is on or in the process of turning on.
* - Power Off : Domain is powered down when System CPU is in deep sleep.
* The third option for the RF Core is to power down when
* the it is idle. prcm_rfpowerdown_whenidle()
* - SERIAL power domain:
* - Power on : Domain is powered on.
* - Power off : Domain is powered off.
* - PERIPHERIAL power domain:
* - Power on : Domain is powered on.
* - Power off : Domain is powered off.
* - VIMS power domain:
* - Power On : Domain is powered if Bus domain is powered.
* - Power Off : Domain is only powered when CPU domain is on.
* - BUS power domain:
* - Power On : Domain is on.
* - Power Off : Domain is on if requested by RF Core or if CPU domain
* is on.
* - CPU power domain:
* - Power On : Domain is on.
* - Power Off : Domain is powering down if System CPU is idle. This
* will also initiate a power down of the SRAM and BUS
* power domains, unless RF Core is requesting them to
* be on.
*
* NOTE: After a call to this function the status of the power domain
* should be checked using either prcm_powerdoamin_status().
* Any write operation to a power domain which is still not operational can
* result in unexpected behavior.
*
* Input Parameters
* domains - Determines which power domains to turn on. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1,
* I2S, DMA, UART1
* 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
* 5) PRCM_DOMAIN_SYSBUS
* 6) PRCM_DOMAIN_CPU
*
******************************************************************************/
void prcm_powerdomain_on(uint32_t domains);
/******************************************************************************
* Name: prcm_powerdomain_off
*
* Description:
* Turn off a specific power domain
* Use this function to power down domains inside the MCU voltage domain.
*
* NOTE: See prcm_powerdomain_on() for specifics regarding on/off
* configuration.
*
* Input Parameters
* domains - Determines which power domains to turn off. The domains that
* can be turned on/off are:
* 1) PRCM_DOMAIN_RFCORE : RF Core
* 2) PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0
* 3) PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1,
* I2S, DMA, UART1
* 4) PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM
* 5) PRCM_DOMAIN_SYSBUS
* 6) PRCM_DOMAIN_CPU
*
******************************************************************************/
void prcm_powerdomain_off(uint32_t domains);
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
* Enables a peripheral in Run mode
*
* Peripherals are enabled with this function. At power-up, some peripherals
* are disabled; they must be enabled in order to operate or respond to
* register reads/writes.
*
* NOTE: The actual enabling of the peripheral may be delayed until some
* time after this function returns. Care should be taken to ensure that the
* peripheral is not accessed until it is enabled.
*
* When enabling Timers always make sure that the division factor for the
* PERBUSCPUCLK is set. This will guarantee that the timers run at a
* continuous rate even if the SYSBUSCLK is gated.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the
* system controller in the AON domain a call to this function should always
* be followed by a call to prcm_load_set().
*
* Input Paramters:
* peripheral - The peripheral to enable. This is an encoded value. See the
* PRCRM_PERIPH_* definitions for available encodings.
*
******************************************************************************/
void prcm_periph_runenable(uint32_t peripheral);
/******************************************************************************
* Name: prcm_periph_rundisable
*
* Description:
* Disables a peripheral in Run mode
*
* Peripherals are disabled with this function. Once disabled, they will not
* operate or respond to register reads/writes.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* NOTE: The actual disabling of the peripheral may be delayed until some
* time after this function returns. Care should be taken by the user to
* ensure that the peripheral is not accessed in this interval as this might
* cause the system to hang.
*
* Input Paramters:
* peripheral - The peripheral to enable. This is an encoded value. See the
* PRCRM_PERIPH_* definitions for available encodings.
*
******************************************************************************/
void prcm_periph_rundisable(uint32_t peripheral);
/******************************************************************************
* Name: prcm_periph_sleepenable
*
* Description:
* Enables a peripheral in sleep mode
*
* This function allows a peripheral to continue operating when the processor
* goes into sleep mode. Since the clocking configuration of the device does
* not change, any peripheral can safely continue operating while the
* processor is in sleep mode, and can therefore wake the processor from sleep
* mode.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to enable in sleep mode. This is an encoded
* value. See the PRCRM_PERIPH_* definitions for available
* encodings.
*
******************************************************************************/
void prcm_periph_sleepenable(uint32_t peripheral);
/******************************************************************************
* Name: prcm_periph_sleepdisable
*
* Description:
* Disables a peripheral in sleep mode
*
* This function causes a peripheral to stop operating when the processor goes
* into sleep mode. Disabling peripherals while in sleep mode helps to lower
* the current draw of the device. If enabled (via prcm_periph_runenable()),
* the peripheral will automatically resume operation when the processor
* leaves sleep mode, maintaining its entire state from before sleep mode was
* entered.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to disable in sleep mode. This is an encoded
* value. See the PRCRM_PERIPH_* definitions for available
* encodings.
*
******************************************************************************/
void prcm_periph_sleepdisable(uint32_t peripheral);
/******************************************************************************
* Name: prcm_periph_deepsleepenable
*
* Description:
* Enables a peripheral in deep-sleep mode
*
* This function allows a peripheral to continue operating when the processor
* goes into deep-sleep mode. Since the clocking configuration of the device
* may change, not all peripherals can safely continue operating while the
* processor is in sleep mode. This in turn depends on the chosen power mode.
* It is the responsibility of the caller to make sensible choices.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to ensable in deep sleep mode. This is an
* encoded value. See the PRCRM_PERIPH_* definitions for
* available encodings.
*
******************************************************************************/
void prcm_periph_deepsleepenable(uint32_t peripheral);
/******************************************************************************
* Name: prcm_periph_deepsleepdisable
*
* Description:
* Disables a peripheral in deep-sleep mode
*
* This function causes a peripheral to stop operating when the processor goes
* into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps
* to lower the current draw of the device, and can keep peripherals that
* require a particular clock frequency from operating when the clock changes
* as a result of entering deep-sleep mode. If enabled (via
* prcm_periph_runenable()), the peripheral will automatically resume
* operation when the processor leaves deep-sleep mode, maintaining its entire
* state from before deep-sleep mode was entered.
*
* NOTE: A call to this function will only setup the shadow registers in the
* MCU domain for the PRCM module. For the changes to propagate to the system
* controller in the AON domain a call to this function should always be
* followed by a call to prcm_load_set().
*
* Input Parameters:
* peripheral - The peripheral to disable in deep sleep mode. This is an
* encoded value. See the PRCRM_PERIPH_* definitions for
* available encodings.
*
******************************************************************************/
void prcm_periph_deepsleepdisable(uint32_t peripheral);
#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_PRCM_H */

10
arch/arm/src/tiva/cc13xx/cc13xx_start.c
View File

@ -270,15 +270,23 @@ void __start(void)
showprogress('E');
#endif
/* Initialize the Power Manager internal state. It must be called prior
* to any other Power API.
*/
cc13xx_power_initialize();
showprogress('F');
/* Initialize onboard resources */
tiva_boardinitialize();
showprogress('F');
showprogress('G');
#ifdef CONFIG_TIVA_EEPROM
/*Initialize the EEPROM */
tiva_eeprom_initialize();
showprogress('H');
#endif
/* Then start NuttX */

150
arch/arm/src/tiva/hardware/cc13x0/cc13x0_prcm.h
View File

@ -220,119 +220,79 @@
# define PRCM_VIMSCLKG_CLKEN_DISSYSCLK (1 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Disable clock when SYCLK disabled */
# define PRCM_VIMSCLKG_CLKEN_ENA (3 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Enable clock */
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes */
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes,
* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode, and
* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKGR_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKGR_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKGR_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode */
/* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and
* GPIO Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKGS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKGS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKGS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_GPIOCLKG_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
#define PRCM_GPIOCLKG_CLKEN (1 << PRCM_GPIOCLKG_CLKEN_SHIFT)
/* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode */
/* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and
* GPT Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKGDS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKGDS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKGDS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_GPTCLKG_CLKEN_GPT0_SHIFT (0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKG_CLKEN_GPT0 (1 << PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
#define PRCM_GPTCLKG_CLKEN_GPT1_SHIFT (1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKG_CLKEN_GPT1 (1 << PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
#define PRCM_GPTCLKG_CLKEN_GPT2_SHIFT (2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKG_CLKEN_GPT2 (1 << PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
#define PRCM_GPTCLKG_CLKEN_GPT3_SHIFT (3) /* Bit 3: Enable clock for GPT3 */
#define PRCM_GPTCLKG_CLKEN_GPT3 (1 << PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
/* GPIO Clock Gate For Run And All Modes */
/* I2C Clock Gate For Run And All Modes, 2C Clock Gate For Sleep Mode, and
* 2C Clock Gate For Deep Sleep Mode
*/
#define PRCM_GPIOCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_I2CCLKGR_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
#define PRCM_I2CCLKGR_CLKEN (1 << PRCM_I2CCLKGR_CLKEN_SHIFT)
/* GPIO Clock Gate For Sleep Mode */
/* UART Clock Gate For Run And All Modes, UART Clock Gate For Sleep Mode, and
* UART Clock Gate For Deep Sleep Mode
*/
#define PRCM_GPIOCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
/* GPIO Clock Gate For Deep Sleep Mode */
/* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and
* SSI Clock Gate For Deep Sleep Mode.
*/
#define PRCM_GPIOCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
/* GPT Clock Gate For Run And All Modes */
/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and
* I2S Clock Gate For Deep Sleep Mode
*/
#define PRCM_GPTCLKGR_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKGR_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKGR_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKGR_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
/* GPT Clock Gate For Sleep Mode */
#define PRCM_GPTCLKGS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKGS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKGS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKGS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
/* GPT Clock Gate For Deep Sleep Mode */
#define PRCM_GPTCLKGDS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKGDS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKGDS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKGDS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
/* I2C Clock Gate For Run And All Modes */
#define PRCM_I2CCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
/* I2C Clock Gate For Sleep Mode */
#define PRCM_I2CCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
/* I2C Clock Gate For Deep Sleep Mode */
#define PRCM_I2CCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
/* UART Clock Gate For Run And All Modes */
#define PRCM_UARTCLKGR_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
/* UART Clock Gate For Sleep Mode */
#define PRCM_UARTCLKGS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
/* UART Clock Gate For Deep Sleep Mode */
#define PRCM_UARTCLKGDS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
/* SSI Clock Gate For Run And All Modes */
#define PRCM_SSICLKGR_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKGR_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
/* SSI Clock Gate For Sleep Mode */
#define PRCM_SSICLKGS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKGS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
/* SSI Clock Gate For Deep Sleep Mode */
#define PRCM_SSICLKGDS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKGDS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
/* I2S Clock Gate For Run And All Modes */
#define PRCM_I2SCLKGR_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
/* I2S Clock Gate For Sleep Mode */
#define PRCM_I2SCLKGS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
/* I2S Clock Gate For Deep Sleep Mode */
#define PRCM_I2SCLKGDS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */
#define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT)
/* Internal */
#define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
# define PRCM_CPUCLKDIV_DIV1 (0)
# define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV
#define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
# define PRCM_CPUCLKDIV_DIV1 (0)
# define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV
/* I2S Clock Control */
#define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */
# define PRCM_I2SBCLKSEL_EXTERNAL (0)
# define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC
#define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */
# define PRCM_I2SBCLKSEL_EXTERNAL (0)
# define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC
/* GPT Scalar */
@ -344,7 +304,7 @@
# define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV65 (6 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT)

145
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_prcm.h
View File

@ -245,130 +245,109 @@
# define PRCM_VIMSCLKG_CLKEN_DISSYSCLK (1 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Disable clock when SYCLK disabled */
# define PRCM_VIMSCLKG_CLKEN_ENA (3 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Enable clock */
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes */
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes,
* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode, and
* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_PKA_CLKEN_SHIFT (1 << 2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKG_PKA_CLKEN (1 << PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes (only) */
#define PRCM_SECDMACLKGR_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKGR_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKGR_PKA_CLKEN (1 << 2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKGR_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_SECDMACLKGR_CRYPTO_AMCLKEN (1 << 16) /* Bit 16: Force Crypto clock on all modes */
#define PRCM_SECDMACLKGR_TRNG_AMCLKEN (1 << 17) /* Bit 17: Force TRNG clock on all modes */
#define PRCM_SECDMACLKGR_PKA_AMCLKEN (1 << 18) /* Bit 18: Force PKA clock on all modes */
#define PRCM_SECDMACLKGR_PKA_ZER0RESETN (1 << 19) /* Bit 18: Enable PKA zeroize of memory */
#define PRCM_SECDMACLKGR_DMA_AMCLKEN (1 << 24) /* Bit 24: Force DMA clock on all modes */
/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode */
/* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and
* GPIO Clock Gate For Deep Sleep Mode
*/
#define PRCM_SECDMACLKGS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKGS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKGS_PKA_CLKEN (1 << 2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKGS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
#define PRCM_GPIOCLKG_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
#define PRCM_GPIOCLKG_CLKEN (1 << PRCM_GPIOCLKG_CLKEN_SHIFT)
/* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode */
/* GPIO Clock Gate For Run And All Modes (only) */
#define PRCM_SECDMACLKGDS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
#define PRCM_SECDMACLKGDS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
#define PRCM_SECDMACLKGDS_PKA_CLKEN (1 << 2) /* Bit 2: Enable PKA clock */
#define PRCM_SECDMACLKGDS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
/* GPIO Clock Gate For Run And All Modes */
#define PRCM_GPIOCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_GPIOCLKGR_AMCLKEN (1 << 8) /* Bit 8 Force clock for all modes */
/* GPIO Clock Gate For Sleep Mode */
/* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and
* GPT Clock Gate For Deep Sleep Mode.
*/
#define PRCM_GPIOCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_GPTCLKG_CLKEN_GPT0_SHIFT (0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKG_CLKEN_GPT0 (1 << PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
#define PRCM_GPTCLKG_CLKEN_GPT1_SHIFT (1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKG_CLKEN_GPT1 (1 << PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
#define PRCM_GPTCLKG_CLKEN_GPT2_SHIFT (2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKG_CLKEN_GPT2 (1 << PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
#define PRCM_GPTCLKG_CLKEN_GPT3_SHIFT (3) /* Bit 3: Enable clock for GPT3 */
#define PRCM_GPTCLKG_CLKEN_GPT3 (1 << PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
/* GPIO Clock Gate For Deep Sleep Mode */
/* GPT Clock Gate For Run And All Modes (only) */
#define PRCM_GPIOCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
/* GPT Clock Gate For Run And All Modes */
#define PRCM_GPTCLKGR_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKGR_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKGR_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKGR_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT0 (1 << 8) /* Bit 8: Enable clock for GPT0 in all modes */
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT1 (1 << 9) /* Bit 9: Enable clock for GPT1 in all modes */
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT2 (1 << 10) /* Bit 11: Enable clock for GPT2 in all modes */
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT3 (1 << 11) /* Bit 11: Enable clock for GPT3 in all modes */
/* GPT Clock Gate For Sleep Mode */
/* I2C Clock Gate For Run And All Modes, 2C Clock Gate For Sleep Mode, and
* 2C Clock Gate For Deep Sleep Mode
*/
#define PRCM_GPTCLKGS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKGS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKGS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKGS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
#define PRCM_I2CCLKGR_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
#define PRCM_I2CCLKGR_CLKEN (1 << PRCM_I2CCLKGR_CLKEN_SHIFT)
/* GPT Clock Gate For Deep Sleep Mode */
/* I2C Clock Gate For Run And All Modes (only) */
#define PRCM_GPTCLKGDS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
#define PRCM_GPTCLKGDS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
#define PRCM_GPTCLKGDS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
#define PRCM_GPTCLKGDS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
/* I2C Clock Gate For Run And All Modes */
#define PRCM_I2CCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_I2CCLKGR_AMCLKEN (1 << 8) /* Bit 8: Force clock on for all modes */
/* I2C Clock Gate For Sleep Mode */
/* UART Clock Gate For Run And All Modes, UART Clock Gate For Sleep Mode, and
* UART Clock Gate For Deep Sleep Mode
*/
#define PRCM_I2CCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
#define PRCM_UARTCLKG_CLKEN_UART1_SHIFT (1 << 1) /* Bit 1: UART1 Enable clock */
#define PRCM_UARTCLKG_CLKEN_UART1 (1 << PRCM_UARTCLKGDS_CLKEN_UART1_SHIFT)
/* I2C Clock Gate For Deep Sleep Mode */
/* UART Clock Gate For Run And All Modes (only) */
#define PRCM_I2CCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
/* UART Clock Gate For Run And All Modes */
#define PRCM_UARTCLKGR_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKGR_CLKEN_UART1 (1 << 1) /* Bit 1: UART1 Enable clock */
#define PRCM_UARTCLKGR_AMCLKEN_UART0 (1 << 8) /* Bit 8: UART0 Force clock on for all modes */
#define PRCM_UARTCLKGR_AMCLKEN_UART1 (1 << 9) /* Bit 9: UART1 Force clock on for all modes */
/* UART Clock Gate For Sleep Mode */
/* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and
* SSI Clock Gate For Deep Sleep Mode
*/
#define PRCM_UARTCLKGS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKGS_CLKEN_UART1 (1 << 1) /* Bit 1: UART1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
/* UART Clock Gate For Deep Sleep Mode */
/* SSI Clock Gate For Run And All Modes (only) */
#define PRCM_UARTCLKGDS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
#define PRCM_UARTCLKGDS_CLKEN_UART1 (1 << 1) /* Bit 1: UART1 Enable clock */
/* SSI Clock Gate For Run And All Modes */
#define PRCM_SSICLKGR_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKGR_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
#define PRCM_SSICLKGR_AMCLKEN_SSI0 (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */
#define PRCM_SSICLKGR_AMCLKEN_SSI1 (1 << 9) /* Bit 9: SSI1 Force clock on for all modes */
/* SSI Clock Gate For Sleep Mode */
/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and
* I2S Clock Gate For Deep Sleep Mode
*/
#define PRCM_SSICLKGS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKGS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
#define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */
#define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT)
/* SSI Clock Gate For Deep Sleep Mode */
/* I2S Clock Gate For Run And All Modes (only) */
#define PRCM_SSICLKGDS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_SSICLKGDS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
/* I2S Clock Gate For Run And All Modes */
#define PRCM_I2SCLKGR_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
#define PRCM_I2SCLKGR_AMCLKEN (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */
/* I2S Clock Gate For Sleep Mode */
#define PRCM_I2SCLKGS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
/* I2S Clock Gate For Deep Sleep Mode */
#define PRCM_I2SCLKGDS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
/* Internal */
#define PRCM_SYSBUSCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
@ -425,7 +404,7 @@
# define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV65 (6 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT)
# define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT)

7
configs/launchxl-cc1312r1/include/board.h
View File

@ -108,9 +108,10 @@
* UART0 (PA0/U0RX and PA1/U0TX).
*/
#define GPIO_UART0_RX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_IOCFG_IE | \
GPIO_DIO(0))
#define GPIO_UART0_TX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_TX) | GPIO_DIO(1))
#define GPIO_UART0_RX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_RX) | \
GPIO_STD_INPUT | GPIO_DIO(0))
#define GPIO_UART0_TX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_TX) | \
GPIO_STD_OUTPUT | GPIO_DIO(1))
/* DMA **********************************************************************/

3
configs/launchxl-cc1312r1/src/cc1312_boot.c
View File

@ -81,6 +81,9 @@ void tiva_boardinitialize(void)
board_autoled_initialize();
#endif
/* TODO: Initialize antenna switch */
/* TODO: Shutdown external FLASH */
}
/****************************************************************************