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arch/risc-v: introduce dynamic stack allocation.

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It is misleading to allocate stack from static array and heap,
make all stack allocated from heap area.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
This commit is contained in:
Inochi Amaoto 2024-04-14 18:40:44 +08:00 committed by Alan Carvalho de Assis
parent 1ef3767f85
commit a33313413d
46 changed files with 181 additions and 219 deletions
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4
arch/risc-v/src/bl602/bl602_head.S
View File

@ -25,6 +25,8 @@
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "riscv_internal.h"
.section .init
.globl bl602_start
.globl __start
@ -47,7 +49,7 @@ bl602_start:
la sp, g_idle_stack
add s11, sp, zero
li t0, CONFIG_IDLETHREAD_STACKSIZE
li t0, SMP_STACK_SIZE
add sp, sp, t0
andi sp, sp, ~0xF

10
arch/risc-v/src/bl602/bl602_start.c
View File

@ -52,8 +52,6 @@
#define showprogress(c)
#endif
#define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Private Data
****************************************************************************/
@ -68,7 +66,7 @@
* address.
*/
uint8_t g_idle_stack[BL602_IDLESTACK_SIZE]
uint8_t g_idle_stack[SMP_STACK_SIZE]
locate_data(".noinit_idle_stack");
/* Dont change the name of variable, since we refer this
@ -167,7 +165,11 @@ void bfl_main(void)
/* Configure IDLE stack */
g_idle_topstack = ((uint32_t)g_idle_stack + BL602_IDLESTACK_SIZE);
g_idle_topstack = ((uint32_t)g_idle_stack + SMP_STACK_SIZE);
/* Setup base stack */
riscv_set_basestack((uintptr_t)g_idle_stack, SMP_STACK_SIZE);
/* Configure the UART so we can get debug output */

34
arch/risc-v/src/bl808/bl808_head.S
View File

@ -29,6 +29,7 @@
#include "chip.h"
#include "riscv_internal.h"
#include "riscv_macros.S"
/****************************************************************************
* Public Symbols
@ -68,13 +69,6 @@ __start:
real_start:
/* Set stack pointer to the idle thread stack */
bnez a0, 1f
la sp, BL808_IDLESTACK_TOP
j 2f
1:
/* Load the number of CPUs that the kernel supports */
#ifdef CONFIG_SMP
@ -90,30 +84,8 @@ real_start:
wfi
3:
/* Get start address of idle stack array */
la t0, g_cpux_idlestack
/* Get idle stack offset */
li t1, SMP_STACK_SIZE
mul t1, t1, a0
/* Load idle stack top to sp */
add sp, t0, t1
/*
* sp (stack top) = sp (stack top) - XCPTCONTEXT_SIZE
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/
li t0, -STACK_ALIGN_UP(XCPTCONTEXT_SIZE)
add sp, sp, t0
2:
/* Set stack pointer to the idle thread stack */
riscv_set_inital_sp BL808_IDLESTACK_BASE, SMP_STACK_SIZE, a0
/* Disable all interrupts (i.e. timer, external) in sie */

3
arch/risc-v/src/bl808/bl808_memorymap.h
View File

@ -39,7 +39,4 @@
#define BL808_IDLESTACK_BASE _ebss
#endif
#define BL808_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
#define BL808_IDLESTACK_TOP (BL808_IDLESTACK_BASE + BL808_IDLESTACK_SIZE)
#endif /* __ARCH_RISCV_SRC_BL808_BL808_MEMORYMAP_H */

19
arch/risc-v/src/bl808/bl808_start.c
View File

@ -59,10 +59,11 @@ extern void __trap_vec(void);
****************************************************************************/
/* NOTE: g_idle_topstack needs to point the top of the idle stack
* for CPU0 and this value is used in up_initial_state()
* for last CPU and this value is used in up_initial_state()
*/
uintptr_t g_idle_topstack = BL808_IDLESTACK_TOP;
uintptr_t g_idle_topstack = BL808_IDLESTACK_BASE +
SMP_STACK_SIZE * CONFIG_SMP_NCPUS;
/****************************************************************************
* Private Functions
@ -113,7 +114,7 @@ static void bl808_copy_overlap(uint8_t *dest, const uint8_t *src,
static void bl808_copy_ramdisk(void)
{
const char *header = "-rom1fs-";
const uint8_t *limit = (uint8_t *)BL808_IDLESTACK_TOP + (256 * 1024);
const uint8_t *limit = (uint8_t *)g_idle_topstack + (256 * 1024);
uint8_t *ramdisk_addr = NULL;
uint8_t *addr;
uint32_t size;
@ -122,9 +123,9 @@ static void bl808_copy_ramdisk(void)
* Limit search to 256 KB after Idle Stack Top.
*/
binfo("_edata=%p, _sbss=%p, _ebss=%p, BL808_IDLESTACK_TOP=%p\n",
binfo("_edata=%p, _sbss=%p, _ebss=%p, idlestack_top=%p\n",
(void *)_edata, (void *)_sbss, (void *)_ebss,
(void *)BL808_IDLESTACK_TOP);
(void *)g_idle_topstack);
for (addr = _edata; addr < limit; addr++)
{
if (memcmp(addr, header, strlen(header)) == 0)
@ -145,9 +146,9 @@ static void bl808_copy_ramdisk(void)
/* RAM Disk must be after Idle Stack, to prevent overwriting */
if (ramdisk_addr <= (uint8_t *)BL808_IDLESTACK_TOP)
if (ramdisk_addr <= (uint8_t *)g_idle_topstack)
{
const size_t pad = (size_t)BL808_IDLESTACK_TOP - (size_t)ramdisk_addr;
const size_t pad = (size_t)g_idle_topstack - (size_t)ramdisk_addr;
_err("RAM Disk must be after Idle Stack. Increase initrd padding "
"by %ul bytes.", pad);
PANIC();
@ -273,6 +274,10 @@ void bl808_start(int mhartid)
bl808_clear_bss();
/* Setup base stack */
riscv_set_basestack(BL808_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Copy the RAM Disk */
bl808_copy_ramdisk();

2
arch/risc-v/src/c906/c906_memorymap.h
View File

@ -44,7 +44,7 @@
#define C906_IDLESTACK_BASE _ebss
#endif
#define C906_IDLESTACK0_TOP (C906_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define C906_IDLESTACK0_TOP (C906_IDLESTACK_BASE + SMP_STACK_SIZE)
#define C906_IDLESTACK_TOP (C906_IDLESTACK0_TOP)
#endif /* __ARCH_RISCV_SRC_C906_C906_MEMORYMAP_H */

4
arch/risc-v/src/c906/c906_start.c
View File

@ -91,6 +91,10 @@ void __c906_start(uint32_t mhartid)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(C906_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

4
arch/risc-v/src/common/espressif/esp_memorymap.h
View File

@ -27,6 +27,8 @@
#include <nuttx/config.h>
#include "riscv_common_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -39,6 +41,6 @@
#define ESP_IDLESTACK_BASE g_idlestack
#endif
#define ESP_IDLESTACK_TOP (ESP_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define ESP_IDLESTACK_TOP (ESP_IDLESTACK_BASE + SMP_STACK_SIZE)
#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_MEMORYMAP_H */

6
arch/risc-v/src/common/espressif/esp_start.c
View File

@ -176,7 +176,7 @@ HDR_ATTR static void (*_entry_point)(void) = __start;
/* Address of the IDLE thread */
uint8_t g_idlestack[CONFIG_IDLETHREAD_STACKSIZE]
uint8_t g_idlestack[SMP_STACK_SIZE]
aligned_data(16) locate_data(".noinit");
uintptr_t g_idle_topstack = ESP_IDLESTACK_TOP;
@ -459,6 +459,10 @@ void __esp_start(void)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(ESP_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Setup the syscall table needed by the ROM code */
esp_setup_syscall_table();

3
arch/risc-v/src/common/riscv_common_memorymap.h
View File

@ -67,8 +67,7 @@ EXTERN uintptr_t g_idle_topstack;
/* Address of per-cpu idle stack base */
EXTERN uint8_t aligned_data(16)
g_cpux_idlestack[CONFIG_SMP_NCPUS - 1][SMP_STACK_SIZE];
EXTERN const uint8_t *g_cpux_idlestack[CONFIG_SMP_NCPUS];
/* Address of the saved user stack pointer */

12
arch/risc-v/src/common/riscv_cpuidlestack.c
View File

@ -43,18 +43,12 @@
* Private Data
****************************************************************************/
/* Note:
* 1. QEMU-RV supports up to 8 cores currently.
* 2. RISC-V requires a 16-byte stack alignment.
*/
uint8_t aligned_data(16)
g_cpux_idlestack[CONFIG_SMP_NCPUS - 1][SMP_STACK_SIZE];
/****************************************************************************
* Public Data
****************************************************************************/
const uint8_t *g_cpux_idlestack[CONFIG_SMP_NCPUS];
/****************************************************************************
* Public Functions
****************************************************************************/
@ -112,7 +106,7 @@ int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size)
/* Get the top of the stack */
stack_alloc = (uintptr_t)g_cpux_idlestack[cpu - 1];
stack_alloc = (uintptr_t)g_cpux_idlestack[cpu];
DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc));
tcb->adj_stack_size = SMP_STACK_SIZE;

5
arch/risc-v/src/common/riscv_initialstate.c
View File

@ -97,10 +97,9 @@ void up_initial_state(struct tcb_s *tcb)
if (tcb->pid == IDLE_PROCESS_ID)
{
tcb->stack_alloc_ptr = (void *)(g_idle_topstack -
CONFIG_IDLETHREAD_STACKSIZE);
tcb->stack_alloc_ptr = (void *)g_cpux_idlestack[riscv_mhartid()];
tcb->stack_base_ptr = tcb->stack_alloc_ptr;
tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE;
tcb->adj_stack_size = SMP_STACK_SIZE;
#ifdef CONFIG_STACK_COLORATION
/* If stack debug is enabled, then fill the stack with a

12
arch/risc-v/src/common/riscv_internal.h
View File

@ -294,6 +294,18 @@ int riscv_check_pmp_access(uintptr_t attr, uintptr_t base, uintptr_t size);
int riscv_configured_pmp_regions(void);
int riscv_next_free_pmp_region(void);
/* RISC-V Memorymap Config **************************************************/
static inline void riscv_set_basestack(uintptr_t base, uintptr_t size)
{
unsigned int i;
for (i = 0; i < CONFIG_SMP_NCPUS; i++)
{
g_cpux_idlestack[i] = (const uint8_t *)(base + size * i);
}
}
/* RISC-V SBI wrappers ******************************************************/
#ifdef CONFIG_ARCH_USE_S_MODE

42
arch/risc-v/src/common/riscv_macros.S
View File

@ -364,3 +364,45 @@
csrr \out, CSR_MHARTID
#endif
.endm
/****************************************************************************
* Name: riscv_set_inital_sp
*
* Description:
* Set inital sp for riscv core. This function should be only called
* when initing.
*
* sp (stack top) = sp base + idle stack size * hart id
* sp (stack base) = sp (stack top) + idle stack size * - XCPTCONTEXT_SIZE
*
* Note: The XCPTCONTEXT_SIZE byte after stack base is reserved for
* up_initial_state since we are already running and using
* the per CPU idle stack.
*
* TODO: Support non-zero boot hart.
*
* Parameter:
* base - Pointer to where the stack is allocated (e.g. _ebss)
* size - Stack size for pre cpu to allocate
* size - Hart id register of this hart (Usually a0)
*
****************************************************************************/
.macro riscv_set_inital_sp base, size, hartid
la t0, \base
li t1, \size
mul t1, \hartid, t1
add t0, t0, t1
/* ensure the last XCPTCONTEXT_SIZE is reserved for non boot CPU */
bnez \hartid, 998f
li t1, STACK_ALIGN_DOWN(\size)
j 999f
998:
li t1, STACK_ALIGN_DOWN(\size - XCPTCONTEXT_SIZE)
999:
add t0, t0, t1
mv sp, t0
.endm

4
arch/risc-v/src/esp32c3-legacy/esp32c3_memorymap.h
View File

@ -25,6 +25,8 @@
* Included Files
****************************************************************************/
#include "riscv_common_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -37,6 +39,6 @@
#define ESP32C3_IDLESTACK_BASE g_idlestack
#endif
#define ESP32C3_IDLESTACK_TOP (ESP32C3_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define ESP32C3_IDLESTACK_TOP (ESP32C3_IDLESTACK_BASE + SMP_STACK_SIZE)
#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_MEMORYMAP_H */

6
arch/risc-v/src/esp32c3-legacy/esp32c3_start.c
View File

@ -129,7 +129,7 @@ HDR_ATTR static void (*_entry_point)(void) = __start;
/* Address of the IDLE thread */
uint8_t g_idlestack[CONFIG_IDLETHREAD_STACKSIZE]
uint8_t g_idlestack[SMP_STACK_SIZE]
aligned_data(16) locate_data(".noinit");
uintptr_t g_idle_topstack = ESP32C3_IDLESTACK_TOP;
@ -294,6 +294,10 @@ void __esp32c3_start(void)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(ESP32C3_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Setup the syscall table needed by the ROM code */
setup_syscall_table();

2
arch/risc-v/src/fe310/fe310_memorymap.h
View File

@ -45,6 +45,6 @@
#define FE310_IDLESTACK_BASE _ebss
#endif
#define FE310_IDLESTACK_TOP (FE310_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define FE310_IDLESTACK_TOP (FE310_IDLESTACK_BASE + SMP_STACK_SIZE)
#endif /* __ARCH_RISCV_SRC_FE310_FE310_MEMORYMAP_H */

4
arch/risc-v/src/fe310/fe310_start.c
View File

@ -81,6 +81,10 @@ void __fe310_start(void)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(FE310_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

2
arch/risc-v/src/hpm6000/hpm_memorymap.h
View File

@ -45,6 +45,6 @@
#define HPM_IDLESTACK_BASE _ebss
#endif
#define HPM_IDLESTACK_TOP (HPM_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define HPM_IDLESTACK_TOP (HPM_IDLESTACK_BASE + SMP_STACK_SIZE)
#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H */

4
arch/risc-v/src/hpm6000/hpm_start.c
View File

@ -76,6 +76,10 @@ void __hpm_start(void)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(HPM_IDLESTACK_BASE, CONFIG_IDLETHREAD_STACKSIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

2
arch/risc-v/src/hpm6750/hpm6750_memorymap.h
View File

@ -45,6 +45,6 @@
#define HPM6750_IDLESTACK_BASE _ebss
#endif
#define HPM6750_IDLESTACK_TOP (HPM6750_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define HPM6750_IDLESTACK_TOP (HPM6750_IDLESTACK_BASE + SMP_STACK_SIZE)
#endif /* __ARCH_RISCV_SRC_HPM6750_HPM6750_MEMORYMAP_H */

4
arch/risc-v/src/hpm6750/hpm6750_start.c
View File

@ -76,6 +76,10 @@ void __hpm6750_start(void)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(HPM6750_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

34
arch/risc-v/src/jh7110/jh7110_head.S
View File

@ -29,6 +29,7 @@
#include "chip.h"
#include "riscv_internal.h"
#include "riscv_macros.S"
/****************************************************************************
* Public Symbols
@ -74,13 +75,6 @@ real_start:
addi a0, a0, -1
/* Set stack pointer to the idle thread stack */
bnez a0, 1f
la sp, JH7110_IDLESTACK_TOP
j 2f
1:
/* Load the number of CPUs that the kernel supports */
#ifdef CONFIG_SMP
@ -96,30 +90,8 @@ real_start:
wfi
3:
/* Get start address of idle stack array */
la t0, g_cpux_idlestack
/* Get idle stack offset */
li t1, SMP_STACK_SIZE
mul t1, t1, a0
/* Load idle stack top to sp */
add sp, t0, t1
/*
* sp (stack top) = sp (stack top) - XCPTCONTEXT_SIZE
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/
li t0, -STACK_ALIGN_UP(XCPTCONTEXT_SIZE)
add sp, sp, t0
2:
/* Set stack pointer to the idle thread stack */
riscv_set_inital_sp JH7110_IDLESTACK_BASE, SMP_STACK_SIZE, a0
/* Disable all interrupts (i.e. timer, external) in sie */

3
arch/risc-v/src/jh7110/jh7110_memorymap.h
View File

@ -39,7 +39,4 @@
#define JH7110_IDLESTACK_BASE _ebss
#endif
#define JH7110_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
#define JH7110_IDLESTACK_TOP (JH7110_IDLESTACK_BASE + JH7110_IDLESTACK_SIZE)
#endif /* __ARCH_RISCV_SRC_JH7110_JH7110_MEMORYMAP_H */

9
arch/risc-v/src/jh7110/jh7110_start.c
View File

@ -53,10 +53,11 @@ extern void __trap_vec(void);
****************************************************************************/
/* NOTE: g_idle_topstack needs to point the top of the idle stack
* for CPU0 and this value is used in up_initial_state()
* for last CPU and this value is used in up_initial_state()
*/
uintptr_t g_idle_topstack = JH7110_IDLESTACK_TOP;
uintptr_t g_idle_topstack = JH7110_IDLESTACK_BASE +
SMP_STACK_SIZE * CONFIG_SMP_NCPUS;
/****************************************************************************
* Public Functions
@ -139,6 +140,10 @@ void jh7110_start(int mhartid)
{
jh7110_clear_bss();
/* Setup base stack */
riscv_set_basestack(JH7110_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Initialize the per CPU areas */
riscv_percpu_add_hart(mhartid);

34
arch/risc-v/src/k210/k210_head.S
View File

@ -28,6 +28,7 @@
#include "chip.h"
#include "k210_memorymap.h"
#include "riscv_internal.h"
#include "riscv_macros.S"
/****************************************************************************
* Public Symbols
@ -46,44 +47,17 @@ __start:
csrr a0, CSR_MHARTID
/* Set stack pointer to the idle thread stack */
bnez a0, 1f
la sp, K210_IDLESTACK0_TOP
j 2f
1:
/* In case of single CPU config, stop here */
#if !defined(CONFIG_SMP) || (CONFIG_SMP_NCPUS == 1)
beqz a0, 2f
csrw CSR_MIE, zero
wfi
#endif
/* Get start address of idle stack array */
la t0, g_cpux_idlestack
/* Get idle stack offset */
li t1, SMP_STACK_SIZE
mul t1, t1, a0
/* Load idle stack top to sp */
add sp, t0, t1
/*
* sp (stack top) = sp (stack top) - XCPTCONTEXT_SIZE
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/
li t0, -STACK_ALIGN_UP(XCPTCONTEXT_SIZE)
add sp, sp, t0
2:
/* Set stack pointer to the idle thread stack */
riscv_set_inital_sp K210_IDLESTACK_BASE, SMP_STACK_SIZE, a0
/* Disable all interrupts (i.e. timer, external) in mie */

1
arch/risc-v/src/k210/k210_memorymap.h
View File

@ -45,6 +45,5 @@
#endif
#define K210_IDLESTACK0_BASE (K210_IDLESTACK_BASE)
#define K210_IDLESTACK0_TOP (K210_IDLESTACK0_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#endif /* __ARCH_RISCV_SRC_K210_K210_MEMORYMAP_H */

7
arch/risc-v/src/k210/k210_start.c
View File

@ -52,7 +52,8 @@
* for CPU0 and this value is used in up_initial_state()
*/
uintptr_t g_idle_topstack = K210_IDLESTACK0_TOP;
uintptr_t g_idle_topstack = K210_IDLESTACK_BASE +
SMP_STACK_SIZE * CONFIG_SMP_NCPUS;
/****************************************************************************
* Public Functions
@ -85,6 +86,10 @@ void __k210_start(uint32_t mhartid)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(K210_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

34
arch/risc-v/src/k230/k230_head.S
View File

@ -30,6 +30,7 @@
#include "chip.h"
#include "riscv_internal.h"
#include "riscv_macros.S"
/****************************************************************************
* Public Symbols
@ -64,13 +65,6 @@ __start:
csrr a0, CSR_MHARTID
#endif
/* Set stack pointer to the idle thread stack */
bnez a0, 1f
la sp, K230_IDLESTACK_TOP
j 2f
1:
/* Load the number of CPUs that the kernel supports */
#ifdef CONFIG_SMP
@ -86,30 +80,8 @@ __start:
wfi
3:
/* Get start address of idle stack array */
la t0, g_cpux_idlestack
/* Get idle stack offset */
li t1, SMP_STACK_SIZE
mul t1, t1, a0
/* Load idle stack top to sp */
add sp, t0, t1
/*
* sp (stack top) = sp (stack top) - XCPTCONTEXT_SIZE
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/
li t0, -STACK_ALIGN_UP(XCPTCONTEXT_SIZE)
add sp, sp, t0
2:
/* Set stack pointer to the idle thread stack */
riscv_set_inital_sp K230_IDLESTACK_BASE, SMP_STACK_SIZE, a0
/* Disable all interrupts (i.e. timer, external) */

3
arch/risc-v/src/k230/k230_memorymap.h
View File

@ -39,7 +39,4 @@
#define K230_IDLESTACK_BASE _ebss
#endif
#define K230_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
#define K230_IDLESTACK_TOP (K230_IDLESTACK_BASE + K230_IDLESTACK_SIZE)
#endif /* __ARCH_RISCV_SRC_K230_K230_MEMORYMAP_H */

7
arch/risc-v/src/k230/k230_start.c
View File

@ -102,10 +102,11 @@ static void k230_copy_init_data(void)
****************************************************************************/
/* NOTE: g_idle_topstack needs to point the top of the idle stack
* for CPU0 and this value is used in up_initial_state()
* for last CPU and this value is used in up_initial_state()
*/
uintptr_t g_idle_topstack = K230_IDLESTACK_TOP;
uintptr_t g_idle_topstack = K230_IDLESTACK_BASE +
SMP_STACK_SIZE * CONFIG_SMP_NCPUS;
/****************************************************************************
* Public Functions
@ -121,6 +122,8 @@ void k230_start(int mhartid, const char *dtb)
{
k230_clear_bss();
riscv_set_basestack(K230_IDLESTACK_BASE, SMP_STACK_SIZE);
#ifdef CONFIG_RISCV_PERCPU_SCRATCH
riscv_percpu_add_hart(mhartid);
#else

3
arch/risc-v/src/litex/litex_memorymap.h
View File

@ -25,6 +25,7 @@
* Included Files
****************************************************************************/
#include "riscv_common_memorymap.h"
#include "hardware/litex_memorymap.h"
#include "hardware/litex_uart.h"
#include "hardware/litex_clint.h"
@ -42,6 +43,6 @@
#define LITEX_IDLESTACK_BASE _ebss
#endif
#define LITEX_IDLESTACK_TOP (LITEX_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE)
#define LITEX_IDLESTACK_TOP (LITEX_IDLESTACK_BASE + SMP_STACK_SIZE)
#endif /* __ARCH_RISCV_SRC_LITEX_LITEX_MEMORYMAP_H */

4
arch/risc-v/src/litex/litex_start.c
View File

@ -93,6 +93,10 @@ void __litex_start(int hart_index, const void * fdt, int arg)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(LITEX_IDLESTACK_BASE, SMP_STACK_SIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

2
arch/risc-v/src/mpfs/mpfs_memorymap.h
View File

@ -44,7 +44,7 @@
#define MPFS_IDLESTACK_BASE _ebss
#endif
#define MPFS_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~15)
#define MPFS_IDLESTACK_SIZE SMP_STACK_SIZE
#define MPFS_IDLESTACK0_TOP (MPFS_IDLESTACK_BASE + MPFS_IDLESTACK_SIZE)

4
arch/risc-v/src/mpfs/mpfs_start.c
View File

@ -98,6 +98,10 @@ void __mpfs_start(uint64_t mhartid)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(MPFS_IDLESTACK_BASE, MPFS_IDLESTACK_SIZE);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

41
arch/risc-v/src/qemu-rv/qemu_rv_head.S
View File

@ -29,6 +29,7 @@
#include "chip.h"
#include "riscv_internal.h"
#include "riscv_macros.S"
/****************************************************************************
* Public Symbols
@ -46,52 +47,18 @@ __start:
csrr a0, CSR_MHARTID
/* Set stack pointer to the idle thread stack */
bnez a0, 1f
la sp, QEMU_RV_IDLESTACK_TOP
j 2f
1:
/* Load the number of CPUs that the kernel supports */
#ifdef CONFIG_SMP
li t1, CONFIG_SMP_NCPUS
#else
li t1, 1
#endif
/* If a0 (mhartid) >= t1 (the number of CPUs), stop here */
blt a0, t1, 3f
blt a0, t1, 2f
csrw CSR_MIE, zero
wfi
3:
/* Get start address of idle stack array */
la t0, g_cpux_idlestack
/* Get idle stack offset */
li t1, SMP_STACK_SIZE
mul t1, t1, a0
/* Load idle stack top to sp */
add sp, t0, t1
/*
* sp (stack top) = sp (stack top) - XCPTCONTEXT_SIZE
*
* Note: Reserve some space used by up_initial_state since we are already
* running and using the per CPU idle stack.
*/
li t0, -STACK_ALIGN_UP(XCPTCONTEXT_SIZE)
add sp, sp, t0
2:
/* Set stack pointer to the idle thread stack */
riscv_set_inital_sp QEMU_RV_IDLESTACK_BASE, SMP_STACK_SIZE, a0
/* Disable all interrupts (i.e. timer, external) in mie */

3
arch/risc-v/src/qemu-rv/qemu_rv_memorymap.h
View File

@ -39,7 +39,4 @@
#define QEMU_RV_IDLESTACK_BASE _ebss
#endif
#define QEMU_RV_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
#define QEMU_RV_IDLESTACK_TOP (QEMU_RV_IDLESTACK_BASE + QEMU_RV_IDLESTACK_SIZE)
#endif /* __ARCH_RISCV_SRC_QEMU_RV_QEMU_RV_MEMORYMAP_H */

7
arch/risc-v/src/qemu-rv/qemu_rv_start.c
View File

@ -87,10 +87,11 @@ void qemu_rv_clear_bss(void)
****************************************************************************/
/* NOTE: g_idle_topstack needs to point the top of the idle stack
* for CPU0 and this value is used in up_initial_state()
* for last CPU and this value is used in up_initial_state()
*/
uintptr_t g_idle_topstack = QEMU_RV_IDLESTACK_TOP;
uintptr_t g_idle_topstack = QEMU_RV_IDLESTACK_BASE +
SMP_STACK_SIZE * CONFIG_SMP_NCPUS;
/****************************************************************************
* Public Functions
@ -118,6 +119,8 @@ void qemu_rv_start(int mhartid, const char *dtb)
#ifndef CONFIG_BUILD_KERNEL
qemu_rv_clear_bss();
riscv_set_basestack(QEMU_RV_IDLESTACK_BASE, SMP_STACK_SIZE);
#ifdef CONFIG_RISCV_PERCPU_SCRATCH
riscv_percpu_add_hart(mhartid);
#endif

4
arch/risc-v/src/rv32m1/rv32m1_memorymap.h
View File

@ -25,6 +25,8 @@
* Included Files
****************************************************************************/
#include "riscv_internal.h"
#include "hardware/rv32m1_memorymap.h"
/****************************************************************************
@ -39,7 +41,7 @@
#define RV32M1_IDLESTACK_BASE _ebss
#endif
#define RV32M1_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
#define RV32M1_IDLESTACK_SIZE SMP_STACK_SIZE
#define RV32M1_IDLESTACK_TOP (RV32M1_IDLESTACK_BASE + RV32M1_IDLESTACK_SIZE)
#endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_MEMORYMAP_H */

4
arch/risc-v/src/rv32m1/rv32m1_start.c
View File

@ -113,6 +113,10 @@ void __rv32m1_start(void)
*dest++ = 0;
}
/* Setup base stack */
riscv_set_basestack(RV32M1_IDLESTACK_BASE, RV32M1_IDLESTACK_TOP);
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the

1
boards/risc-v/bl808/ox64/scripts/ld.script
View File

@ -116,6 +116,7 @@ SECTIONS
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(32);
_ebss = . ;
} > ksram

1
boards/risc-v/jh7110/star64/scripts/ld.script
View File

@ -116,6 +116,7 @@ SECTIONS
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(32);
_ebss = . ;
} > ksram

2
boards/risc-v/k210/maix-bit/scripts/ld.script
View File

@ -81,7 +81,7 @@ SECTIONS
*(.gnu.linkonce.b.*)
*(.gnu.linkonce.sb.*)
*(COMMON)
. = ALIGN(8);
. = ALIGN(32);
_ebss = ABSOLUTE(.);
} > sram

2
boards/risc-v/k210/maix-bit/scripts/user-space.ld
View File

@ -75,7 +75,7 @@ SECTIONS
*(.sbss .sbss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(8);
. = ALIGN(32);
_ebss = ABSOLUTE(.);
} > usram

1
boards/risc-v/k230/canmv230/scripts/ld-flat.script
View File

@ -114,6 +114,7 @@ SECTIONS
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(32);
_ebss = . ;
}

1
boards/risc-v/qemu-rv/rv-virt/scripts/ld.script
View File

@ -108,6 +108,7 @@ SECTIONS
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
. = ALIGN(32);
_ebss = . ;
}