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Fixed some interrupt-related bugs

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@45 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2007-03-08 22:34:02 +00:00
parent 9a3efb5f8d
commit a3455d2a77
7 changed files with 33 additions and 42 deletions
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8
arch/c5471/src/up_assert.c
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@ -155,10 +155,10 @@ void up_assert(const ubyte *filename, int lineno)
up_ledon(LED_ASSERTION); up_ledon(LED_ASSERTION);
#if CONFIG_TASK_NAME_SIZE > 0 #if CONFIG_TASK_NAME_SIZE > 0
dbg("Assertion failed at file:%s line: %d task: %s\n", lldbg("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name); filename, lineno, rtcb->name);
#else #else
dbg("Assertion failed at file:%s line: %d\n", lldbg("Assertion failed at file:%s line: %d\n",
filename, lineno); filename, lineno);
#endif #endif
up_stackdump(); up_stackdump();
@ -177,10 +177,10 @@ void up_assert_code(const ubyte *filename, int lineno, int errorcode)
up_ledon(LED_ASSERTION); up_ledon(LED_ASSERTION);
#if CONFIG_TASK_NAME_SIZE > 0 #if CONFIG_TASK_NAME_SIZE > 0
dbg("Assertion failed at file:%s line: %d task: %s error code: %d\n", lldbg("Assertion failed at file:%s line: %d task: %s error code: %d\n",
filename, lineno, rtcb->name, errorcode); filename, lineno, rtcb->name, errorcode);
#else #else
dbg("Assertion failed at file:%s line: %d error code: %d\n", lldbg("Assertion failed at file:%s line: %d error code: %d\n",
filename, lineno, errorcode); filename, lineno, errorcode);
#endif #endif
up_stackdump(); up_stackdump();

7
arch/c5471/src/up_idle.c
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@ -75,9 +75,10 @@
void up_idle(void) void up_idle(void)
{ {
#ifdef CONFIG_SUPPRESS_INTERRUPTS #if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle, then process "fake" timer interrupts. /* If the system is idle and there are no timer interrupts,
* Hopefully, something will wake up. * then process "fake" timer interrupts. Hopefully, something
* will wake up.
*/ */
sched_process_timer(); sched_process_timer();

2
arch/c5471/src/up_initialize.c
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@ -88,7 +88,7 @@ void up_initialize(void)
/* Initialize the system timer interrupt */ /* Initialize the system timer interrupt */
#ifndef CONFIG_SUPPRESS_INTERRUPTS #if !defined(CONFIG_SUPPRESS_INTERRUPTS) && !defined(CONFIG_SUPPRESS_TIMER_INTS)
up_timerinit(); up_timerinit();
#endif #endif

4
arch/c5471/src/up_internal.h
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@ -49,7 +49,9 @@
* board bring-up and not part of normal platform configuration. * board bring-up and not part of normal platform configuration.
*/ */
#define CONFIG_SUPPRESS_INTERRUPTS 1 /* Do not enable interrupts */ #undef CONFIG_SUPPRESS_INTERRUPTS /* Do not enable interrupts */
#define CONFIG_SUPPRESS_TIMER_INTS 1 /* No timer */
#define CONFIG_SUPPRESS_SERIAL_INTS 1 /* Console will poll */
#undef CONFIG_SUPPRESS_UART_CONFIG /* Do not reconfig UART */ #undef CONFIG_SUPPRESS_UART_CONFIG /* Do not reconfig UART */
#define CONFIG_C5471_STACKDUMP 1 /* Dump stack on assertion */ #define CONFIG_C5471_STACKDUMP 1 /* Dump stack on assertion */

12
arch/c5471/src/up_serial.c
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@ -252,14 +252,18 @@ static inline void up_disablerxint(up_dev_t *dev)
static inline void up_enabletxint(up_dev_t *dev) static inline void up_enabletxint(up_dev_t *dev)
{ {
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
dev->regs.ier |= UART_IER_XmitInt; dev->regs.ier |= UART_IER_XmitInt;
up_serialout(dev, UART_IER_OFFS, dev->regs.ier); up_serialout(dev, UART_IER_OFFS, dev->regs.ier);
#endif
} }
static inline void up_enablerxint(up_dev_t *dev) static inline void up_enablerxint(up_dev_t *dev)
{ {
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
dev->regs.ier |= UART_IER_RecvInt; dev->regs.ier |= UART_IER_RecvInt;
up_serialout(dev, UART_IER_OFFS, dev->regs.ier); up_serialout(dev, UART_IER_OFFS, dev->regs.ier);
#endif
} }
static inline void up_disableuartint(up_dev_t *dev, uint16 *ier) static inline void up_disableuartint(up_dev_t *dev, uint16 *ier)
@ -617,7 +621,7 @@ static void up_putxmitchar(up_dev_t *dev, int ch)
{ {
/* Still no space */ /* Still no space */
#ifdef CONFIG_SUPPRESS_INTERRUPTS #if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_SERIAL_INTS)
up_waittxfifonotfull(dev); up_waittxfifonotfull(dev);
#else #else
dev->xmitwaiting = TRUE; dev->xmitwaiting = TRUE;
@ -876,7 +880,7 @@ static ssize_t up_read(struct file *filep, char *buffer, size_t buflen)
} }
} }
up_enabletxint(dev); up_enablerxint(dev);
return ret; return ret;
} }
@ -1026,8 +1030,10 @@ static int up_open(struct file *filep)
/* Attache and enabled the IRQ */ /* Attache and enabled the IRQ */
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
ret = irq_attach(dev->irq, up_interrupt); ret = irq_attach(dev->irq, up_interrupt);
if (ret == OK) if (ret == OK)
#endif
{ {
/* Mark the io buffers empty */ /* Mark the io buffers empty */
@ -1038,7 +1044,9 @@ static int up_open(struct file *filep)
/* Finally, enable interrupts */ /* Finally, enable interrupts */
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
up_enable_irq(dev->irq); up_enable_irq(dev->irq);
#endif
up_enablerxint(dev); up_enablerxint(dev);
} }
irqrestore(flags); irqrestore(flags);

20
arch/c5471/src/up_timerisr.c
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@ -89,29 +89,9 @@
int up_timerisr(int irq, uint32 *regs) int up_timerisr(int irq, uint32 *regs)
{ {
uint32 *saved_regs;
/* Save the pointer to the interrupted context (exercising some
* logic for the unexpected case of nested interrupts).
*/
if (!current_regs)
{
saved_regs = NULL;
current_regs = regs;
}
else
{
saved_regs = current_regs;
}
/* Process timer interrupt */ /* Process timer interrupt */
sched_process_timer(); sched_process_timer();
/* Restore the previous context */
current_regs = saved_regs;
return 0; return 0;
} }

22
arch/c5471/src/up_vectors.S
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@ -50,13 +50,13 @@
************************************************************/ ************************************************************/
.data .data
up_irqtmp: g_irqtmp:
.word 0 /* Saved lr */ .word 0 /* Saved lr */
.word 0 /* Saved spsr */ .word 0 /* Saved spsr */
up_undeftmp: g_undeftmp:
.word 0 /* Saved lr */ .word 0 /* Saved lr */
.word 0 /* Saved spsr */ .word 0 /* Saved spsr */
up_aborttmp: g_aborttmp:
.word 0 /* Saved lr */ .word 0 /* Saved lr */
.word 0 /* Saved spsr */ .word 0 /* Saved spsr */
@ -102,7 +102,7 @@ up_vectorirq:
bic lr, lr, #MODE_MASK /* Keep F and T bits */ bic lr, lr, #MODE_MASK /* Keep F and T bits */
orr lr, lr, #I_BIT | SVC_MODE orr lr, lr, #I_BIT | SVC_MODE
msr spsr_c, lr /* Swith to SVC mode */ msr cpsr, lr /* Swith to SVC mode */
/* Create a context structure */ /* Create a context structure */
@ -156,7 +156,7 @@ up_vectorirq:
ldmia sp, {r0-r15}^ /* Return */ ldmia sp, {r0-r15}^ /* Return */
.Lirqtmp: .Lirqtmp:
.word up_irqtmp .word g_irqtmp
.align 5 .align 5
@ -231,7 +231,7 @@ up_vectordata:
bic lr, lr, #MODE_MASK /* Keep F and T bits */ bic lr, lr, #MODE_MASK /* Keep F and T bits */
orr lr, lr, #I_BIT | SVC_MODE orr lr, lr, #I_BIT | SVC_MODE
msr spsr_c, lr /* Swith to SVC mode */ msr cpsr, lr /* Swith to SVC mode */
/* Create a context structure */ /* Create a context structure */
@ -257,7 +257,7 @@ up_vectordata:
ldmia sp, {r0-r15}^ /* Return */ ldmia sp, {r0-r15}^ /* Return */
.Ldaborttmp: .Ldaborttmp:
.word up_aborttmp .word g_aborttmp
.align 5 .align 5
@ -286,7 +286,7 @@ up_vectorprefetch:
bic lr, lr, #MODE_MASK /* Keep F and T bits */ bic lr, lr, #MODE_MASK /* Keep F and T bits */
orr lr, lr, #I_BIT | SVC_MODE orr lr, lr, #I_BIT | SVC_MODE
msr spsr_c, lr /* Swith to SVC mode */ msr cpsr, lr /* Swith to SVC mode */
/* Create a context structure */ /* Create a context structure */
@ -312,7 +312,7 @@ up_vectorprefetch:
ldmia sp, {r0-r15}^ /* Return */ ldmia sp, {r0-r15}^ /* Return */
.Lpaborttmp: .Lpaborttmp:
.word up_aborttmp .word g_aborttmp
.align 5 .align 5
@ -341,7 +341,7 @@ up_vectorundefinsn:
bic lr, lr, #MODE_MASK /* Keep F and T bits */ bic lr, lr, #MODE_MASK /* Keep F and T bits */
orr lr, lr, #I_BIT | SVC_MODE orr lr, lr, #I_BIT | SVC_MODE
msr spsr_c, lr /* Swith to SVC mode */ msr cpsr, lr /* Swith to SVC mode */
/* Create a context structure */ /* Create a context structure */
@ -367,7 +367,7 @@ up_vectorundefinsn:
ldmia sp, {r0-r15}^ /* Return */ ldmia sp, {r0-r15}^ /* Return */
.Lundeftmp: .Lundeftmp:
.word up_undeftmp .word g_undeftmp
.align 5 .align 5