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PIC32MX SPI: Fix typos in Kconfig; Move constant SPI config data to ROM-able const structure

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This commit is contained in:
Gregory Nutt 2015-03-03 10:06:49 -06:00
parent da2319a27f
commit a3464c54bd
2 changed files with 85 additions and 53 deletions
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12
arch/mips/src/pic32mz/Kconfig
View File

@ -142,32 +142,32 @@ config PIC32MZ_I2C5
config PIC32MZ_SPI1 config PIC32MZ_SPI1
bool "SPI1" bool "SPI1"
default n default n
select PIC32MX_SPI select PIC32MZ_SPI
config PIC32MZ_SPI2 config PIC32MZ_SPI2
bool "SPI2" bool "SPI2"
default n default n
select PIC32MX_SPI select PIC32MZ_SPI
config PIC32MZ_SPI3 config PIC32MZ_SPI3
bool "SPI3" bool "SPI3"
default n default n
select PIC32MX_SPI select PIC32MZ_SPI
config PIC32MZ_SPI4 config PIC32MZ_SPI4
bool "SPI4" bool "SPI4"
default n default n
select PIC32MX_SPI select PIC32MZ_SPI
config PIC32MZ_SPI5 config PIC32MZ_SPI5
bool "SPI5" bool "SPI5"
default n default n
select PIC32MX_SPI select PIC32MZ_SPI
config PIC32MZ_SPI6 config PIC32MZ_SPI6
bool "SPI6" bool "SPI6"
default n default n
select PIC32MX_SPI select PIC32MZ_SPI
config PIC32MZ_UART1 config PIC32MZ_UART1
bool "UART1" bool "UART1"

126
arch/mips/src/pic32mz/pic32mz-spi.c
View File

@ -66,17 +66,7 @@
#define BOARD_PBCLOCK BOARD_PBCLK2 #define BOARD_PBCLOCK BOARD_PBCLK2
/* Enables non-standard debug output from this file. /* Debug */
*
* CONFIG_SPI_DEBUG && CONFIG_DEBUG - Define to enable basic SPI debug
* CONFIG_DEBUG_VERBOSE - Define to enable verbose SPI debug
*/
#ifndef CONFIG_DEBUG
# undef CONFIG_DEBUG_SPI
# undef CONFIG_DEBUG_VERBOSE
# undef CONFIG_SPI_REGDEBUG
#endif
#ifdef CONFIG_DEBUG_SPI #ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg # define spidbg lldbg
@ -93,12 +83,12 @@
/**************************************************************************** /****************************************************************************
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
/* This structure describes the fixed (ROM-able) configuration of the SPI
* peripheral.
*/
/* This structure describes the state of the SSP driver */ struct pic32mz_config_s
struct pic32mz_dev_s
{ {
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
uint32_t base; /* SPI register base address */ uint32_t base; /* SPI register base address */
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
uint8_t firq; /* SPI fault interrupt number */ uint8_t firq; /* SPI fault interrupt number */
@ -108,6 +98,15 @@ struct pic32mz_dev_s
uint8_t sdipps; /* SDI peripheral pin selection */ uint8_t sdipps; /* SDI peripheral pin selection */
uint8_t sdopps; /* SDO peripheral pin selection */ uint8_t sdopps; /* SDO peripheral pin selection */
uintptr_t sdoreg; /* SDO peripheral pin configuration register */ uintptr_t sdoreg; /* SDO peripheral pin configuration register */
};
/* This structure describes the state of the SPI driver */
struct pic32mz_dev_s
{
struct spi_dev_s spidev; /* Externally visible part of the SPI interface */
FAR const struct pic32mz_config_s *config;
#ifndef CONFIG_SPI_OWNBUS #ifndef CONFIG_SPI_OWNBUS
sem_t exclsem; /* Held while chip is selected for mutual exclusion */ sem_t exclsem; /* Held while chip is selected for mutual exclusion */
uint32_t frequency; /* Requested clock frequency */ uint32_t frequency; /* Requested clock frequency */
@ -168,9 +167,8 @@ static const struct spi_ops_s g_spi1ops =
#endif #endif
}; };
static struct pic32mz_dev_s g_spi1dev = static const struct pic32mz_config_s g_spi1config =
{ {
.spidev = { &g_spi1ops },
.base = PIC32MZ_SPI1_K1BASE, .base = PIC32MZ_SPI1_K1BASE,
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
.firq = PIC32MZ_IRQ_SPI1F, .firq = PIC32MZ_IRQ_SPI1F,
@ -181,6 +179,12 @@ static struct pic32mz_dev_s g_spi1dev =
.sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO1_PPS), .sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO1_PPS),
.sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO1_PPS), .sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO1_PPS),
}; };
static struct pic32mz_dev_s g_spi1dev =
{
.spidev = { &g_spi1ops },
.config = &g_spi1config,
};
#endif #endif
#ifdef CONFIG_PIC32MZ_SPI2 #ifdef CONFIG_PIC32MZ_SPI2
@ -207,9 +211,8 @@ static const struct spi_ops_s g_spi2ops =
#endif #endif
}; };
static struct pic32mz_dev_s g_spi2dev = static const struct pic32mz_config_s g_spi2config =
{ {
.spidev = { &g_spi2ops },
.base = PIC32MZ_SPI2_K1BASE, .base = PIC32MZ_SPI2_K1BASE,
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
.firq = PIC32MZ_IRQ_SPI2F, .firq = PIC32MZ_IRQ_SPI2F,
@ -220,6 +223,12 @@ static struct pic32mz_dev_s g_spi2dev =
.sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO2_PPS), .sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO2_PPS),
.sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO2_PPS), .sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO2_PPS),
}; };
static struct pic32mz_dev_s g_spi2dev =
{
.spidev = { &g_spi2ops },
.config = &g_spi2config,
};
#endif #endif
#ifdef CONFIG_PIC32MZ_SPI3 #ifdef CONFIG_PIC32MZ_SPI3
@ -246,9 +255,8 @@ static const struct spi_ops_s g_spi3ops =
#endif #endif
}; };
static struct pic32mz_dev_s g_spi3dev = static const struct pic32mz_config_s g_spi3config =
{ {
.spidev = { &g_spi3ops },
.base = PIC32MZ_SPI3_K1BASE, .base = PIC32MZ_SPI3_K1BASE,
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
.firq = PIC32MZ_IRQ_SPI3F, .firq = PIC32MZ_IRQ_SPI3F,
@ -259,6 +267,12 @@ static struct pic32mz_dev_s g_spi3dev =
.sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO3_PPS), .sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO3_PPS),
.sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO3_PPS), .sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO3_PPS),
}; };
static struct pic32mz_dev_s g_spi3dev =
{
.spidev = { &g_spi3ops },
.config = &g_spi3config,
};
#endif #endif
#ifdef CONFIG_PIC32MZ_SPI4 #ifdef CONFIG_PIC32MZ_SPI4
@ -285,9 +299,8 @@ static const struct spi_ops_s g_spi4ops =
#endif #endif
}; };
static struct pic32mz_dev_s g_spi4dev = static const struct pic32mz_config_s g_spi4config =
{ {
.spidev = { &g_spi4ops },
.base = PIC32MZ_SPI4_K1BASE, .base = PIC32MZ_SPI4_K1BASE,
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
.firq = PIC32MZ_IRQ_SPI4F, .firq = PIC32MZ_IRQ_SPI4F,
@ -298,6 +311,12 @@ static struct pic32mz_dev_s g_spi4dev =
.sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO4_PPS), .sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO4_PPS),
.sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO4_PPS), .sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO4_PPS),
}; };
static struct pic32mz_dev_s g_spi4dev =
{
.spidev = { &g_spi4ops },
.config = &g_spi4config,
};
#endif #endif
#ifdef CONFIG_PIC32MZ_SPI5 #ifdef CONFIG_PIC32MZ_SPI5
@ -324,9 +343,8 @@ static const struct spi_ops_s g_spi5ops =
#endif #endif
}; };
static struct pic32mz_dev_s g_spi5dev = static const struct pic32mz_config_s g_spi5config =
{ {
.spidev = { &g_spi5ops },
.base = PIC32MZ_SPI5_K1BASE, .base = PIC32MZ_SPI5_K1BASE,
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
.firq = PIC32MZ_IRQ_SPI5F, .firq = PIC32MZ_IRQ_SPI5F,
@ -337,6 +355,12 @@ static struct pic32mz_dev_s g_spi5dev =
.sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO5_PPS), .sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO5_PPS),
.sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO5_PPS), .sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO5_PPS),
}; };
static struct pic32mz_dev_s g_spi5dev =
{
.spidev = { &g_spi5ops },
.config = &g_spi5config,
};
#endif #endif
#ifdef CONFIG_PIC32MZ_SPI6 #ifdef CONFIG_PIC32MZ_SPI6
@ -363,9 +387,8 @@ static const struct spi_ops_s g_spi6ops =
#endif #endif
}; };
static struct pic32mz_dev_s g_spi6dev = static const struct pic32mz_config_s g_spi6config =
{ {
.spidev = { &g_spi6ops },
.base = PIC32MZ_SPI6_K1BASE, .base = PIC32MZ_SPI6_K1BASE,
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
.firq = PIC32MZ_IRQ_SPI6F, .firq = PIC32MZ_IRQ_SPI6F,
@ -376,6 +399,12 @@ static struct pic32mz_dev_s g_spi6dev =
.sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO6_PPS), .sdopps = PPS_OUTPUT_REGVAL(BOARD_SDO6_PPS),
.sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO6_PPS), .sdoreg = PPS_OUTPUT_REGADDR(BOARD_SDO6_PPS),
}; };
static struct pic32mz_dev_s g_spi6dev =
{
.spidev = { &g_spi6ops },
.config = &g_spi6config,
};
#endif #endif
/**************************************************************************** /****************************************************************************
@ -417,7 +446,7 @@ static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv, unsigned int offset)
/* Read the value from the register */ /* Read the value from the register */
addr = priv->base + offset; addr = priv->config->base + offset;
value = getreg32(addr); value = getreg32(addr);
/* Is this the same value that we read from the same register last time? /* Is this the same value that we read from the same register last time?
@ -464,7 +493,7 @@ static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv, unsigned int offset)
#else #else
static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv, unsigned int offset) static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv, unsigned int offset)
{ {
return getreg32(priv->base + offset); return getreg32(priv->config->base + offset);
} }
#endif #endif
@ -492,7 +521,7 @@ static void spi_putreg(FAR struct pic32mz_dev_s *priv, unsigned int offset,
/* Get the address to write to */ /* Get the address to write to */
addr = priv->base + offset; addr = priv->config->base + offset;
/* Show the register value being written */ /* Show the register value being written */
@ -506,7 +535,7 @@ static void spi_putreg(FAR struct pic32mz_dev_s *priv, unsigned int offset,
static void spi_putreg(FAR struct pic32mz_dev_s *priv, unsigned int offset, static void spi_putreg(FAR struct pic32mz_dev_s *priv, unsigned int offset,
uint32_t value) uint32_t value)
{ {
putreg32(value, priv->base + offset); putreg32(value, priv->config->base + offset);
} }
#endif #endif
@ -1051,9 +1080,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
flags = irqsave(); flags = irqsave();
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
up_disable_irq(priv->firq); up_disable_irq(priv->config->firq);
up_disable_irq(priv->txirq); up_disable_irq(priv->config->rxirq);
up_disable_irq(priv->rxirq); up_disable_irq(priv->config->txirq);
#endif #endif
/* Stop and reset the SPI module by clearing the ON bit in the CON register. */ /* Stop and reset the SPI module by clearing the ON bit in the CON register. */
@ -1068,32 +1097,35 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
* managed as GPIOs; CLK (output) pins are not selectable. * managed as GPIOs; CLK (output) pins are not selectable.
*/ */
putreg32((uint32_t)priv->sdipps, regaddr); putreg32((uint32_t)priv->config->sdipps, regaddr);
putreg32((uint32_t)priv->sdopps, priv->sdoreg); putreg32((uint32_t)priv->config->sdopps, priv->config->sdoreg);
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
/* Attach the interrupt handlers. We do this early to make sure that the /* Attach the interrupt handlers. We do this early to make sure that the
* resources are available. * resources are available.
*/ */
ret = irq_attach(priv->rxirq, spi_interrupt); ret = irq_attach(priv->config->rxirq, spi_interrupt);
if (ret < 0) if (ret < 0)
{ {
spidbg("Failed to attach RX interrupt: %d port: %d\n", priv->rxirq, port); spidbg("Failed to attach RX interrupt: %d port: %d\n",
priv->config->rxirq, port);
goto errout; goto errout;
} }
ret = irq_attach(priv->txirq, spi_interrupt); ret = irq_attach(priv->config->txirq, spi_interrupt);
if (ret < 0) if (ret < 0)
{ {
spidbg("Failed to attach TX interrupt: %d port: %d\n", priv->txirq, port); spidbg("Failed to attach TX interrupt: %d port: %d\n",
priv->tconfig->xirq, port);
goto errout_with_rxirq; goto errout_with_rxirq;
} }
ret = irq_attach(priv->firq, spi_interrupt); ret = irq_attach(priv->config->firq, spi_interrupt);
if (ret < 0) if (ret < 0)
{ {
spidbg("Failed to attach fault interrupt: %d port: %d\n", priv->firq, port); spidbg("Failed to attach fault interrupt: %d port: %d\n",
priv->config->firq, port);
goto errout_with_txirq; goto errout_with_txirq;
} }
#endif #endif
@ -1137,9 +1169,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
/* Enable interrupts at the SPI controller */ /* Enable interrupts at the SPI controller */
up_enable_irq(priv->firq); up_enable_irq(priv->config->firq);
up_enable_irq(priv->txirq); up_enable_irq(priv->config->rxirq);
up_enable_irq(priv->rxirq); up_enable_irq(priv->config->txirq);
#endif #endif
/* Enable interrupts at the interrupt controller */ /* Enable interrupts at the interrupt controller */
@ -1149,9 +1181,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
#ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS #ifdef CONFIG_PIC32MZ_SPI_INTERRUPTS
errout_with_txirq: errout_with_txirq:
irq_detatch(priv->txirq); irq_detatch(priv->config->txirq);
errout_with_rxirq: errout_with_rxirq:
irq_detatch(priv->rxirq); irq_detatch(priv->config->rxirq);
errout: errout:
irqrestore(flags); irqrestore(flags);
return NULL; return NULL;