diff --git a/arch/arm/src/imxrt/hardware/imxrt_usdhc.h b/arch/arm/src/imxrt/hardware/imxrt_usdhc.h
index 2a0ec097bd..146d8c2a23 100644
--- a/arch/arm/src/imxrt/hardware/imxrt_usdhc.h
+++ b/arch/arm/src/imxrt/hardware/imxrt_usdhc.h
@@ -58,7 +58,7 @@
 #define IMXRT_USDHC_CMDRSP1_OFFSET       0x0014 /* Command Response 1 */
 #define IMXRT_USDHC_CMDRSP2_OFFSET       0x0018 /* Command Response 2 */
 #define IMXRT_USDHC_CMDRSP3_OFFSET       0x001c /* Command Response 3 */
-#define IMXRT_USDHC_DATPORT_OFFSET       0x0020 /* Buffer Data Port Register */
+#define IMXRT_USDHC_DATAPORT_OFFSET      0x0020 /* Buffer Data Port Register */
 #define IMXRT_USDHC_PRSSTAT_OFFSET       0x0024 /* Present State Register */
 #define IMXRT_USDHC_PROCTL_OFFSET        0x0028 /* Protocol Control Register */
 #define IMXRT_USDHC_SYSCTL_OFFSET        0x002c /* System Control Register */
@@ -92,7 +92,7 @@
 #define IMXRT_USDHC1_CMDRSP1             (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP1_OFFSET)
 #define IMXRT_USDHC1_CMDRSP2             (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP2_OFFSET)
 #define IMXRT_USDHC1_CMDRSP3             (IMXRT_USDHC1_BASE + IMXRT_USDHC_CMDRSP3_OFFSET)
-#define IMXRT_USDHC1_DATPORT             (IMXRT_USDHC1_BASE + IMXRT_USDHC_DATPORT_OFFSET)
+#define IMXRT_USDHC1_DATAPORT            (IMXRT_USDHC1_BASE + IMXRT_USDHC_DATAPORT_OFFSET)
 #define IMXRT_USDHC1_PRSSTAT             (IMXRT_USDHC1_BASE + IMXRT_USDHC_PRSSTAT_OFFSET)
 #define IMXRT_USDHC1_PROCTL              (IMXRT_USDHC1_BASE + IMXRT_USDHC_PROCTL_OFFSET)
 #define IMXRT_USDHC1_SYSCTL              (IMXRT_USDHC1_BASE + IMXRT_USDHC_SYSCTL_OFFSET)
@@ -124,7 +124,7 @@
 #define IMXRT_USDHC2_CMDRSP1             (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP1_OFFSET)
 #define IMXRT_USDHC2_CMDRSP2             (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP2_OFFSET)
 #define IMXRT_USDHC2_CMDRSP3             (IMXRT_USDHC2_BASE + IMXRT_USDHC_CMDRSP3_OFFSET)
-#define IMXRT_USDHC2_DATPORT             (IMXRT_USDHC2_BASE + IMXRT_USDHC_DATPORT_OFFSET)
+#define IMXRT_USDHC2_DATAPORT            (IMXRT_USDHC2_BASE + IMXRT_USDHC_DATPORT_OFFSET)
 #define IMXRT_USDHC2_PRSSTAT             (IMXRT_USDHC2_BASE + IMXRT_USDHC_PRSSTAT_OFFSET)
 #define IMXRT_USDHC2_PROCTL              (IMXRT_USDHC2_BASE + IMXRT_USDHC_PROCTL_OFFSET)
 #define IMXRT_USDHC2_SYSCTL              (IMXRT_USDHC2_BASE + IMXRT_USDHC_SYSCTL_OFFSET)
diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c
index 4470b3064a..d625a5c01e 100644
--- a/arch/arm/src/imxrt/imxrt_usdhc.c
+++ b/arch/arm/src/imxrt/imxrt_usdhc.c
@@ -989,7 +989,7 @@ static void imxrt_receive(struct imxrt_dev_s *priv)
            priv->addr + IMXRT_USDHC_WML_OFFSET);
 
   mcinfo("Exit: remaining: %d IRQSTAT: %08x WML: %08x\n", priv->remaining,
-         getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET);
+         getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET),
          getreg32(priv->addr + IMXRT_USDHC_WML_OFFSET));
 }
 #endif
@@ -1104,9 +1104,11 @@ static void imxrt_endtransfer(struct imxrt_dev_s *priv,
 
   priv->remaining = 0;
 
+#ifdef CONFIG_IMXRT_USDHC_DMA
   /* DMA modified the buffer, so we need to flush its cache lines. */
 
   up_invalidate_dcache((uintptr_t) priv->buffer, (uintptr_t) priv->bufferend);
+#endif
 
   /* Debug instrumentation */
 
@@ -2017,6 +2019,11 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
    * overlap and maximum performance.
    */
 
+  if ((getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET) & USDHC_RESPERR_INTS) != 0)
+    {
+      putreg32(USDHC_SYSCTL_RSTC, priv->addr + IMXRT_USDHC_SYSCTL_OFFSET);
+    }
+
   timeout = USDHC_CMDTIMEOUT;
   start   = clock_systimer();
   while ((getreg32(priv->addr + IMXRT_USDHC_PRSSTAT_OFFSET) &
@@ -2324,9 +2331,6 @@ static int imxrt_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
         ret = -EIO;
     }
 
-  /* Clear the response wait status bits */
-
-  putreg32(USDHC_RESPDONE_INTS, priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET);
   return ret;
 }