sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

SAM4E: Update SAM3/4 SMC and SUPC register definition header files

Browse Source
This commit is contained in:
Gregory Nutt 2014-02-24 10:26:44 -06:00
parent 6a5abb6cf9
commit a39db83fcc
4 changed files with 82 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

66
arch/arm/src/sam34/chip/sam3u_smc.h → arch/arm/src/sam34/chip/sam_smc.h
View File

@ -1,8 +1,8 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_smc.h
* arch/arm/src/sam34/chip/sam_smc.h
* Static Memory Controller (SMC) definitions for the SAM3U and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -34,8 +34,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SMC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SMC_H
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H
/****************************************************************************************
* Included Files
@ -101,7 +101,7 @@
# define SAM_SMC_WPCR_OFFSET 0x01e4 /* Write Protection Control Register */
# define SAM_SMC_WPSR_OFFSET 0x01e8 /* Write Protection Status Register */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SAM_SMCCS_OFFSET(n) ((n) << 4)
# define SAM_SMCCS0_OFFSET 0x0000 /* SMC CS0 offset */
# define SAM_SMCCS1_OFFSET 0x0010 /* SMC CS1 offset */
@ -466,18 +466,33 @@
/* SMC Pulse Register */
#define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */
#define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT)
# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT)
#define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */
#define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT)
#define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */
#define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT)
# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT)
#define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */
#define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-6: NWE Pulse Length */
# define SMCCS_PULSE_NWEPULSE_MASK (127 << SMCCS_PULSE_NWEPULSE_SHIFT)
# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT)
# define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-14: NCS Pulse Length in WRITE Access */
# define SMCCS_PULSE_NCSWRPULSE_MASK (127 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT)
# define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-22: NRD Pulse Length */
# define SMCCS_PULSE_NRDPULSE_MASK (127 << SMCCS_PULSE_NRDPULSE_SHIFT)
# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT)
# define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-30: NCS Pulse Length in READ Access */
# define SMCCS_PULSE_NCSRDPULSE_MASK (127 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT)
#else
# define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */
# define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT)
# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT)
# define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */
# define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT)
# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT)
# define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */
# define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT)
# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT)
# define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */
# define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT)
# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT)
#endif
/* SMC Cycle Register */
@ -530,9 +545,11 @@
#define SMCCS_MODE_TDFCYCLES_SHIFT (16) /* Bits 16-19: Data Float Time */
#define SMCCS_MODE_TDFCYCLES_MASK (15 << SMCCS_MODE_TDFCYCLES_SHIFT)
# define SMCCS_MODE_TDFCYCLES(n) ((uint32_t)(n) << SMCCS_MODE_TDFCYCLES_SHIFT)
#define SMCCS_MODE_TDFMODE (1 << 20) /* Bit 20: TDF Optimization */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
# define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
# define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
@ -545,9 +562,12 @@
/* SMC OCMS Mode Register */
#define SMC_OCMS_SMSE (1 << 0) /* Bit 0: Static Memory Controller Scrambling Enable */
#define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if !defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMC_OCMS_SRSE (1 << 1) /* Bit 1: SRAM Scrambling Enable */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */
# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */
# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */
@ -559,7 +579,7 @@
/* SMC Write Protect Mode Register */
#define SMC_WPCR_WPPEN (1 << 9) /* Bit 9: Write Protection Enable */
#define SMC_WPCR_WPPEN (1 << 0) /* Bit 0: Write Protection Enable */
#define SMC_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY password */
#define SMC_WPCR_WPKEY_MASK (0x00ffffff << SMC_WPCR_WPKEY_SHIFT)
# define SMC_WPCR_WPKEY (0x00534d43 << SMC_WPCR_WPKEY_SHIFT)
@ -574,7 +594,7 @@
# define SMC_WPSR_PVS_ RCREG (1 << SMC_WPSR_PVS_SHIFT) /* Attempt to write a control reg */
# define SMC_WPSR_PVS_RESET (2 << SMC_WPSR_PVS_SHIFT) /* Software reset */
# define SMC_WPSR_PVS_BOTH (3 << SMC_WPSR_PVS_SHIFT) /* Write + reset */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
#elif defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMC_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Source */
#endif
@ -593,4 +613,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SMC_H */
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SMC_H */

9
arch/arm/src/sam34/chip/sam_spi.h
View File

@ -237,8 +237,13 @@
/* SPI Write Protection Status Register */
#define SPI_WPSR_WPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
#define SPI_WPSR_WPVS_MASK (7 << SPI_WPSR_WPVS_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define SPI_WPSR_WPVS (1 << 0) /* Bit 0: SPI Write Protection Violation Status */
#else
# define SPI_WPSR_WPVS_SHIFT (0) /* Bits 0-2: SPI Write Protection Violation Status */
# define SPI_WPSR_WPVS_MASK (7 << SPI_WPSR_WPVS_SHIFT)
#endif
#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT)

49
arch/arm/src/sam34/chip/sam3u_supc.h → arch/arm/src/sam34/chip/sam_supc.h
View File

@ -1,8 +1,8 @@
/****************************************************************************************
* arch/arm/src/sam34/chip/sam3u_supc.h
* Supply Controller (SUPC) definitions for the SAM3U, SAM3X, SAM3A, and SAM4S
* arch/arm/src/sam34/chip/sam_supc.h
* Supply Controller (SUPC) definitions for the SAM3U, SAM3X, SAM3A, SAM4E, and SAM4S
*
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2013-2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -34,8 +34,8 @@
*
****************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
/****************************************************************************************
* Included Files
@ -59,7 +59,7 @@
#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
/* SUPC register adresses ***************************************************************/
/* SUPC register addresses **************************************************************/
#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
@ -81,8 +81,9 @@
#define SUPC_SMMR_SMTH_SHIFT (0) /* Bits 0-3: Supply Monitor Threshold */
#define SUPC_SMMR_SMTH_MASK (15 << SUPC_SMMR_SMTH_SHIFT)
# define SUPC_SMMR_SMTH(n) ((uint32_t)(n) << SUPC_SMMR_SMTH_SHIFT)
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_SMMR_SMTH_1p6V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.56 < 1.6 < 1.64 */
# define SUPC_SMMR_SMTH_1p7V (1 << SUPC_SMMR_SMTH_SHIFT) /* 1.68 < 1.72 < 1.76 */
# define SUPC_SMMR_SMTH_1p8V (2 << SUPC_SMMR_SMTH_SHIFT) /* 1.79 < 1.84 < 1.89 */
@ -99,7 +100,8 @@
# define SUPC_SMMR_SMTH_3p2V (13 << SUPC_SMMR_SMTH_SHIFT) /* 3.08 < 3.16 < 3.24 */
# define SUPC_SMMR_SMTH_3p3V (14 << SUPC_SMMR_SMTH_SHIFT) /* 3.20 < 3.28 < 3.36 */
# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.32 < 3.4 < 3.49 */
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_SMMR_SMTH_1p9V (0 << SUPC_SMMR_SMTH_SHIFT) /* 1.9V */
# define SUPC_SMMR_SMTH_2p0V (1 << SUPC_SMMR_SMTH_SHIFT) /* 2.0V */
# define SUPC_SMMR_SMTH_2p1V (2 << SUPC_SMMR_SMTH_SHIFT) /* 2.1V */
@ -133,21 +135,24 @@
#define SUPC_MR_BODRSTEN (1 << 12) /* Bit 12: Brownout Detector Reset Enable */
#define SUPC_MR_BODDIS (1 << 13) /* Bit 13: Brownout Detector Disable */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_MR_ONREG (1 << 14) /* Bit 14: Voltage Regulator enable */
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SUPC_MR_VDDIORDY (1 << 14) /* Bit 14: VDDIO Ready */
#endif
#define SUPC_MR_OSCBYPASS (1 << 20) /* Bit 20: Oscillator Bypass */
#define SUPC_MR_KEY_SHIFT (24) /* Bits 24-31: Password Key */
#define SUPC_MR_KEY_MASK (0xff << SUPC_MR_KEY_SHIFT)
# define SUPC_MR_KEY (0xa5 << SUPC_MR_KEY_SHIFT)
/* Supply Controller Wake Up Mode Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_WUMR_FWUPEN (1 << 0) /* Bit 0: Force Wake Up Enable */
#endif
@ -155,11 +160,14 @@
#define SUPC_WUMR_RTTEN (1 << 2) /* Bit 2: Real Time Timer Wake Up Enable */
#define SUPC_WUMR_RTCEN (1 << 3) /* Bit 3: Real Time Clock Wake Up Enable */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_WUMR_LPDBCEN0 (1 << 5) /* Bit 5: Low power Debouncer ENable WKUP0 */
# define SUPC_WUMR_LPDBCEN1 (1 << 6) /* Bit 6: Low power Debouncer ENable WKUP1 */
# define SUPC_WUMR_LPDBCCLR (1 << 7) /* Bit 7: Low power Debouncer Clear */
#elif defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_WUMR_FWUPDBC_SHIFT (8) /* Bits 8-10: Force Wake Up Debouncer */
# define SUPC_WUMR_FWUPDBC_MASK (7 << SUPC_WUMR_FWUPDBC_SHIFT)
# define SUPC_WUMR_FWUPDBC_1SCLK (0 << SUPC_WUMR_FWUPDBC_SHIFT) /* Immediate, no debouncing */
@ -179,7 +187,7 @@
# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
#if defined(CONFIG_ARCH_CHIP_SAM4S)
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_WUMR_LPDBC_SHIFT (16) /* Bits 16-18: Low Power Debouncer Period */
# define SUPC_WUMR_LPDBC_MASK (7 << SUPC_WUMR_LPDBC_SHIFT)
# define SUPC_WUMR_LPDBC_DISABLE (0 << SUPC_WUMR_LPDBC_SHIFT) /* Disable low power debouncer */
@ -203,7 +211,8 @@
/* Supply Controller Status Register */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_SR_FWUPS (1 << 0) /* Bit 0: FWUP Wake Up Status */
#endif
@ -215,15 +224,19 @@
#define SUPC_SR_SMOS (1 << 6) /* Bit 6: Supply Monitor Output Status */
#define SUPC_SR_OSCSEL (1 << 7) /* Bit 7: 32-kHz Oscillator Selection Status */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A)
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_SR_FWUPIS (1 << 12) /* Bit 12: FWUP Input Status */
#elif defined(CONFIG_ARCH_CHIP_SAM4S)
#endif
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SUPC_SR_LPDBCS0 (1 << 13) /* Bit 13: Low Power Debouncer Wake Up Status on WKUP0 */
# define SUPC_SR_LPDBCS1 (1 << 14) /* Bit 14: Low Power Debouncer Wake Up Status on WKUP1 */
#endif
#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */
#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
# define SUPC_SR_WKUPIS(n) (1 << (SUPC_SR_WKUPIS_SHIFT+(n)))
/****************************************************************************************
* Public Types
@ -237,4 +250,4 @@
* Public Functions
****************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H */
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H */

2
arch/arm/src/sam34/sam_clockconfig.c
View File

@ -52,7 +52,7 @@
#include "chip/sam_pmc.h"
#include "chip/sam_eefc.h"
#include "chip/sam3u_wdt.h"
#include "chip/sam3u_supc.h"
#include "chip/sam_supc.h"
#include "chip/sam_matrix.h"
/****************************************************************************