LPC43xx: Add Ethernet support. From Ilya Averyanov

arch/arm/src/lpc43xx/Kconfig

@@ -163,6 +163,151 @@ config LPC43_ETHERNET
 	bool "Ethernet"
 	default n
 
+if LPC43_ETHERNET
+menu "Ethernet MAC configuration"
+
+config LPC43_PHYADDR
+	int "PHY address"
+	default 1
+	---help---
+		The 5-bit address of the PHY on the board.  Default: 1
+
+config LPC43_PHYINIT
+	bool "Board-specific PHY Initialization"
+	default n
+	---help---
+		Some boards require specialized initialization of the PHY before it can be used.
+		This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+		LPC43_PHYINIT is defined in the configuration then the board specific logic must
+		provide lpc43_phyinitialize();  The LPC43 Ethernet driver will call this function
+		one time before it first uses the PHY.
+
+config LPC43_MII
+	bool "Use MII interface"
+	default n
+	---help---
+		Support Ethernet MII interface.
+
+config LPC43_AUTONEG
+	bool "Use autonegotiation"
+	default y
+	---help---
+		Use PHY autonegotiation to determine speed and mode
+
+config LPC43_ETHFD
+	bool "Full duplex"
+	default n
+	depends on !LPC43_AUTONEG
+	---help---
+		If LPC43_AUTONEG is not defined, then this may be defined to select full duplex
+		mode. Default: half-duplex
+
+config LPC43_ETH100MBPS
+	bool "100 Mbps"
+	default n
+	depends on !LPC43_AUTONEG
+	---help---
+		If LPC43_AUTONEG is not defined, then this may be defined to select 100 MBps
+		speed.  Default: 10 Mbps
+
+config LPC43_PHYSR
+	int "PHY Status Register Address (decimal)"
+	depends on LPC43_AUTONEG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  The PHY status register
+		address may diff from PHY to PHY.  This configuration sets the address of
+		the PHY status register.
+
+config LPC43_PHYSR_ALTCONFIG
+	bool "PHY Status Alternate Bit Layout"
+	default n
+	depends on LPC43_AUTONEG
+	---help---
+		Different PHYs present speed and mode information in different ways.  Some
+		will present separate information for speed and mode (this is the default).
+		Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
+		full/half duplex indication. This options selects an alternative representation
+		where speed and mode information are combined.  This might mean, for example,
+		separate bits for 10HD, 100HD, 10FD and 100FD.
+
+config LPC43_PHYSR_SPEED
+	hex "PHY Speed Mask"
+	depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This provides bit mask
+		for isolating the 10 or 100MBps speed indication.
+
+config LPC43_PHYSR_100MBPS
+	hex "PHY 100Mbps Speed Value"
+	depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This provides the value
+		of the speed bit(s) indicating 100MBps speed.
+
+config LPC43_PHYSR_MODE
+	hex "PHY Mode Mask"
+	depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This provide bit mask
+		for isolating the full or half duplex mode bits.
+
+config LPC43_PHYSR_FULLDUPLEX
+	hex "PHY Full Duplex Mode Value"
+	depends on LPC43_AUTONEG && !LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This provides the
+		value of the mode bits indicating full duplex mode.
+
+config LPC43_PHYSR_ALTMODE
+	hex "PHY Mode Mask"
+	depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This provide bit mask
+		for isolating the speed and full/half duplex mode bits.
+
+config LPC43_PHYSR_10HD
+	hex "10MBase-T Half Duplex Value"
+	depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 10Mbps, half duplex setting.
+
+config LPC43_PHYSR_100HD
+	hex "100Base-T Half Duplex Value"
+	depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 100Mbps, half duplex setting.
+
+config LPC43_PHYSR_10FD
+	hex "10Base-T Full Duplex Value"
+	depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 10Mbps, full duplex setting.
+
+config LPC43_PHYSR_100FD
+	hex "100Base-T Full Duplex Value"
+	depends on LPC43_AUTONEG && LPC43_PHYSR_ALTCONFIG
+	---help---
+		This must be provided if LPC43_AUTONEG is defined.  This is the value
+		under the bit mask that represents the 100Mbps, full duplex setting.
+
+config LPC43_RMII
+	bool
+	default y if !LPC43_MII
+
+
+config LPC43_ETHERNET_REGDEBUG
+	bool "Register-Level Debug"
+	default n
+	depends on DEBUG
+	---help---
+		Enable very low-level register access debug.  Depends on DEBUG.
+
+endmenu
+endif
+
 config LPC43_EVNTMNTR
 	bool "Event Monitor"
 	default n

arch/arm/src/lpc43xx/Make.defs

@@ -118,6 +118,10 @@ ifeq ($(CONFIG_GPIO_IRQ),y)
 CHIP_CSRCS += lpc43_gpioint.c
 endif
 
+ifeq ($(CONFIG_LPC43_ETHERNET),y)
+CHIP_CSRCS += lpc43_ethernet.c
+endif
+
 ifeq ($(CONFIG_LPC43_SPI),y)
 CHIP_CSRCS += lpc43_spi.c
 endif

arch/arm/src/lpc43xx/chip/lpc43_ethernet.h

@@ -181,7 +181,8 @@
 /* MAC frame filter register */
 
 #define ETH_MACFFLT_PR               (1 << 0)  /* Bit 0: Promiscuous mode */
-                                               /* Bits 1-2: Reserved */
+#define ETH_MACFFLT_HUC              (1 << 1)  /* Bit 1: Hash Unicast */
+#define ETH_MACFFLT_HMC              (1 << 2)  /* Bit 2: Hash Multicast */
 #define ETH_MACFFLT_DAIF             (1 << 3)  /* Bit 3: Destination address inverse filtering */
 #define ETH_MACFFLT_PM               (1 << 4)  /* Bit 4: Pass all multicast */
 #define ETH_MACFFLT_DBF              (1 << 5)  /* Bit 5: Disable Broadcast Frames */
@@ -191,9 +192,9 @@
 #  define ETH_MACFFLT_PCF_PAUSE      (1 << ETH_MACFFLT_PCF_SHIFT) /* Prevents all except Pause control frames */
 #  define ETH_MACFFLT_PCF_ALL        (2 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all control frames */
 #  define ETH_MACFFLT_PCF_FILTER     (3 << ETH_MACFFLT_PCF_SHIFT) /* Forwards all that pass address filter */
-#define ETH_MACFFLT_SAIF             (1 << 8)  /* Bit 8: Source address inverse filtering */
+											   /* Bit 8-9: Reserved */
-#define ETH_MACFFLT_SAF              (1 << 9)  /* Bit 9: Source address filter */
+#define ETH_MACFFLT_HPF              (1 << 10) /* Bit 10: Hash or perfect filter */
-                                               /* Bits 10-30: Reserved */
+                                               /* Bits 11-30: Reserved */
 #define ETH_MACFFLT_RA               (1 << 31) /* Bit 31: Receive all */
 
 /* MAC hash table high/low register (32-bit values) */
@@ -208,7 +209,7 @@
 #  define ETH_MACMIIA_CR_100_150     (1 << ETH_MACMIIA_CR_SHIFT)  /* 100-150 MHz CLK_M4_ETHERNET/62 */
 #  define ETH_MACMIIA_CR_20_35       (2 << ETH_MACMIIA_CR_SHIFT)  /* 20-35   MHz CLK_M4_ETHERNET/16 */
 #  define ETH_MACMIIA_CR_35_60       (3 << ETH_MACMIIA_CR_SHIFT)  /* 35-60   MHz CLK_M4_ETHERNET/26 */
-#  define ETH_MACMIIA_CR_150_168     (4 << ETH_MACMIIA_CR_SHIFT)  /* 150-168 MHz CLK_M4_ETHERNET/102 */
+#  define ETH_MACMIIA_CR_150_250     (4 << ETH_MACMIIA_CR_SHIFT)  /* 150-250 MHz CLK_M4_ETHERNET/102 */
 #  define ETH_MACMIIA_CR_250_300     (5 << ETH_MACMIIA_CR_SHIFT)  /* 250-300 MHz CLK_M4_ETHERNET/124 */
 #  define ETH_MACMIIA_CR_DIV42       (8 << ETH_MACMIIA_CR_SHIFT)  /* 60-100  MHz CLK_M4_ETHERNET/42 */
 #  define ETH_MACMIIA_CR_DIV62       (9 << ETH_MACMIIA_CR_SHIFT)  /* 100-150 MHz CLK_M4_ETHERNET/62 */
@@ -314,7 +315,7 @@
                                                /* Bits 4-8: Reserved */
 #define ETH_MACIM_TSIM               (1 << 9)  /* Bit 9: Time stamp interrupt mask */
                                                /* Bits 10-31: Reserved */
-#define ETH_MACIM_ALLINTS            (ETH_MACIM_PMTIM|ETH_MACIM_TSTIM)
+#define ETH_MACIM_ALLINTS            (ETH_MACIM_PMTIM|ETH_MACIM_TSIM)
 
 /* MAC address 0 high register */
 
@@ -499,9 +500,9 @@
 #define ETH_TDES0_CC_MASK            (15 << ETH_TDES0_CC_SHIFT)
 #define ETH_TDES0_VF                 (1 << 7)  /* Bit 7:  VLAN frame */
 #define ETH_TDES0_EC                 (1 << 8)  /* Bit 8:  Excessive collision */
-#define ETH_TDES0_LC                 (1 << 9)  /* Bit 9:  Late collision */
+#define ETH_TDES0_LCL                (1 << 9)  /* Bit 9:  Late collision */
 #define ETH_TDES0_NC                 (1 << 10) /* Bit 10: No carrier */
-#define ETH_TDES0_LC                 (1 << 11) /* Bit 11: Loss of carrier */
+#define ETH_TDES0_LCR                (1 << 11) /* Bit 11: Loss of carrier */
 #define ETH_TDES0_IPE                (1 << 12) /* Bit 12: IP payload error */
 #define ETH_TDES0_FF                 (1 << 13) /* Bit 13: Frame flushed */
 #define ETH_TDES0_JT                 (1 << 14) /* Bit 14: Jabber timeout */
@@ -536,7 +537,7 @@
 
 #define ETH_RDES0_ESA                (1 << 0)  /* Bit 0:  Extended status available */
 #define ETH_RDES0_CE                 (1 << 1)  /* Bit 1:  CRC error */
-#define ETH_RDES0_DE                 (1 << 2)  /* Bit 2:  Dribble bit error */
+#define ETH_RDES0_DRE                (1 << 2)  /* Bit 2:  Dribble bit error */
 #define ETH_RDES0_RE                 (1 << 3)  /* Bit 3:  Receive error */
 #define ETH_RDES0_RWT                (1 << 4)  /* Bit 4:  Receive watchdog timeout */
 #define ETH_RDES0_FT                 (1 << 5)  /* Bit 5:  Frame type */
@@ -548,7 +549,7 @@
 #define ETH_RDES0_OE                 (1 << 11) /* Bit 11: Overflow error */
 #define ETH_RDES0_LE                 (1 << 12) /* Bit 12: Length error */
 #define ETH_RDES0_SAF                (1 << 13) /* Bit 13: Source address filter fail */
-#define ETH_RDES0_DE                 (1 << 14) /* Bit 14: Descriptor error */
+#define ETH_RDES0_DS                 (1 << 14) /* Bit 14: Descriptor error */
 #define ETH_RDES0_ES                 (1 << 15) /* Bit 15: Error summary */
 #define ETH_RDES0_FL_SHIFT           (16)      /* Bits 16-29: Frame length */
 #define ETH_RDES0_FL_MASK            (0x3fff << ETH_RDES0_FL_SHIFT)
@@ -584,12 +585,12 @@
                                                                  * transparent clock) */
 #  define ETH_RDES4_MT_PDELREQMM     (6 << ETH_RDES4_MT_SHIFT)  /* Pdelay_Resp (in peer-to-peer
                                                                  * transparent clock) */
-#  define ETH_RDES4_MT_PDELREQFUS    (7 << ETH_RDES4_MT_SHIFT)  /* Pdelay_Resp_Follow_Up (in
+#  define ETH_RDES4_MT_PDELRESFUS    (7 << ETH_RDES4_MT_SHIFT)  /* Pdelay_Resp_Follow_Up (in
                                                                  * peer-to-peer transparent clock) */
-#  define ETH_RDES4_MT_PDELREQFUS    (8 << ETH_RDES4_MT_SHIFT)  /* Announce */
+#  define ETH_RDES4_MT_ANNOUNCE      (8 << ETH_RDES4_MT_SHIFT)  /* Announce */
-#  define ETH_RDES4_MT_PDELREQFUS    (9 << ETH_RDES4_MT_SHIFT)  /* Management */
+#  define ETH_RDES4_MT_MANAGEMENT    (9 << ETH_RDES4_MT_SHIFT)  /* Management */
-#  define ETH_RDES4_MT_PDELREQFUS    (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
+#  define ETH_RDES4_MT_SIGNALING     (10 << ETH_RDES4_MT_SHIFT) /* Signaling */
-#  define ETH_RDES4_MT_PDELREQFUS    (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
+#  define ETH_RDES4_MT_PTP		     (15 << ETH_RDES4_MT_SHIFT) /* PTP packet with Reserved message type */
 #define ETH_RDES4_PTPTYPE            (1 << 12) /* Bit 12: PTP frame type */
 #define ETH_RDES4_PTPVERSION         (1 << 13) /* Bit 13: PTP version */
                                                /* Bits 14-31:  Reserved */
@@ -662,6 +663,5 @@ extern "C"
 #endif
 
 #endif /* __ASSEMBLY__ */
-#endif /* LPC43_NETHERNET > 0 */
 #endif /* __ARCH_ARM_SRC_LPC43XX_CHIP_LPC43_ETHERNET_H */
 

arch/arm/src/lpc43xx/lpc43_ethernet.h

@@ -0,0 +1,93 @@
+/************************************************************************************
+ * arch/arm/src/lpc43xx/lpc43_eth.h
+ *
+ *   Copyright (C) 2009-2015 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
+#define __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+#include "chip/lpc43_ethernet.h"
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Function: lpc43_phy_boardinitialize
+ *
+ * Description:
+ *   Some boards require specialized initialization of the PHY before it can be used.
+ *   This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+ *   CONFIG_LPC43_PHYINIT is defined in the configuration then the board specific
+ *   logic must provide lpc43_phyinitialize();  The LPC43 Ethernet driver will call
+ *   this function one time before it first uses the PHY.
+ *
+ * Parameters:
+ *   intf - Always zero for now.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_LPC43_PHYINIT
+int lpc43_phy_boardinitialize(int intf);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43_ETH_H */