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Changes from review of last PR. Mostly costmetic.

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This commit is contained in:
Gregory Nutt 2016-06-15 12:43:06 -06:00
parent ff7be7cead
commit a42651de4f
13 changed files with 772 additions and 784 deletions
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19
arch/arm/src/stm32f7/Kconfig
View File

@ -983,6 +983,10 @@ config STM32F7_SPI
bool
default n
config STM32F7_TIM
bool
default n
config STM32F7_USART
bool
default n
@ -1239,62 +1243,77 @@ config STM32F7_SPI6
config STM32F7_TIM1
bool "TIM1"
default n
select STM32F7_TIM
config STM32F7_TIM2
bool "TIM2"
default n
select STM32F7_TIM
config STM32F7_TIM3
bool "TIM3"
default n
select STM32F7_TIM
config STM32F7_TIM4
bool "TIM4"
default n
select STM32F7_TIM
config STM32F7_TIM5
bool "TIM5"
default n
select STM32F7_TIM
config STM32F7_TIM6
bool "TIM6"
default n
select STM32F7_TIM
config STM32F7_TIM7
bool "TIM7"
default n
select STM32F7_TIM
config STM32F7_TIM8
bool "TIM8"
default n
select STM32F7_TIM
config STM32F7_TIM9
bool "TIM9"
default n
select STM32F7_TIM
config STM32F7_TIM10
bool "TIM10"
default n
select STM32F7_TIM
config STM32F7_TIM11
bool "TIM11"
default n
select STM32F7_TIM
config STM32F7_TIM12
bool "TIM12"
default n
select STM32F7_TIM
config STM32F7_TIM13
bool "TIM13"
default n
select STM32F7_TIM
config STM32F7_TIM14
bool "TIM14"
default n
select STM32F7_TIM
config STM32F7_TIM15
bool "TIM15"
default n
select STM32F7_TIM
config STM32F7_USART1
bool "USART1"

18
arch/arm/src/stm32f7/Make.defs
View File

@ -114,7 +114,7 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c stm32_tim.c
CHIP_CSRCS += stm32_start.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += stm32_timerisr.c
@ -139,6 +139,18 @@ ifeq ($(CONFIG_STM32_PWR),y)
CHIP_CSRCS += stm32_exti_pwr.c
endif
ifeq ($(CONFIG_STM32F7_I2C),y)
CHIP_CSRCS += stm32_i2c.c
endif
ifeq ($(CONFIG_STM32F7_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32F7_TIM),y)
CHIP_CSRCS += stm32_tim.c
endif
ifeq ($(CONFIG_ADC),y)
CHIP_CSRCS += stm32_adc.c
endif
@ -149,10 +161,6 @@ CHIP_CSRCS += stm32_exti_alarm.c
endif
endif
ifeq ($(CONFIG_STM32F7_SPI),y)
CHIP_CSRCS += stm32_spi.c
endif
ifeq ($(CONFIG_STM32F7_ETHMAC),y)
CHIP_CSRCS += stm32_ethernet.c
endif

1
arch/arm/src/stm32f7/chip.h
View File

@ -50,7 +50,6 @@
#include <arch/stm32f7/chip.h>
#include "chip/stm32_pinmap.h"
#include "chip/stm32_memorymap.h"
#include "chip/stm32_pinmap.h"
/* If the common ARMv7-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported external

380
arch/arm/src/stm32f7/chip/stm32_adc.h
View File

@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_adc.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -55,26 +55,26 @@
#define STM32_ADC_CR2_OFFSET 0x0008 /* ADC control register 2 (32-bit) */
#define STM32_ADC_SMPR1_OFFSET 0x000c /* ADC sample time register 1 (32-bit) */
#define STM32_ADC_SMPR2_OFFSET 0x0010 /* ADC sample time register 2 (32-bit) */
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
#define STM32_ADC_JOFR1_OFFSET 0x0014 /* ADC injected channel data offset register 1 (32-bit) */
#define STM32_ADC_JOFR2_OFFSET 0x0018 /* ADC injected channel data offset register 2 (32-bit) */
#define STM32_ADC_JOFR3_OFFSET 0x001c /* ADC injected channel data offset register 3 (32-bit) */
#define STM32_ADC_JOFR4_OFFSET 0x0020 /* ADC injected channel data offset register 4 (32-bit) */
#define STM32_ADC_HTR_OFFSET 0x0024 /* ADC watchdog high threshold register (32-bit) */
#define STM32_ADC_LTR_OFFSET 0x0028 /* ADC watchdog low threshold register (32-bit) */
#define STM32_ADC_SQR1_OFFSET 0x002c /* ADC regular sequence register 1 (32-bit) */
#define STM32_ADC_SQR2_OFFSET 0x0030 /* ADC regular sequence register 2 (32-bit) */
#define STM32_ADC_SQR3_OFFSET 0x0034 /* ADC regular sequence register 3 (32-bit) */
#define STM32_ADC_JSQR_OFFSET 0x0038 /* ADC injected sequence register (32-bit) */
#define STM32_ADC_JDR1_OFFSET 0x003c /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR2_OFFSET 0x0040 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR3_OFFSET 0x0044 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_JDR4_OFFSET 0x0048 /* ADC injected data register 1 (32-bit) */
#define STM32_ADC_DR_OFFSET 0x004c /* ADC regular data register (32-bit) */
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */
#define STM32_ADC_CCR_OFFSET 0x0004 /* Common control register */
#define STM32_ADC_CDR_OFFSET 0x0008 /* Data register for dual and triple modes */
/* Register Addresses *******************************************************************************/
@ -147,9 +147,9 @@
# define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET)
#endif
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET)
#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET)
#define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET)
/* Register Bitfield Definitions ********************************************************************/
@ -160,7 +160,7 @@
#define ADC_SR_JEOC (1 << 2) /* Bit 2 : Injected channel end of conversion */
#define ADC_SR_JSTRT (1 << 3) /* Bit 3 : Injected channel Start flag */
#define ADC_SR_STRT (1 << 4) /* Bit 4 : Regular channel Start flag */
#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
#define ADC_SR_OVR (1 << 5) /* Bit 5 : Overrun */
/* ADC control register 1 */
@ -183,13 +183,13 @@
#define ADC_CR1_JAWDEN (1 << 22) /* Bit 22: Analog watchdog enable on injected channels */
#define ADC_CR1_AWDEN (1 << 23) /* Bit 23: Analog watchdog enable on regular channels */
#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
#define ADC_CR1_RES_SHIFT (24) /* Bits 24-25: Resolution */
#define ADC_CR1_RES_MASK (3 << ADC_CR1_RES_SHIFT)
#define ADC_CR1_RES_12BIT (0 << ADC_CR1_RES_SHIFT) /* 15 ADCCLK cycles. For STM32L15XX: 12 ADCCLK cycles */
#define ADC_CR1_RES_10BIT (1 << ADC_CR1_RES_SHIFT) /* 13 ADCCLK cycles. For STM32L15XX: 11 ADCCLK cycles */
#define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
#define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
#define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
/* ADC control register 2 */
@ -204,114 +204,114 @@
#define ADC_CR2_ALIGN (1 << 11) /* Bit 11: Data Alignment */
/* Bits 12-15: Reserved */
#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
/* 0110: NA */
#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
#define ADC_CR2_JEXTSEL_T3CC3 (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
#define ADC_CR2_JEXTSEL_T5TRGO (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
#define ADC_CR2_JEXTSEL_T3CC1 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
#define ADC_CR2_JEXTSEL_T6TRGO (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
/* 1111: NA */
#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
#define ADC_CR2_JEXTSEL_SHIFT (16) /* Bits 16-19: External event select for injected group */
#define ADC_CR2_JEXTSEL_MASK (0x0F << ADC_CR2_JEXTSEL_SHIFT)
#define ADC_CR2_JEXTSEL_T1TRGO (0x00 << ADC_CR2_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */
#define ADC_CR2_JEXTSEL_T1CC4 (0x01 << ADC_CR2_JEXTSEL_SHIFT) /* 0001: Timer 1 CC4 event */
#define ADC_CR2_JEXTSEL_T2TRGO (0x02 << ADC_CR2_JEXTSEL_SHIFT) /* 0010: Timer 2 TRGO event */
#define ADC_CR2_JEXTSEL_T2CC1 (0x03 << ADC_CR2_JEXTSEL_SHIFT) /* 0011: Timer 2 CC1 event */
#define ADC_CR2_JEXTSEL_T3CC4 (0x04 << ADC_CR2_JEXTSEL_SHIFT) /* 0100: Timer 3 CC4 event */
#define ADC_CR2_JEXTSEL_T4TRGO (0x05 << ADC_CR2_JEXTSEL_SHIFT) /* 0101: Timer 4 TRGO event */
/* 0110: NA */
#define ADC_CR2_JEXTSEL_T8CC4 (0x07 << ADC_CR2_JEXTSEL_SHIFT) /* 0111: Timer 8 CC4 event */
#define ADC_CR2_JEXTSEL_T1TRGO2 (0x08 << ADC_CR2_JEXTSEL_SHIFT) /* 1000: Timer 1 TRGO2 event */
#define ADC_CR2_JEXTSEL_T8TRGO (0x09 << ADC_CR2_JEXTSEL_SHIFT) /* 1001: Timer 8 TRGO event */
#define ADC_CR2_JEXTSEL_T8TRGO2 (0x0A << ADC_CR2_JEXTSEL_SHIFT) /* 1010: Timer 8 TRGO2 event */
#define ADC_CR2_JEXTSEL_T3CC3 (0x0B << ADC_CR2_JEXTSEL_SHIFT) /* 1011: Timer 3 CC3 event */
#define ADC_CR2_JEXTSEL_T5TRGO (0x0C << ADC_CR2_JEXTSEL_SHIFT) /* 1100: Timer 5 TRGO event */
#define ADC_CR2_JEXTSEL_T3CC1 (0x0D << ADC_CR2_JEXTSEL_SHIFT) /* 1101: Timer 3 CC1 event */
#define ADC_CR2_JEXTSEL_T6TRGO (0x0E << ADC_CR2_JEXTSEL_SHIFT) /* 1110: Timer 6 TRGO event */
/* 1111: NA */
#define ADC_CR2_JEXTEN_SHIFT (20) /* Bits 20-21: External trigger enable for injected channels */
#define ADC_CR2_JEXTEN_MASK (3 << ADC_CR2_JEXTEN_SHIFT)
#define ADC_CR2_JEXTEN_NONE (0 << ADC_CR2_JEXTEN_SHIFT) /* 00: Trigger detection disabled */
#define ADC_CR2_JEXTEN_RISING (1 << ADC_CR2_JEXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
#define ADC_CR2_JEXTEN_FALLING (2 << ADC_CR2_JEXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
#define ADC_CR2_JEXTEN_BOTH (3 << ADC_CR2_JEXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
#define ADC_CR2_JSWSTART (1 << 22) /* Bit 22: Start Conversion of injected channels */
/* Bit 23: Reserved, must be kept at reset value. */
#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
#define ADC_CR2_EXTSEL_T1TRGO2 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
#define ADC_CR2_EXTSEL_T2TRGO (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
#define ADC_CR2_EXTSEL_T4TRGO (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
#define ADC_CR2_EXTSEL_T6TRGO (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
/* 1110: NA */
#define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
#define ADC_CR2_EXTSEL_SHIFT (24) /* Bits 24-27: External Event Select for regular group */
#define ADC_CR2_EXTSEL_MASK (0x0F << ADC_CR2_EXTSEL_SHIFT)
#define ADC_CR2_EXTSEL_T1CC1 (0x0 << ADC_CR2_EXTSEL_SHIFT) /* 0000: Timer 1 CC1 event */
#define ADC_CR2_EXTSEL_T1CC2 (0x01 << ADC_CR2_EXTSEL_SHIFT) /* 0001: Timer 1 CC2 event */
#define ADC_CR2_EXTSEL_T1CC3 (0x02 << ADC_CR2_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */
#define ADC_CR2_EXTSEL_T2CC2 (0x03 << ADC_CR2_EXTSEL_SHIFT) /* 0011: Timer 2 CC2 event */
#define ADC_CR2_EXTSEL_T5TRGO (0x04 << ADC_CR2_EXTSEL_SHIFT) /* 0100: Timer 5 TRGO event */
#define ADC_CR2_EXTSEL_T4CC4 (0x05 << ADC_CR2_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */
#define ADC_CR2_EXTSEL_T3CC4 (0x06 << ADC_CR2_EXTSEL_SHIFT) /* 0110: Timer 3 CC4 event */
#define ADC_CR2_EXTSEL_T8TRGO (0x07 << ADC_CR2_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */
#define ADC_CR2_EXTSEL_T8TRGO2 (0x08 << ADC_CR2_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */
#define ADC_CR2_EXTSEL_T1TRGO (0x09 << ADC_CR2_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */
#define ADC_CR2_EXTSEL_T1TRGO2 (0x0A << ADC_CR2_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */
#define ADC_CR2_EXTSEL_T2TRGO (0x0B << ADC_CR2_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */
#define ADC_CR2_EXTSEL_T4TRGO (0x0C << ADC_CR2_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */
#define ADC_CR2_EXTSEL_T6TRGO (0x0D << ADC_CR2_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */
/* 1110: NA */
#define ADC_CR2_EXTSEL_EXTI11 (0x0F << ADC_CR2_EXTSEL_SHIFT) /* 1111: EXTI line 11 */
#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
#define ADC_CR2_EXTEN_SHIFT (28) /* Bits 28-29: External trigger enable for regular channels */
#define ADC_CR2_EXTEN_MASK (3 << ADC_CR2_EXTEN_SHIFT)
#define ADC_CR2_EXTEN_NONE (0 << ADC_CR2_EXTEN_SHIFT) /* 00: Trigger detection disabled */
#define ADC_CR2_EXTEN_RISING (1 << ADC_CR2_EXTEN_SHIFT) /* 01: Trigger detection on the rising edge */
#define ADC_CR2_EXTEN_FALLING (2 << ADC_CR2_EXTEN_SHIFT) /* 10: Trigger detection on the falling edge */
#define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
/* ADC sample time register 1 */
#define ADC_SMPR_3 0 /* 000: 3 cycles */
#define ADC_SMPR_15 1 /* 001: 15 cycles */
#define ADC_SMPR_28 2 /* 010: 28 cycles */
#define ADC_SMPR_56 3 /* 011: 56 cycles */
#define ADC_SMPR_84 4 /* 100: 84 cycles */
#define ADC_SMPR_112 5 /* 101: 112 cycles */
#define ADC_SMPR_144 6 /* 110: 144 cycles */
#define ADC_SMPR_480 7 /* 111: 480 cycles */
#define ADC_SMPR_3 0 /* 000: 3 cycles */
#define ADC_SMPR_15 1 /* 001: 15 cycles */
#define ADC_SMPR_28 2 /* 010: 28 cycles */
#define ADC_SMPR_56 3 /* 011: 56 cycles */
#define ADC_SMPR_84 4 /* 100: 84 cycles */
#define ADC_SMPR_112 5 /* 101: 112 cycles */
#define ADC_SMPR_144 6 /* 110: 144 cycles */
#define ADC_SMPR_480 7 /* 111: 480 cycles */
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP10_SHIFT (0) /* Bits 0-2: Channel 10 Sample time selection */
#define ADC_SMPR1_SMP10_MASK (7 << ADC_SMPR1_SMP10_SHIFT)
#define ADC_SMPR1_SMP11_SHIFT (3) /* Bits 3-5: Channel 11 Sample time selection */
#define ADC_SMPR1_SMP11_MASK (7 << ADC_SMPR1_SMP11_SHIFT)
#define ADC_SMPR1_SMP12_SHIFT (6) /* Bits 6-8: Channel 12 Sample time selection */
#define ADC_SMPR1_SMP12_MASK (7 << ADC_SMPR1_SMP12_SHIFT)
#define ADC_SMPR1_SMP13_SHIFT (9) /* Bits 9-11: Channel 13 Sample time selection */
#define ADC_SMPR1_SMP13_MASK (7 << ADC_SMPR1_SMP13_SHIFT)
#define ADC_SMPR1_SMP14_SHIFT (12) /* Bits 12-14: Channel 14 Sample time selection */
#define ADC_SMPR1_SMP14_MASK (7 << ADC_SMPR1_SMP14_SHIFT)
#define ADC_SMPR1_SMP15_SHIFT (15) /* Bits 15-17: Channel 15 Sample time selection */
#define ADC_SMPR1_SMP15_MASK (7 << ADC_SMPR1_SMP15_SHIFT)
#define ADC_SMPR1_SMP16_SHIFT (18) /* Bits 18-20: Channel 16 Sample time selection */
#define ADC_SMPR1_SMP16_MASK (7 << ADC_SMPR1_SMP16_SHIFT)
#define ADC_SMPR1_SMP17_SHIFT (21) /* Bits 21-23: Channel 17 Sample time selection */
#define ADC_SMPR1_SMP17_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
#define ADC_SMPR1_SMP18_SHIFT (21) /* Bits 24-26: Channel 18 Sample time selection */
#define ADC_SMPR1_SMP18_MASK (7 << ADC_SMPR1_SMP17_SHIFT)
/* ADC sample time register 2 */
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
#define ADC_SMPR2_SMP0_SHIFT (0) /* Bits 2-0: Channel 0 Sample time selection */
#define ADC_SMPR2_SMP0_MASK (7 << ADC_SMPR2_SMP0_SHIFT)
#define ADC_SMPR2_SMP1_SHIFT (3) /* Bits 5-3: Channel 1 Sample time selection */
#define ADC_SMPR2_SMP1_MASK (7 << ADC_SMPR2_SMP1_SHIFT)
#define ADC_SMPR2_SMP2_SHIFT (6) /* Bits 8-6: Channel 2 Sample time selection */
#define ADC_SMPR2_SMP2_MASK (7 << ADC_SMPR2_SMP2_SHIFT)
#define ADC_SMPR2_SMP3_SHIFT (9) /* Bits 11-9: Channel 3 Sample time selection */
#define ADC_SMPR2_SMP3_MASK (7 << ADC_SMPR2_SMP3_SHIFT)
#define ADC_SMPR2_SMP4_SHIFT (12) /* Bits 14-12: Channel 4 Sample time selection */
#define ADC_SMPR2_SMP4_MASK (7 << ADC_SMPR2_SMP4_SHIFT)
#define ADC_SMPR2_SMP5_SHIFT (15) /* Bits 17-15: Channel 5 Sample time selection */
#define ADC_SMPR2_SMP5_MASK (7 << ADC_SMPR2_SMP5_SHIFT)
#define ADC_SMPR2_SMP6_SHIFT (18) /* Bits 20-18: Channel 6 Sample time selection */
#define ADC_SMPR2_SMP6_MASK (7 << ADC_SMPR2_SMP6_SHIFT)
#define ADC_SMPR2_SMP7_SHIFT (21) /* Bits 23-21: Channel 7 Sample time selection */
#define ADC_SMPR2_SMP7_MASK (7 << ADC_SMPR2_SMP7_SHIFT)
#define ADC_SMPR2_SMP8_SHIFT (24) /* Bits 26-24: Channel 8 Sample time selection */
#define ADC_SMPR2_SMP8_MASK (7 << ADC_SMPR2_SMP8_SHIFT)
#define ADC_SMPR2_SMP9_SHIFT (27) /* Bits 29-27: Channel 9 Sample time selection */
#define ADC_SMPR2_SMP9_MASK (7 << ADC_SMPR2_SMP9_SHIFT)
/* ADC injected channel data offset register 1-4 */
@ -331,58 +331,58 @@
/* ADC regular sequence register 1 */
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
#define ADC_SQR1_RESERVED (0xff000000)
#define ADC_SQR1_FIRST (13)
#define ADC_SQR1_LAST (16)
#define ADC_SQR1_SQ_OFFSET (0)
#define ADC_SQR1_SQ13_SHIFT (0) /* Bits 4-0: 13th conversion in regular sequence */
#define ADC_SQR1_SQ13_MASK (0x1f << ADC_SQR1_SQ13_SHIFT)
#define ADC_SQR1_SQ14_SHIFT (5) /* Bits 9-5: 14th conversion in regular sequence */
#define ADC_SQR1_SQ14_MASK (0x1f << ADC_SQR1_SQ14_SHIFT)
#define ADC_SQR1_SQ15_SHIFT (10) /* Bits 14-10: 15th conversion in regular sequence */
#define ADC_SQR1_SQ15_MASK (0x1f << ADC_SQR1_SQ15_SHIFT)
#define ADC_SQR1_SQ16_SHIFT (15) /* Bits 19-15: 16th conversion in regular sequence */
#define ADC_SQR1_SQ16_MASK (0x1f << ADC_SQR1_SQ16_SHIFT)
#define ADC_SQR1_L_SHIFT (20) /* Bits 23-20: Regular channel sequence length */
#define ADC_SQR1_L_MASK (0x0f << ADC_SQR1_L_SHIFT)
#define ADC_SQR1_RESERVED (0xff000000)
#define ADC_SQR1_FIRST (13)
#define ADC_SQR1_LAST (16)
#define ADC_SQR1_SQ_OFFSET (0)
/* ADC regular sequence register 2 */
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
#define ADC_SQR2_RESERVED (0xc0000000)
#define ADC_SQR2_FIRST (7)
#define ADC_SQR2_LAST (12)
#define ADC_SQR2_SQ_OFFSET (0)
#define ADC_SQR2_SQ7_SHIFT (0) /* Bits 4-0: 7th conversion in regular sequence */
#define ADC_SQR2_SQ7_MASK (0x1f << ADC_SQR2_SQ7_SHIFT)
#define ADC_SQR2_SQ8_SHIFT (5) /* Bits 9-5: 8th conversion in regular sequence */
#define ADC_SQR2_SQ8_MASK (0x1f << ADC_SQR2_SQ8_SHIFT)
#define ADC_SQR2_SQ9_SHIFT (10) /* Bits 14-10: 9th conversion in regular sequence */
#define ADC_SQR2_SQ9_MASK (0x1f << ADC_SQR2_SQ9_SHIFT)
#define ADC_SQR2_SQ10_SHIFT (15) /* Bits 19-15: 10th conversion in regular sequence */
#define ADC_SQR2_SQ10_MASK (0x1f << ADC_SQR2_SQ10_SHIFT)
#define ADC_SQR2_SQ11_SHIFT (20) /* Bits 24-20: 11th conversion in regular sequence */
#define ADC_SQR2_SQ11_MASK (0x1f << ADC_SQR2_SQ11_SHIFT )
#define ADC_SQR2_SQ12_SHIFT (25) /* Bits 29-25: 12th conversion in regular sequence */
#define ADC_SQR2_SQ12_MASK (0x1f << ADC_SQR2_SQ12_SHIFT)
#define ADC_SQR2_RESERVED (0xc0000000)
#define ADC_SQR2_FIRST (7)
#define ADC_SQR2_LAST (12)
#define ADC_SQR2_SQ_OFFSET (0)
/* ADC regular sequence register 3 */
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
#define ADC_SQR3_RESERVED (0xc0000000)
#define ADC_SQR3_FIRST (1)
#define ADC_SQR3_LAST (6)
#define ADC_SQR3_SQ_OFFSET (0)
#define ADC_SQR3_SQ1_SHIFT (0) /* Bits 4-0: 1st conversion in regular sequence */
#define ADC_SQR3_SQ1_MASK (0x1f << ADC_SQR3_SQ1_SHIFT)
#define ADC_SQR3_SQ2_SHIFT (5) /* Bits 9-5: 2nd conversion in regular sequence */
#define ADC_SQR3_SQ2_MASK (0x1f << ADC_SQR3_SQ2_SHIFT)
#define ADC_SQR3_SQ3_SHIFT (10) /* Bits 14-10: 3rd conversion in regular sequence */
#define ADC_SQR3_SQ3_MASK (0x1f << ADC_SQR3_SQ3_SHIFT)
#define ADC_SQR3_SQ4_SHIFT (15) /* Bits 19-15: 4th conversion in regular sequence */
#define ADC_SQR3_SQ4_MASK (0x1f << ADC_SQR3_SQ4_SHIFT)
#define ADC_SQR3_SQ5_SHIFT (20) /* Bits 24-20: 5th conversion in regular sequence */
#define ADC_SQR3_SQ5_MASK (0x1f << ADC_SQR3_SQ5_SHIFT )
#define ADC_SQR3_SQ6_SHIFT (25) /* Bits 29-25: 6th conversion in regular sequence */
#define ADC_SQR3_SQ6_MASK (0x1f << ADC_SQR3_SQ6_SHIFT)
#define ADC_SQR3_RESERVED (0xc0000000)
#define ADC_SQR3_FIRST (1)
#define ADC_SQR3_LAST (6)
#define ADC_SQR3_SQ_OFFSET (0)
/* Offset between SQ bits */
@ -413,26 +413,26 @@
/* Common status register */
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
#define ADC_CSR_AWD1 (1 << 0) /* Bit 0: Analog watchdog flag of ADC1 (copy of AWD in ADC1_SR) */
#define ADC_CSR_EOC1 (1 << 1) /* Bit 1: End of conversion of ADC1 (copy of EOC in ADC1_SR) */
#define ADC_CSR_JEOC1 (1 << 2) /* Bit 2: Injected channel end of conversion of ADC1 (copy of JEOC in ADC1_SR) */
#define ADC_CSR_JSTRT1 (1 << 3) /* Bit 3: Injected channel Start flag of ADC1 (copy of JSTRT in ADC1_SR) */
#define ADC_CSR_STRT1 (1 << 4) /* Bit 4: Regular channel Start flag of ADC1 (copy of STRT in ADC1_SR) */
#define ADC_CSR_OVR1 (1 << 5) /* Bit 5: Overrun flag of ADC1 (copy of OVR in ADC1_SR) */
#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
# /* Bits 14-15: Reserved, must be kept at reset value. */
#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
#define ADC_CSR_AWD2 (1 << 8) /* Bit 8: Analog watchdog flag of ADC2 (copy of AWD in ADC2_SR) */
#define ADC_CSR_EOC2 (1 << 9) /* Bit 9: End of conversion of ADC2 (copy of EOC in ADC2_SR) */
#define ADC_CSR_JEOC2 (1 << 10) /* Bit 10: Injected channel end of conversion of ADC2 (copy of JEOC in ADC2_SR) */
#define ADC_CSR_JSTRT2 (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
#define ADC_CSR_STRT2 (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
#define ADC_CSR_OVR2 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
/* Bits 14-15: Reserved, must be kept at reset value. */
#define ADC_CSR_AWD3 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
#define ADC_CSR_EOC3 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
#define ADC_CSR_JEOC3 (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */
#define ADC_CSR_JSTRT3 (1 << 19) /* Bit 19: ADC3 Injected channel Start flag (copy of JSTRT in ADC3_SR) */
#define ADC_CSR_STRT3 (1 << 20) /* Bit 20: ADC3 Regular channel Start flag (copy of STRT in ADC3_SR). */
#define ADC_CSR_OVR3 (1 << 21) /* Bit 21: ADC3 overrun flag (copy of OVR in ADC3_SR). */
/* Common control register */

2
arch/arm/src/stm32f7/chip/stm32_i2c.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_i2c.h
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without

8
arch/arm/src/stm32f7/chip/stm32_tim.h
View File

@ -1,7 +1,7 @@
/****************************************************************************************************
* arch/arm/src/stm32f7/chip/stm32_tim.h
*
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -712,10 +712,10 @@
/* Repetition counter register */
#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */
#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
#define ATIM_RCR_REP_SHIFT (0) /* Bits 0-7: Repetition Counter Value */
#define ATIM_RCR_REP_MASK (0xff << ATIM_RCR_REP_SHIFT)
#define ATIM_RCR_REP_MAX 128
#define ATIM_RCR_REP_MAX 128
/* Capture/compare registers (CCR) */

204
arch/arm/src/stm32f7/chip/stm32f74xx75xx_i2c.h
View File

@ -102,131 +102,131 @@
/* Control register 1 */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
#define I2C_CR1_PE (1 << 0) /* Bit 0: Peripheral Enable */
#define I2C_CR1_TXIE (1 << 1) /* Bit 1: TX Interrupt enable */
#define I2C_CR1_RXIE (1 << 2) /* Bit 2: RX Interrupt enable */
#define I2C_CR1_ADDRIE (1 << 3) /* Bit 3: Address match interrupt enable (slave) */
#define I2C_CR1_NACKIE (1 << 4) /* Bit 4: Not acknowledge received interrupt enable */
#define I2C_CR1_STOPIE (1 << 5) /* Bit 5: STOP detection interrupt enable */
#define I2C_CR1_TCIE (1 << 6) /* Bit 6: Transfer Complete interrupt enable */
#define I2C_CR1_ERRIE (1 << 7) /* Bit 7: Error interrupts enable */
#define I2C_CR1_DNF_SHIFT (8) /* Bits 8-11: Digital noise filter */
#define I2C_CR1_DNF_MASK (15 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF_DISABLE (0 << I2C_CR1_DNF_SHIFT)
# define I2C_CR1_DNF(n) ((n) << I2C_CR1_DNF_SHIFT) /* Up to n * Ti2cclk, n=1..15 */
#define I2C_CR1_ANFOFF (1 << 12) /* Bit 12: Analog noise filter OFF */
#define I2C_CR1_TXDMAEN (1 << 14) /* Bit 14: DMA transmission requests enable */
#define I2C_CR1_RXDMAEN (1 << 15) /* Bit 15: DMA reception requests enable */
#define I2C_CR1_SBC (1 << 16) /* Bit 16: Slave byte control */
#define I2C_CR1_NOSTRETCH (1 << 17) /* Bit 17: Clock stretching disable */
#define I2C_CR1_WUPEN (1 << 18) /* Bit 18: Wakeup from STOP enable */
#define I2C_CR1_GCEN (1 << 19) /* Bit 19: General call enable */
#define I2C_CR1_SMBHEN (1 << 20) /* Bit 20: SMBus Host address enable */
#define I2C_CR1_SMBDEN (1 << 21) /* Bit 21: SMBus Device Default address enable */
#define I2C_CR1_ALERTEN (1 << 22) /* Bit 22: SMBus alert enable */
#define I2C_CR1_PECEN (1 << 23) /* Bit 23: PEC enable */
/* Control register 2 */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
#define I2C_CR2_SADD10_SHIFT (0) /* Bits 0-9: Slave 10-bit address (master) */
#define I2C_CR2_SADD10_MASK (0x3ff << I2C_CR2_SADD10_SHIFT)
#define I2C_CR2_SADD7_SHIFT (1) /* Bits 1-7: Slave 7-bit address (master) */
#define I2C_CR2_SADD7_MASK (0x7f << I2C_CR2_SADD7_SHIFT)
#define I2C_CR2_RD_WRN (1 << 10) /* Bit 10: Transfer direction (master) */
#define I2C_CR2_ADD10 (1 << 11) /* Bit 11: 10-bit addressing mode (master) */
#define I2C_CR2_HEAD10R (1 << 12) /* Bit 12: 10-bit address header only read direction (master) */
#define I2C_CR2_START (1 << 13) /* Bit 13: Start generation */
#define I2C_CR2_STOP (1 << 14) /* Bit 14: Stop generation (master) */
#define I2C_CR2_NACK (1 << 15) /* Bit 15: NACK generation (slave) */
#define I2C_CR2_NBYTES_SHIFT (16) /* Bits 16-23: Number of bytes */
#define I2C_CR2_NBYTES_MASK (0xff << I2C_CR2_NBYTES_SHIFT)
#define I2C_CR2_RELOAD (1 << 24) /* Bit 24: NBYTES reload mode */
#define I2C_CR2_AUTOEND (1 << 25) /* Bit 25: Automatic end mode (master) */
#define I2C_CR2_PECBYTE (1 << 26) /* Bit 26: Packet error checking byte */
/* Own address register 1 */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
#define I2C_OAR1_OA1_10_SHIFT (0) /* Bits 0-9: 10-bit interface address */
#define I2C_OAR1_OA1_10_MASK (0x3ff << I2C_OAR1_OA1_10_SHIFT)
#define I2C_OAR1_OA1_7_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR1_OA1_7_MASK (0x7f << I2C_OAR1_OA1_7_SHIFT)
#define I2C_OAR1_OA1MODE (1 << 10) /* Bit 10: Own Address 1 10-bit mode */
#define I2C_OAR1_OA1EN (1 << 15) /* Bit 15: Own Address 1 enable */
/* Own address register 2 */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
#define I2C_OAR2_OA2_SHIFT (1) /* Bits 1-7: 7-bit interface address */
#define I2C_OAR2_OA2_MASK (0x7f << I2C_OAR2_OA2_SHIFT)
#define I2C_OAR2_OA2MSK_SHIFT (8) /* Bits 8-10: Own Address 2 masks */
#define I2C_OAR2_OA2MSK_MASK (7 << I2C_OAR2_OA2MSK_SHIFT)
# define I2C_OAR2_OA2MSK_NONE (0 << I2C_OAR2_OA2MSK_SHIFT) /* No mask */
# define I2C_OAR2_OA2MSK_2_7 (1 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:2] are compared */
# define I2C_OAR2_OA2MSK_3_7 (2 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:3] are compared */
# define I2C_OAR2_OA2MSK_4_7 (3 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:4] are compared */
# define I2C_OAR2_OA2MSK_5_7 (4 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:5] are compared */
# define I2C_OAR2_OA2MSK_6_7 (5 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7:6] are compared */
# define I2C_OAR2_OA2MSK_7 (6 << I2C_OAR2_OA2MSK_SHIFT) /* Only OA2[7] is compared */
# define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) /* All 7-bit addresses acknowledged */
#define I2C_OAR2_OA2EN (1 << 15) /* Bit 15: Own Address 2 enable */
/* Timing register */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLL_SHIFT (0) /* Bits 0-7: SCL low period (master) */
#define I2C_TIMINGR_SCLL_MASK (0xff << I2C_TIMINGR_SCLL_SHIFT)
# define I2C_TIMINGR_SCLL(n) (((n)-1) << I2C_TIMINGR_SCLL_SHIFT) /* tSCLL = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SCLH_SHIFT (8) /* Bits 8-15: SCL high period (master) */
#define I2C_TIMINGR_SCLH_MASK (0xff << I2C_TIMINGR_SCLH_SHIFT)
# define I2C_TIMINGR_SCLH(n) (((n)-1) << I2C_TIMINGR_SCLH_SHIFT) /* tSCLH = n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SDADEL_SHIFT (16) /* Bits 16-19: Data hold time */
#define I2C_TIMINGR_SDADEL_MASK (15 << I2C_TIMINGR_SDADEL_SHIFT)
# define I2C_TIMINGR_SDADEL(n) ((n) << I2C_TIMINGR_SDADEL_SHIFT) /* tSDADEL= n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_SCLDEL_SHIFT (20) /* Bits 20-23: Data setup time */
#define I2C_TIMINGR_SCLDEL_MASK (15 << I2C_TIMINGR_SCLDEL_SHIFT)
# define I2C_TIMINGR_SCLDEL(n) (((n)-1) << I2C_TIMINGR_SCLDEL_SHIFT) /* tSCLDEL = n x tPRESC */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
#define I2C_TIMINGR_PRESC_SHIFT (28) /* Bits 28-31: Timing prescaler */
#define I2C_TIMINGR_PRESC_MASK (15 << I2C_TIMINGR_PRESC_SHIFT)
# define I2C_TIMINGR_PRESC(n) (((n)-1) << I2C_TIMINGR_PRESC_SHIFT) /* tPRESC = n x tI2CCLK */
/* Timeout register */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
#define I2C_TIMEOUTR_A_SHIFT (0) /* Bits 0-11: Bus Timeout A */
#define I2C_TIMEOUTR_A_MASK (0x0fff << I2C_TIMEOUTR_A_SHIFT)
# define I2C_TIMEOUTR_A(n) ((n) << I2C_TIMEOUTR_A_SHIFT)
#define I2C_TIMEOUTR_TIDLE (1 << 12) /* Bit 12: Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) /* Bit 15: Clock timeout enable */
#define I2C_TIMEOUTR_B_SHIFT (16) /* Bits 16-27: Bus Timeout B */
#define I2C_TIMEOUTR_B_MASK (0x0fff << I2C_TIMEOUTR_B_SHIFT)
# define I2C_TIMEOUTR_B(n) ((n) << I2C_TIMEOUTR_B_SHIFT)
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */
#define I2C_INT_NACK (1 << 4) /* Bit 4: Not Acknowledge received flag */
#define I2C_INT_STOP (1 << 5) /* Bit 5: Stop detection flag */
#define I2C_INT_BERR (1 << 8) /* Bit 8: Bus error */
#define I2C_INT_ARLO (1 << 9) /* Bit 9: Arbitration lost */
#define I2C_INT_OVR (1 << 10) /* Bit 10: Overrun/Underrun (slave) */
#define I2C_INT_PECERR (1 << 11) /* Bit 11: PEC Error in reception */
#define I2C_INT_TIMEOUT (1 << 12) /* Bit 12: Timeout or tLOW detection flag */
#define I2C_INT_ALERT (1 << 13) /* Bit 13: SMBus alert */
/* Fields unique to the Interrupt and Status register */
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_TXE (1 << 0) /* Bit 0: Transmit data register empty (transmitters) */
#define I2C_ISR_TXIS (1 << 1) /* Bit 1: Transmit interrupt status (transmitters) */
#define I2C_ISR_RXNE (1 << 2) /* Bit 2: Receive data register not empty (receivers) */
#define I2C_ISR_TC (1 << 6) /* Bit 6: Transfer Complete (master) */
#define I2C_ISR_TCR (1 << 7) /* Bit 7: Transfer Complete Reload */
#define I2C_ISR_BUSY (1 << 15) /* Bit 15: Bus busy */
#define I2C_ISR_DIR (1 << 16) /* Bit 16: Transfer direction (slave) */
#define I2C_ISR_ADDCODE_SHIFT (17) /* Bits 17-23: Address match code (slave) */
#define I2C_ISR_ADDCODE_MASK (0x7f << I2C_ISR_ADDCODE_SHIFT)
#define I2C_ISR_ERRORMASK (I2C_INT_BERR | I2C_INT_ARLO | I2C_INT_OVR | I2C_INT_PECERR | I2C_INT_TIMEOUT)
@ -235,15 +235,15 @@
/* Packet error checking register */
#define I2C_PECR_MASK (0xff)
#define I2C_PECR_MASK (0xff)
/* Receive data register */
#define I2C_RXDR_MASK (0xff)
#define I2C_RXDR_MASK (0xff)
/* Transmit data register */
#define I2C_TXDR_MASK (0xff)
#define I2C_TXDR_MASK (0xff)
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_I2C_H */

156
arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -49,17 +49,17 @@
/* Maximum allowed speed as per specifications for all SPIs */
#define STM32F7_SPI_CLK_MAX 27000000UL
#define STM32F7_SPI_CLK_MAX 27000000UL
/* Register Offsets *****************************************************************/
#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
#define STM32F7_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
#define STM32F7_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
#define STM32F7_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
#define STM32F7_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
#define STM32F7_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
#define STM32F7_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
#define STM32F7_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
/* Register Addresses ***************************************************************/
@ -127,81 +127,81 @@
/* SPI Control Register 1 */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
/* SPI Control Register 2 */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_VAL(bits) ( ((bits)-1) << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
#define SPI_CR2_NSSP (1 << 3) /* Bit 3: NSS pulse management */
#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
#define SPI_CR2_DS_MASK (15 << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_VAL(bits) (((uint32_t)(bits)-1) << SPI_CR2_DS_SHIFT)
# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL( 4)
# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL( 5)
# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL( 6)
# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL( 7)
# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL( 8)
# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL( 9)
# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
/* SPI status register */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
#define SPI_SR_FRLVL_MASK (3 << SPI_SR_FRLVL_SHIFT)
# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
#define SPI_SR_FTLVL_MASK (3 << SPI_SR_FTLVL_SHIFT)
# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SPI_H */

16
arch/arm/src/stm32f7/stm32_adc.c
View File

@ -103,11 +103,11 @@
#define ADC_IER_AWD ADC_CR1_AWDIE
#define ADC_ISR_JEOC ADC_SR_JEOC
#define ADC_IER_JEOC ADC_CR1_JEOCIE
#define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK
#define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE
#define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING
#define ADC_ISR_OVR ADC_SR_OVR
#define ADC_IER_OVR ADC_CR1_OVRIE
#define ADC_EXTREG_EXTEN_MASK ADC_CR2_EXTEN_MASK
#define ADC_EXTREG_EXTEN_NONE ADC_CR2_EXTEN_NONE
#define ADC_EXTREG_EXTEN_DEFAULT ADC_CR2_EXTEN_RISING
#define ADC_ISR_OVR ADC_SR_OVR
#define ADC_IER_OVR ADC_CR1_OVRIE
#define ADC_ISR_ALLINTS (ADC_ISR_EOC | ADC_ISR_AWD | ADC_ISR_JEOC | \
ADC_ISR_OVR)
@ -1622,7 +1622,7 @@ static int adc123_interrupt(int irq, FAR void *context)
****************************************************************************/
/****************************************************************************
* Name: stm32_adcinitialize
* Name: stm32_adc_initialize
*
* Description:
* Initialize the ADC.
@ -1647,8 +1647,8 @@ static int adc123_interrupt(int irq, FAR void *context)
*
****************************************************************************/
struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
int cchannels)
struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist,
int cchannels)
{
FAR struct adc_dev_s *dev;
FAR struct stm32_dev_s *priv;

233
arch/arm/src/stm32f7/stm32_adc.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_adc.h
*
* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
@ -294,124 +294,123 @@
*
*/
# define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
# define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
# define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
# define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
# define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
# define ADC1_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
# define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
# define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
# define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
# define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
# define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
# define ADC2_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
# define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
# define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
# define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
# define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
# define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
# define ADC3_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
#define ADC1_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
#define ADC1_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
#define ADC1_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
#define ADC1_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
#define ADC1_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
#define ADC1_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
#define ADC2_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
#define ADC2_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
#define ADC2_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
#define ADC2_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
#define ADC2_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
#define ADC2_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
#define ADC3_EXTSEL_T1CC1 ADC_CR2_EXTSEL_T1CC1
#define ADC3_EXTSEL_T1CC2 ADC_CR2_EXTSEL_T1CC2
#define ADC3_EXTSEL_T1CC3 ADC_CR2_EXTSEL_T1CC3
#define ADC3_EXTSEL_T1CC4 ADC_CR2_EXTSEL_T1CC4
#define ADC3_EXTSEL_T1TRGO ADC_CR2_EXTSEL_T1TRGO
#define ADC3_EXTSEL_T1TRGO2 ADC_CR2_EXTSEL_T1TRGO2
# define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
# define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
# define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
# define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
# define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
# define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
# define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
# define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
# define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
# define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
# define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
# define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
# define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
# define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
# define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
#define ADC1_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
#define ADC1_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
#define ADC1_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
#define ADC1_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
#define ADC1_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
#define ADC2_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
#define ADC2_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
#define ADC2_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
#define ADC2_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
#define ADC2_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
#define ADC3_EXTSEL_T2CC1 ADC_CR2_EXTSEL_T2CC1
#define ADC3_EXTSEL_T2CC2 ADC_CR2_EXTSEL_T2CC2
#define ADC3_EXTSEL_T2CC3 ADC_CR2_EXTSEL_T2CC3
#define ADC3_EXTSEL_T2CC4 ADC_CR2_EXTSEL_T2CC4
#define ADC3_EXTSEL_T2TRGO ADC_CR2_EXTSEL_T2TRGO
# define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
# define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
# define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
# define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
# define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
# define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
# define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
# define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
# define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
# define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
# define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
# define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
# define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
# define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
# define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
#define ADC1_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
#define ADC1_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
#define ADC1_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
#define ADC1_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
#define ADC1_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
#define ADC2_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
#define ADC2_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
#define ADC2_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
#define ADC2_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
#define ADC2_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
#define ADC3_EXTSEL_T3CC1 ADC_CR2_EXTSEL_T3CC1
#define ADC3_EXTSEL_T3CC2 ADC_CR2_EXTSEL_T3CC2
#define ADC3_EXTSEL_T3CC3 ADC_CR2_EXTSEL_T3CC3
#define ADC3_EXTSEL_T3CC4 ADC_CR2_EXTSEL_T3CC4
#define ADC3_EXTSEL_T3TRGO ADC_CR2_EXTSEL_T3TRGO
# define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
# define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
# define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
# define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
# define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
# define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
# define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
# define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
# define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
# define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
# define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
# define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
# define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
# define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
# define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
#define ADC1_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
#define ADC1_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
#define ADC1_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
#define ADC1_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
#define ADC1_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
#define ADC2_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
#define ADC2_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
#define ADC2_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
#define ADC2_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
#define ADC2_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
#define ADC3_EXTSEL_T4CC1 ADC_CR2_EXTSEL_T4CC1
#define ADC3_EXTSEL_T4CC2 ADC_CR2_EXTSEL_T4CC2
#define ADC3_EXTSEL_T4CC3 ADC_CR2_EXTSEL_T4CC3
#define ADC3_EXTSEL_T4CC4 ADC_CR2_EXTSEL_T4CC4
#define ADC3_EXTSEL_T4TRGO ADC_CR2_EXTSEL_T4TRGO
# define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
# define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
# define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
# define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
# define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
# define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
# define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
# define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
# define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
# define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
# define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
# define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
# define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
# define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
# define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
#define ADC1_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
#define ADC1_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
#define ADC1_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
#define ADC1_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
#define ADC1_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
#define ADC2_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
#define ADC2_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
#define ADC2_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
#define ADC2_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
#define ADC2_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
#define ADC3_EXTSEL_T5CC1 ADC_CR2_EXTSEL_T5CC1
#define ADC3_EXTSEL_T5CC2 ADC_CR2_EXTSEL_T5CC2
#define ADC3_EXTSEL_T5CC3 ADC_CR2_EXTSEL_T5CC3
#define ADC3_EXTSEL_T5CC4 ADC_CR2_EXTSEL_T5CC4
#define ADC3_EXTSEL_T5TRGO ADC_CR2_EXTSEL_T5TRGO
# define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
# define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
# define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
# define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
# define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
# define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
# define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
# define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
# define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
# define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
# define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
# define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
# define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
# define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
# define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
# define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
# define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
# define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
# define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
# define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
# define ADC1_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
# define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
# define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
# define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
# define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
# define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
# define ADC2_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
# define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
# define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
# define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
# define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
# define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
# define ADC3_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#define ADC1_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
#define ADC1_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
#define ADC1_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
#define ADC1_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
#define ADC1_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
#define ADC2_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
#define ADC2_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
#define ADC2_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
#define ADC2_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
#define ADC2_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
#define ADC3_EXTSEL_T6CC1 ADC_CR2_EXTSEL_T6CC1
#define ADC3_EXTSEL_T6CC2 ADC_CR2_EXTSEL_T6CC2
#define ADC3_EXTSEL_T6CC3 ADC_CR2_EXTSEL_T6CC3
#define ADC3_EXTSEL_T6CC4 ADC_CR2_EXTSEL_T6CC4
#define ADC3_EXTSEL_T6TRGO ADC_CR2_EXTSEL_T6TRGO
#define ADC1_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
#define ADC1_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
#define ADC1_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
#define ADC1_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
#define ADC1_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
#define ADC1_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#define ADC2_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
#define ADC2_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
#define ADC2_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
#define ADC2_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
#define ADC2_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
#define ADC2_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#define ADC3_EXTSEL_T8CC1 ADC_CR2_EXTSEL_T8CC1
#define ADC3_EXTSEL_T8CC2 ADC_CR2_EXTSEL_T8CC2
#define ADC3_EXTSEL_T8CC3 ADC_CR2_EXTSEL_T8CC3
#define ADC3_EXTSEL_T8CC4 ADC_CR2_EXTSEL_T8CC4
#define ADC3_EXTSEL_T8TRGO ADC_CR2_EXTSEL_T8TRGO
#define ADC3_EXTSEL_T8TRGO2 ADC_CR2_EXTSEL_T8TRGO2
#if defined(CONFIG_STM32F7_TIM1_ADC1)
# if CONFIG_STM32F7_ADC1_TIMTRIG == 0
@ -729,7 +728,6 @@
* Public Types
************************************************************************************/
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
@ -744,7 +742,7 @@ extern "C"
#endif
/****************************************************************************
* Name: stm32_adcinitialize
* Name: stm32_adc_initialiize
*
* Description:
* Initialize the ADC.
@ -760,8 +758,9 @@ extern "C"
****************************************************************************/
struct adc_dev_s;
struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
int nchannels);
struct adc_dev_s *stm32_adc_initialiize(int intf,
FAR const uint8_t *chanlist,
int nchannels);
#undef EXTERN
#ifdef __cplusplus
}

501
arch/arm/src/stm32f7/stm32_i2c.c
View File

@ -726,7 +726,6 @@ static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
}
#endif
/************************************************************************************
* Name: stm32_i2c_sem_waitdone
*
@ -756,10 +755,10 @@ static inline int stm32_i2c_sem_waitdone(FAR struct stm32_i2c_priv_s *priv)
stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0,
(I2C_CR1_ALLINTS & ~I2C_CR1_TXRX));
/* Signal the interrupt handler that we are waiting */
/* Signal the interrupt handler that we are waiting */
priv->intstate = INTSTATE_WAITING;
do
priv->intstate = INTSTATE_WAITING;
do
{
/* Get the current time */
@ -1244,57 +1243,58 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
if (frequency != priv->frequency)
{
/* I2C peripheral must be disabled to update clocking configuration */
/* I2C peripheral must be disabled to update clocking configuration */
pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
if (pe)
{
stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
}
pe = (stm32_i2c_getreg32(priv, STM32F7_I2C_CR1_OFFSET) & I2C_CR1_PE);
if (pe)
{
stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, I2C_CR1_PE, 0);
}
/* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
digital off from STM32F0-F3_AN4235_V1.0.1 */
/* TODO: speed/timing calcs, at the moment 45Mhz = STM32_PCLK1_FREQUENCY, analog filter is on,
digital off from STM32F0-F3_AN4235_V1.0.1 */
if (frequency == 100000)
{
presc = 0x06;
scl_delay = 0x02;
sda_delay = 0x00;
scl_h_period = 0x1e;
scl_l_period = 0x2b;
if (frequency == 100000)
{
presc = 0x06;
scl_delay = 0x02;
sda_delay = 0x00;
scl_h_period = 0x1e;
scl_l_period = 0x2b;
}
else if (frequency == 400000)
{
presc = 0x00;
scl_delay = 0x0A;
sda_delay = 0x00;
scl_h_period = 0x1b;
scl_l_period = 0x5b;
}
else
{
presc = 0x00;
scl_delay = 0x08;
sda_delay = 0x00;
scl_h_period = 0x09;
scl_l_period = 0x1c;
}
}
else if (frequency == 400000)
{
presc = 0x00;
scl_delay = 0x0A;
sda_delay = 0x00;
scl_h_period = 0x1b;
scl_l_period = 0x5b;
}
else
{
presc = 0x00;
scl_delay = 0x08;
sda_delay = 0x00;
scl_h_period = 0x09;
scl_l_period = 0x1c;
}
uint32_t timingr =
(presc << I2C_TIMINGR_PRESC_SHIFT) |
(scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
(sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
(scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
(scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
uint32_t timingr =
(presc << I2C_TIMINGR_PRESC_SHIFT) |
(scl_delay << I2C_TIMINGR_SCLDEL_SHIFT) |
(sda_delay << I2C_TIMINGR_SDADEL_SHIFT) |
(scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
(scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
stm32_i2c_putreg32(priv, STM32F7_I2C_TIMINGR_OFFSET, timingr);
if (pe)
{
stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
}
priv->frequency = frequency;
if (pe)
{
stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
}
priv->frequency = frequency;
}
}
@ -1327,7 +1327,6 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
{
/* Flag the first byte as an address byte */
priv->astart = true;
@ -1371,15 +1370,18 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
* it otherwise.
*/
if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255) {
if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255)
{
i2cerr("RELOAD enabled: dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
priv->dcnt, priv->msgc);
stm32_i2c_enable_reload(priv);
} else {
}
else
{
i2cerr("RELOAD disable: dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
priv->dcnt, priv->msgc);
stm32_i2c_disable_reload(priv);
}
}
/* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of
* bytes in the current message or 255, whichever is lower so as to not
@ -1416,7 +1418,7 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
*/
i2cerr("Sending START: dcnt=%i msgc=%i flags=0x%04x\n",
priv->dcnt, priv->msgc, priv->flags);
priv->dcnt, priv->msgc, priv->flags);
stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR2_OFFSET, 0, I2C_CR2_START);
}
@ -1464,7 +1466,7 @@ static inline uint32_t stm32_i2c_getstatus(FAR struct stm32_i2c_priv_s *priv)
static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
{
stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
stm32_i2c_modifyreg32(priv, STM32F7_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK);
}
/************************************************************************************
@ -1487,8 +1489,7 @@ static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
uint32_t status;
uint32_t status;
/* Get state of the I2C controller */
@ -1545,19 +1546,17 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
/* NACK received on first (address) byte: address is invalid */
i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n",
priv->dcnt, priv->msgc, status);
priv->dcnt, priv->msgc, status);
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
}
}
else
{
/* NACK received on regular byte */
{
/* NACK received on regular byte */
i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n",
priv->dcnt, priv->msgc, status);
priv->dcnt, priv->msgc, status);
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
}
}
/* Set flags to terminate message transmission:
*
@ -1570,7 +1569,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
priv->dcnt = -1;
priv->msgc = 0;
}
/* Transmit Interrupt Status (TXIS) Handler
@ -1621,67 +1619,61 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
if (priv->astart == true)
{
i2cinfo("TXIS: Address Valid\n");
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr);
priv->astart = false;
i2cinfo("TXIS: Address Valid\n");
stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr);
priv->astart = false;
}
/* If one or more bytes in the current message are ready to transmit */
if (priv->dcnt > 0)
{
/* Prepare to transmit the current byte */
/* Prepare to transmit the current byte */
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr);
i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr);
/* Decrement byte counter */
/* Decrement byte counter */
priv->dcnt--;
priv->dcnt--;
/* If we are about to transmit the last byte in the current message */
/* If we are about to transmit the last byte in the current message */
if (priv->dcnt == 0) {
if (priv->dcnt == 0)
{
/* If this is also the last message to send, disable RELOAD so
* TC fires next and issues STOP condition. If we don't do this
* TCR will fire next, and since there are no bytes to send we
* can't write NBYTES to clear TCR so it will fire forever.
*/
/* If this is also the last message to send, disable RELOAD so
* TC fires next and issues STOP condition. If we don't do this
* TCR will fire next, and since there are no bytes to send we
* can't write NBYTES to clear TCR so it will fire forever.
*/
if ((priv->msgc - 1) == 0)
{
stm32_i2c_disable_reload(priv);
}
}
if ((priv->msgc - 1) == 0) {
/* Transmit current byte */
stm32_i2c_disable_reload(priv);
stm32_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr);
}
}
/* Transmit current byte */
stm32_i2c_putreg(priv, STM32F7_I2C_TXDR_OFFSET, *priv->ptr);
/* Advance to next byte */
priv->ptr++;
/* Advance to next byte */
priv->ptr++;
}
else
{
/* Unsupported state */
/* Unsupported state */
i2cerr("TXIS: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n",
priv->dcnt, status);
i2cerr("TXIS: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n",
priv->dcnt, status);
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
}
i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
}
/* Receive Buffer Not Empty (RXNE) State Handler
*
* This branch is only triggered when the RXNE interrupt occurs. This
@ -1725,9 +1717,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
/* If more bytes in the current message */
if (priv->dcnt > 0)
{
stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
{
stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
/* No interrupts or context switches may occur in the following
* sequence. Otherwise, additional bytes may be received.
@ -1740,36 +1731,33 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
*priv->ptr = stm32_i2c_getreg(priv, STM32F7_I2C_RXDR_OFFSET);
i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr);
i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr);
/* Advance buffer to the next byte in the message */
/* Advance buffer to the next byte in the message */
priv->ptr++;
priv->ptr++;
/* Signal byte received */
/* Signal byte received */
priv->dcnt--;
#ifdef CONFIG_I2C_POLLED
leave_critical_section(state);
#endif
}
else
{
/* Unsupported state */
/* Unsupported state */
stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
status = stm32_i2c_getreg(priv, STM32F7_I2C_ISR_OFFSET);
i2cerr("RXNE: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n",
priv->dcnt, status);
priv->dcnt, status);
/* Set signals that will terminate ISR and wake waiting thread */
priv->dcnt = -1;
priv->msgc = 0;
}
i2cinfo("RXNE: EXIT dcnt = %i msgc = %i status 0x%08x\n",
@ -1807,63 +1795,61 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else if ((status & I2C_ISR_TC) != 0)
{
i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
i2cinfo("TC: ENTER dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
/* Prior message has been sent successfully */
/* Prior message has been sent successfully */
priv->msgc--;
priv->msgc--;
/* if additional messages remain to be transmitted / received */
/* if additional messages remain to be transmitted / received */
if (priv->msgc > 0) {
if (priv->msgc > 0)
{
i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n",
priv->dcnt, priv->msgc);
stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc);
i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n",
priv->dcnt, priv->msgc);
stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc);
/* Issue a START condition.
*
* Note that the first thing sendstart does is update the
* private structure "current message" data (ptr, dcnt, flags)
* so they all reflect the next message in the list so we
* update msgv before we get there.
*/
/* Issue a START condition.
*
* Note that the first thing sendstart does is update the
* private structure "current message" data (ptr, dcnt, flags)
* so they all reflect the next message in the list so we
* update msgv before we get there.
*/
/* Advance to the next message in the list */
/* Advance to the next message in the list */
priv->msgv++;
priv->msgv++;
stm32_i2c_sendstart(priv);
stm32_i2c_sendstart(priv);
}
else
{
/* Issue a STOP conditions.
*
* No additional messages to transmit / receive, so the
* transfer is indeed complete. Nothing else to do but
* issue a STOP and exit.
*/
} else {
i2cinfo("TC: STOP: dcnt=%i msgc=%i\n",
priv->dcnt, priv->msgc);
stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt);
/* Issue a STOP conditions.
*
* No additional messages to transmit / receive, so the
* transfer is indeed complete. Nothing else to do but
* issue a STOP and exit.
*/
stm32_i2c_sendstop(priv);
i2cinfo("TC: STOP: dcnt=%i msgc=%i\n",
priv->dcnt, priv->msgc);
stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt);
/* Set signals that will terminate ISR and wake waiting thread */
stm32_i2c_sendstop(priv);
/* Set signals that will terminate ISR and wake waiting thread */
priv->dcnt = -1;
priv->msgc = 0;
}
i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
priv->dcnt = -1;
priv->msgc = 0;
}
i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
}
/* Transfer Complete (Reload) State Handler
*
* This branch is only triggered when the TCR interrupt occurs. This
@ -1901,94 +1887,94 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else if ((status & I2C_ISR_TCR) != 0)
{
i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
i2cinfo("TCR: ENTER dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
/* If no more bytes in the current message to transfer */
/* If no more bytes in the current message to transfer */
if (priv->dcnt == 0) {
if (priv->dcnt == 0)
{
/* Prior message has been sent successfully */
/* Prior message has been sent successfully */
priv->msgc--;
priv->msgc--;
/* Advance to the next message in the list */
/* Advance to the next message in the list */
priv->msgv++;
priv->msgv++;
/* Update current message data */
/* Update current message data */
priv->ptr = priv->msgv->buffer;
priv->dcnt = priv->msgv->length;
priv->flags = priv->msgv->flags;
priv->ptr = priv->msgv->buffer;
priv->dcnt = priv->msgv->length;
priv->flags = priv->msgv->flags;
/* if this is the last message, disable reload so the
* TC event fires next time */
/* if this is the last message, disable reload so the
* TC event fires next time */
if (priv->msgc == 0)
{
i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
if (priv->msgc == 0) {
i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
stm32_i2c_disable_reload(priv);
}
stm32_i2c_disable_reload(priv);
}
/* Update NBYTES with length of current message */
/* Update NBYTES with length of current message */
i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
}
else
{
/* More bytes in the current (greater than 255 byte payload
* length) message, so set NBYTES according to the bytes
* remaining in the message, up to a maximum each cycle of 255.
*/
stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
if (priv->dcnt > 255)
{
i2cinfo("TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
} else {
/* More than 255 bytes to transfer so the RELOAD bit is
* set in order to generate a TCR event rather than a TC
* event when 255 bytes are successfully transferred.
* This forces us to return here to update NBYTES and
* continue until NBYTES is set to less than 255 bytes,
* at which point RELOAD will be disabled and a TC
* event will (eventually) follow to officially terminate
* the transfer.
*/
/* More bytes in the current (greater than 255 byte payload
* length) message, so set NBYTES according to the bytes
* remaining in the message, up to a maximum each cycle of 255.
*/
stm32_i2c_enable_reload(priv);
if (priv->dcnt > 255) {
stm32_i2c_set_bytes_to_transfer(priv, 255);
}
else
{
/* Less than 255 bytes left to transfer, which means we'll
* complete the transfer of all bytes in the current message
* the next time around.
*
* This means we need to disable the RELOAD functionality so
* we receive a TC event next time which will allow us to
* either RESTART and continue sending the contents of the
* next message or send a STOP condition and exit the ISR.
*/
i2cinfo("TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
/* More than 255 bytes to transfer so the RELOAD bit is
* set in order to generate a TCR event rather than a TC
* event when 255 bytes are successfully transferred.
* This forces us to return here to update NBYTES and
* continue until NBYTES is set to less than 255 bytes,
* at which point RELOAD will be disabled and a TC
* event will (eventually) follow to officially terminate
* the transfer.
*/
stm32_i2c_disable_reload(priv);
stm32_i2c_enable_reload(priv);
stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
}
stm32_i2c_set_bytes_to_transfer(priv, 255);
} else {
/* Less than 255 bytes left to transfer, which means we'll
* complete the transfer of all bytes in the current message
* the next time around.
*
* This means we need to disable the RELOAD functionality so
* we receive a TC event next time which will allow us to
* either RESTART and continue sending the contents of the
* next message or send a STOP condition and exit the ISR.
*/
i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n",
priv->dcnt, priv->msgc);
stm32_i2c_disable_reload(priv);
stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
}
i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
}
i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n",
priv->dcnt, priv->msgc, status);
}
}
/* Empty call handler
@ -2080,7 +2066,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
priv->intstate = INTSTATE_DONE;
}
#endif
}
status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
@ -2172,7 +2157,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
}
#ifndef CONFIG_I2C_POLLED
/* Attach error and event interrupts to the ISRs */
irq_attach(priv->config->ev_irq, priv->config->isr);
@ -2231,7 +2215,6 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
return OK;
}
/************************************************************************************
* Name: stm32_i2c_process
*
@ -2283,7 +2266,6 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
priv->status = 0;
#ifndef CONFIG_I2C_POLLED
/* Enable transmit and receive interrupts here so when we send the start
* condition below the ISR will fire if the data was sent and some
* response from the slave received. All other interrupts relevant to
@ -2345,11 +2327,11 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
/* Check for error status conditions */
if ((status & (I2C_INT_BERR |
I2C_INT_ARLO |
I2C_INT_OVR |
I2C_INT_PECERR |
I2C_INT_TIMEOUT |
I2C_INT_NACK)) != 0)
I2C_INT_ARLO |
I2C_INT_OVR |
I2C_INT_PECERR |
I2C_INT_TIMEOUT |
I2C_INT_NACK)) != 0)
{
/* one or more errors in the mask are present */
@ -2358,7 +2340,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
{
/* Bus Error, ignore it because of errata (revision A,Z) */
i2cerr("I2C: Bus Error\n");
i2cerr("I2C: Bus Error\n");
/* errval = EIO; */
}
@ -2366,7 +2348,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
{
/* Arbitration Lost (master mode) */
i2cerr("I2C: Arbitration Lost\n");
i2cerr("I2C: Arbitration Lost\n");
errval = EAGAIN;
}
@ -2374,43 +2356,43 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
{
/* Overrun/Underrun */
i2cerr("I2C: Overrun/Underrun\n");
i2cerr("I2C: Overrun/Underrun\n");
errval = EIO;
}
else if (status & I2C_INT_PECERR)
{
/* PEC Error in reception (SMBus Only) */
/* PEC Error in reception (SMBus Only) */
i2cerr("I2C: PEC Error\n");
i2cerr("I2C: PEC Error\n");
errval = EPROTO;
}
else if (status & I2C_INT_TIMEOUT)
{
/* Timeout or Tlow Error (SMBus Only) */
i2cerr("I2C: Timeout / Tlow Error\n");
i2cerr("I2C: Timeout / Tlow Error\n");
errval = ETIME;
}
else if (status & I2C_INT_NACK)
{
/* NACK Received, flag as "communication error on send" */
if (priv->astart == TRUE)
{
i2cerr("I2C: Address NACK\n");
errval = EADDRNOTAVAIL;
}
else
{
i2cerr("I2C: Data NACK\n");
errval = ECOMM;
/* NACK Received, flag as "communication error on send" */
if (priv->astart == TRUE)
{
i2cerr("I2C: Address NACK\n");
errval = EADDRNOTAVAIL;
}
else
{
i2cerr("I2C: Data NACK\n");
errval = ECOMM;
}
}
}
else
{
/* Unrecognized error */
/* Unrecognized error */
i2cerr("I2C: Unrecognized Error");
i2cerr("I2C: Unrecognized Error");
errval = EINTR;
}
}
@ -2423,7 +2405,6 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
else if ((status & I2C_ISR_BUSY) != 0)
{
/* I2C Bus Busy
*
* This is a status condition rather than an error.
@ -2440,13 +2421,14 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
while(status & I2C_ISR_BUSY)
{
if((clock_systimer() - start) > timeout)
{
i2cerr("I2C: Bus busy");
errval = EBUSY;
break;
}
status = stm32_i2c_getstatus(priv);
if((clock_systimer() - start) > timeout)
{
i2cerr("I2C: Bus busy");
errval = EBUSY;
break;
}
status = stm32_i2c_getstatus(priv);
}
}
@ -2713,5 +2695,4 @@ out:
}
#endif /* CONFIG_I2C_RESET */
#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || CONFIG_STM32F7_I2C3 */

1
configs/stm32f746-ws/src/stm32_boot.c
View File

@ -75,7 +75,6 @@ void stm32_boardinitialize(void)
stm32_spidev_initialize();
}
#endif
}
/************************************************************************************

17
configs/stm32f746-ws/src/stm32_spi.c
View File

@ -57,23 +57,6 @@
defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#ifdef CONFIG_DEBUG_SPI
# define spidbg lldbg
# ifdef SPI_VERBOSE
# define spivdbg lldbg
# else
# define spivdbg(x...)
# endif
#else
# undef SPI_VERBOSE
# define spidbg(x...)
# define spivdbg(x...)
#endif
/************************************************************************************
* Public Functions
************************************************************************************/